JPH0214779B2 - - Google Patents
Info
- Publication number
- JPH0214779B2 JPH0214779B2 JP57199203A JP19920382A JPH0214779B2 JP H0214779 B2 JPH0214779 B2 JP H0214779B2 JP 57199203 A JP57199203 A JP 57199203A JP 19920382 A JP19920382 A JP 19920382A JP H0214779 B2 JPH0214779 B2 JP H0214779B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- substrate
- protrusion
- protrusions
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052751 metal Inorganic materials 0.000 claims description 86
- 239000002184 metal Substances 0.000 claims description 86
- 238000000034 method Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000005304 joining Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 241000587161 Gomphocarpus Species 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体素子上の電極と外部リードとを
接合する場合の金属リードへの金属突起物形成方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming metal protrusions on metal leads when bonding electrodes on a semiconductor element and external leads.
従来例の構成とその問題点
近年、IC、LSI等の半導体素子は各種の家庭電
化製品、、産業用機器の分野へ導入されている。
これら家庭電化製品、産業用機器は省資源化、省
電力化のためにあるいは利用範囲を拡大させるた
めに、小型化、薄型化のいわゆるポータブル化が
促進されている。Conventional configurations and their problems In recent years, semiconductor elements such as ICs and LSIs have been introduced into the fields of various home appliances and industrial equipment.
These home appliances and industrial equipment are being made smaller and thinner, so-called portable, in order to save resources and power, or to expand the scope of their use.
半導体素子においてもポータブル化に対応する
ために、パツケージングの小型化、薄型化が要求
されてきている。拡散工程、電極配線工程の終了
したシリコンスライスは半導体素子単位のチツプ
に切断され、チツプの周辺に設けられたアルミ電
極端子から外部端子へ電極リードを取出して取扱
いやすくしまた機械的保護のためにパツケージン
グされる。通常、これら半導体素子のパツケージ
ングにはDIL、チツプキヤリヤ、テープキヤリヤ
方式等が用いられている。この中で接続箇所の信
頼性が高く、小型化、薄型化のパツケージングを
提供できるものとして、テープキヤリヤ方式があ
る。テープキヤリヤ方式による半導体素子のパツ
ケージングは半導体素子上の電極端子上にバリヤ
メタルと呼ばれる多層金属膜を設け、さらに、こ
の多層金属膜上に電気メツキ法により金属突起を
設ける。そして、一定幅の長尺のポリイミドテー
プ上に金属リード端子を設け、半導体素子の電極
端子上の金属突起とリード端子とを、電極端子数
に無関係に同時に一括接続するものである。 In order to make semiconductor devices portable, there has been a demand for smaller and thinner packaging. After the diffusion process and electrode wiring process have been completed, the silicon slice is cut into chips for each semiconductor element, and electrode leads are taken out from the aluminum electrode terminals provided around the chip to external terminals for ease of handling and for mechanical protection. packaged. Usually, DIL, chip carrier, tape carrier methods, etc. are used for packaging these semiconductor devices. Among these, the tape carrier method is one that has high reliability at connection points and can provide smaller, thinner packaging. In packaging a semiconductor device using the tape carrier method, a multilayer metal film called a barrier metal is provided on the electrode terminals on the semiconductor device, and metal protrusions are further provided on this multilayer metal film by electroplating. Then, metal lead terminals are provided on a long polyimide tape of a constant width, and the metal protrusions on the electrode terminals of the semiconductor element and the lead terminals are simultaneously connected all at once regardless of the number of electrode terminals.
しかしながら従来のテープキヤリヤ方式も種々
の問題を含んでいる。そこで本発明者らは特願昭
56−37499号においてテープキヤリヤ方式を基本
にした新規なる接合方法（以下転写バンプ方式と
呼称する）を提案した。 However, conventional tape carrier systems also include various problems. Therefore, the inventors of the present invention
In No. 56-37499, we proposed a new bonding method (hereinafter referred to as the transfer bump method) based on the tape carrier method.
この発明の主な特徴は半導体素子上に金属突起
を形成する必要がないとともに、さらに金属突起
を転写方式により金属リード側に形成することに
ある。 The main feature of the present invention is that there is no need to form metal protrusions on the semiconductor element, and furthermore, the metal protrusions are formed on the metal lead side by a transfer method.
第１図をもとにして本発明者らが先に提案した
上記発明の一実施例の方法をのべる。 Based on FIG. 1, a method according to an embodiment of the above invention previously proposed by the present inventors will be described.
まず長尺のポリイミイド樹脂テープ２１上に電
極リード２２が形成される。電極リード２２は例
えば35μｍ厚さのGu箔に0.2〜1.0μｍ程度のSnメ
ツキを施こしたもので、通常のフイルムキヤリヤ
方式に用いる構成と同一のものである。次に基板
２３上に金属リード２２の間隔と同一寸法に金属
突起２４が電解メツキ法で形成される（第１図
ａ）。 First, electrode leads 22 are formed on a long polyimide resin tape 21 . The electrode lead 22 is made of, for example, a 35 .mu.m thick Gu foil plated with Sn to a thickness of about 0.2 to 1.0 .mu.m, and has the same structure as that used in a normal film carrier system. Next, metal protrusions 24 are formed on the substrate 23 by electrolytic plating to have the same dimensions as the spacing between the metal leads 22 (FIG. 1a).
金属突起２４と金属リード２２とを位置合せ
し、ツール２６で矢印２７のごとく加熱、加圧す
れば（第１図ｂ）、仮に金属突起２４がAuで構成
されておれば、金属リード２２に形成されてい
る。Snと共晶を起こし、完全な接合を得ること
ができる。加圧２７を取り去れば、金属突起２４
は基板２３側から剥離され、金属リード２２に接
合された状態となる（第１図ｃ）。第１図ｃの状
態は基板２３の金属突起２４を、金属リード２２
側に転写したことになる。 If the metal protrusion 24 and the metal lead 22 are aligned and heated and pressurized as shown by the arrow 27 using the tool 26 (FIG. 1b), if the metal protrusion 24 is made of Au, the metal lead 22 will be It is formed. A perfect bond can be obtained by forming eutectic formation with Sn. If the pressure 27 is removed, the metal protrusion 24
is peeled off from the substrate 23 side and joined to the metal lead 22 (FIG. 1c). In the state shown in FIG. 1c, the metal protrusion 24 of the substrate 23 is
This means that it has been transferred to the side.
次に半導体素子２５上のアルミニウム電極２８
に金属突起２４を位置合せし、ツール２６′で２
７′のごとく加熱、加圧する（第１図ｄ）。この動
作により、金属突起２４のAuと半導体素子２５
上のアルミニウム電極２８とは合金化し、完全な
接合を得ることができる。この状態を第１図ｅに
示した。 Next, the aluminum electrode 28 on the semiconductor element 25
Align the metal protrusion 24 with the
Heat and pressurize as shown in step 7' (Fig. 1d). By this operation, the Au of the metal protrusion 24 and the semiconductor element 25
It can be alloyed with the upper aluminum electrode 28 to obtain a perfect bond. This state is shown in FIG. 1e.
この第１図の方法において、金属リード２２の
間隔、基板２３上に形成した金属突起２４の間隔
さらに半導体素子２５上のアルミニウム電極２８
の間隔は同一値である。 In the method shown in FIG.
The intervals of are the same value.
以上のべた本発明者らが先に提案した方法は通
常用いられているフイルムキヤリヤのリードに、
別の基板上に形成した金属突起とを接合せしめ、
この段階でリードに金属突起を転写するものであ
る。そしてリードに形成された金属突起は半導体
素子上のアルミニウム電極と容易に接合される。 The method previously proposed by the inventors described above is based on the lead of the commonly used film carrier.
Joining metal protrusions formed on another substrate,
At this stage, the metal protrusions are transferred to the leads. The metal protrusions formed on the leads are easily joined to aluminum electrodes on the semiconductor element.
この方式は、基本的にはネイルヘツドのワイヤ
ボンデイングの金ボールを一括して多数個、同時
に接合せんとする思想である。本発明者らは、こ
の方式において半導体側と接する金属突起の形状
が平均であると、半導体側のアルミニウム電極上
の酸化物の除去が不充分となり、接合が不完全に
なり信頼性が問題となりやすいという欠点がある
ことを見い出した。又、前記金属リードと接する
側の金属突起の面は平担である方が加圧時に前記
金属リードと金属突起の滑りが少なく、確実な接
合が得られることを見い出した。 This method is basically based on the idea of simultaneously bonding a large number of gold balls for nail head wire bonding. The inventors found that in this method, if the shape of the metal protrusion in contact with the semiconductor side is average, the removal of oxide on the aluminum electrode on the semiconductor side will be insufficient, resulting in incomplete bonding and reliability problems. I found out that it has the disadvantage of being easy to use. It has also been found that when the surface of the metal protrusion in contact with the metal lead is flat, there is less slippage between the metal lead and the metal protrusion when pressure is applied, and a more reliable bond can be obtained.
発明の目的
本発明はこのような従来の問題に鑑み、金属リ
ードへ転写される金属突起の形状を接合に適した
形状にして、金属突起と半導体素子上の電極との
接合をより確実に実施し、接合の信頼性をより高
めた金属リードへの金属突起物形成方法を提供す
ることを目的とする。Purpose of the Invention In view of these conventional problems, the present invention provides a method for making the shape of the metal protrusion transferred to the metal lead suitable for bonding, thereby more reliably bonding the metal protrusion and the electrode on the semiconductor element. An object of the present invention is to provide a method for forming metal protrusions on a metal lead with higher bonding reliability.
発明の構成
金属リードへの金属突起物形成方法において、
金属突起を形成する基板に半球形状の凹部を設け
た構成であつて、前記凹部上に前記金属突起を形
成することを特徴とするものである。この方法に
より、金属突起の半導体素子上の電極と接すべき
面は平担とならず、その形状は凹部の形状に応じ
て半球形等にすることができるものである。Structure of the Invention In a method for forming metal protrusions on a metal lead,
The present invention is characterized in that a hemispherical recess is provided on a substrate on which a metal protrusion is to be formed, and the metal protrusion is formed on the recess. By this method, the surface of the metal protrusion that should be in contact with the electrode on the semiconductor element is not flat, and its shape can be made into a hemispherical shape or the like depending on the shape of the recess.
実施例の説明
第２図ａ，ｂは本発明の実施例の金属リードへ
の金属突起物形成方法で用いる基板の形状を示し
ている。これらの図において基板３１，３１′上
の金属突起を形成する位置にそれぞれ凹部３２，
３２′形成する。第２図ａはＶ形の溝、ｂは半球
形の溝を有しており、凹部の溝は、光蝕刻法や、
機械加工法によつて形成し、溝の深さは、例え
ば、20〜40μｍ程度に設けるものである。DESCRIPTION OF EMBODIMENTS FIGS. 2a and 2b show the shape of a substrate used in the method of forming metal protrusions on metal leads according to an embodiment of the present invention. In these figures, recesses 32 and 32 are formed on the substrates 31 and 31' at positions where metal protrusions are to be formed, respectively.
Form 32'. Figure 2 a has a V-shaped groove, and b has a hemispherical groove.
The grooves are formed by a machining method, and the depth of the grooves is, for example, about 20 to 40 μm.
次に第２図ａの基板に関して説明すると、第３
図ａに示すように、全面にAu、Cu、Ni、Pd、
Pt等の金属膜３２を形成し、電解メツキ法、ス
クリーン印刷法等により金属突起３４を前記凹部
３２上に形成させる。 Next, to explain about the board of FIG. 2a, the third
As shown in figure a, Au, Cu, Ni, Pd,
A metal film 32 of Pt or the like is formed, and metal protrusions 34 are formed on the recesses 32 by electrolytic plating, screen printing, or the like.
この様にして形成された金属突起の形状は第２
図ａの如くのＶ溝をもつ基板を用いれば第４図ａ
の様に三角錐状部４０をもつ金属突起３４を得る
ことができる。また第２図ｂの如くの半球形の溝
を有する基板を用いれば、第４図ｂの様に半球状
４０′の金属突起３４′を得ることができる。一
方、基板と接していない金属突起の反対面は、平
らな形状４１，４１′に形成するものである。 The shape of the metal protrusion formed in this way is the second
If a substrate with a V-groove as shown in Figure a is used, Figure 4
A metal protrusion 34 having a triangular pyramidal portion 40 can be obtained as shown in FIG. Further, by using a substrate having hemispherical grooves as shown in FIG. 2b, it is possible to obtain metal protrusions 34' having a hemispherical shape 40' as shown in FIG. 4b. On the other hand, the opposite surface of the metal protrusion that is not in contact with the substrate is formed into a flat shape 41, 41'.
なお、第３図ｂに示すように凹部３１を形成し
た基板３１と金属膜３３との間に樹脂層３５を設
けた構成が他の実施例として考えられ、この様な
構成にすると、前記金属突起３４を金属リードに
接合（転写）する際の熱が基板３１側に流出し、
接合温度を急激に減少せしめるのを防いだり、あ
るいは、前記樹脂層３５が緩衡剤となり加圧によ
つて基板が損傷するのを防ぐことができる。した
がつて、安定で、かつ確実なる金属突起の金属リ
ードへの接合（転写）を得ることができる。 In addition, as shown in FIG. 3b, a configuration in which a resin layer 35 is provided between the substrate 31 in which the recessed portion 31 is formed and the metal film 33 can be considered as another embodiment. Heat when bonding (transferring) the protrusion 34 to the metal lead flows out to the substrate 31 side,
It is possible to prevent a sudden decrease in the bonding temperature, or the resin layer 35 can act as a buffer to prevent damage to the substrate due to pressurization. Therefore, stable and reliable bonding (transfer) of the metal protrusion to the metal lead can be achieved.
更に本発明の金属突起物形成方法で用いる基板
において、第２図ａ，ｂに示す凹部３２，３２′
が設けられた基板３１，３１′は、金属突起が電
解メツキ法で形成されるものならば導電性部材を
用い、直接、前記凹部３２，３２′上に金属突起
を形成しても良いし、スクリーン印刷法等で前記
金属突起を形成するものであるならば、絶縁部
材、導電部材のいずれも用いることができる。こ
の様に基板と接する側の金属突起は半球形状とな
り、反対面の金属突起は平らに形成される。 Furthermore, in the substrate used in the method for forming metal protrusions of the present invention, recesses 32, 32' shown in FIGS.
If the substrates 31 and 31' provided with the metal protrusions are formed by electrolytic plating, the metal protrusions may be formed directly on the recesses 32 and 32' using a conductive member; Either an insulating member or a conductive member can be used as long as the metal protrusion is formed by a screen printing method or the like. In this way, the metal protrusion on the side that contacts the substrate has a hemispherical shape, and the metal protrusion on the opposite side is formed flat.
いずれにせよ前述した方法であれば、工数が短
縮されるので著じるしく安い基板を提供できるも
のである。 In any case, the above-described method reduces the number of man-hours and makes it possible to provide a significantly cheaper substrate.
発明の効果
以上の様に本発明の金属リードへの金属突起物
形成方法は、基板に凹部を設けることにより、半
導体素子の電極に接合するのに好適な半球状等の
金属突起を得ることができる。Effects of the Invention As described above, the method for forming a metal protrusion on a metal lead of the present invention makes it possible to obtain a hemispherical metal protrusion suitable for bonding to an electrode of a semiconductor element by providing a recess in a substrate. can.
すなわち、転写バンプ方式により金属リードの
先端に接合した本発明で用いる基板により形成さ
れた金属突起は、半導体素子上の電極に接し、加
圧、加熱された際、半球等の金属突起の先端は突
がつた形状をしているために、前記電極上の表面
に形成されている薄い酸化物層を容易に除去でき
る。このために安定で、確実な、信頼性の高い一
括接合を得ることができる。 That is, the metal protrusion formed by the substrate used in the present invention, which is bonded to the tip of the metal lead by the transfer bump method, comes into contact with the electrode on the semiconductor element, and when pressurized and heated, the tip of the hemispherical metal protrusion, etc. Due to the pointed shape, the thin oxide layer formed on the surface of the electrode can be easily removed. For this reason, stable, reliable, and highly reliable batch bonding can be obtained.
又、基板と接していない反対面の金属突起が平
担に形成されているから、前記平担な金属突起側
に金属リードを位置合せ加圧しても、金属リード
が、前記金属突起より滑り、位置づれを発生せし
めたり、これによる不充分な接合を発生させる事
がない、すなわち、加圧時に前記金属リードは金
属突起の平らな部分を充分に、確実に圧すること
ができる。したがつて、著じるしく信頼性の高い
接合を得ることができるものである。 Furthermore, since the metal protrusions on the opposite side that are not in contact with the substrate are formed flat, even if the metal leads are aligned and pressed against the flat metal protrusions, the metal leads will not slip from the metal protrusions. There is no possibility of misalignment or insufficient bonding due to the occurrence of misalignment, that is, the metal lead can sufficiently and reliably press the flat portion of the metal protrusion when pressurized. Therefore, it is possible to obtain a bond with significantly high reliability.
このように本発明の方法における基板を用い
て、形成した金属突起は、一方が半円球状等の形
状をし、他方が平らな面を有しているから、丁
度、ワイヤボンデイングのネイルヘツドの金ボー
ルの熱圧着接合を一括して接合するに理想的な金
属突起の形状と加圧の状態を得ることが出来るも
のである。 As described above, the metal protrusions formed using the substrate according to the method of the present invention have a shape such as a semicircle on one side and a flat surface on the other side, so they are just like the metal protrusions of a nail head in wire bonding. This makes it possible to obtain the ideal metal protrusion shape and pressurizing condition for batch bonding of balls by thermocompression bonding.
第１図ａ〜ｅは本発明者らがすでに提案した転
写バンプ方式を示す製造工程断面図、第２図ａ，
ｂは本発明の金属突起物形成方法で用いる基板の
実施例を示す断面図、第３図ａ，ｂはそれぞれ本
発明の実施例の方法により基板上に金属突起を形
成した状態を示す断面図、第４図ａ，ｂは本発明
の実施例の方法で用いる金属突起の断面図であ
る。
３１，３１′……基板、３２，３２′……凹部、
３３……金属膜、３４，３４′……金属突起、３
５……樹脂層。
Figures 1a to 1e are cross-sectional views of the manufacturing process showing the transfer bump method already proposed by the present inventors, and Figures 2a,
FIG. 3b is a sectional view showing an embodiment of a substrate used in the method of forming metal protrusions of the present invention, and FIGS. , FIGS. 4a and 4b are cross-sectional views of metal protrusions used in the method of the embodiment of the present invention. 31, 31'...Substrate, 32, 32'...Concavity,
33...Metal film, 34, 34'...Metal protrusion, 3
5...Resin layer.
Claims (1)
接合し、前記基板より前記金属突起を分離した
後、前記金属リードに接合した金属突起と半導体
素子上の電極とを加圧、加熱して接合する方法に
おいて、前記基板の主面に複数の凹部が設けられ
前記凹部に前記金属突起が形成されるとともに前
記凹部の内面が半球形状の空間部を形成してなる
ことを特徴とする金属リードへの金属突起物形成
方法。1. After joining a metal protrusion formed on a substrate to a metal lead and separating the metal protrusion from the substrate, the metal protrusion bonded to the metal lead and the electrode on the semiconductor element are bonded by applying pressure and heating. In the method, a plurality of recesses are provided on the main surface of the substrate, the metal protrusions are formed in the recesses, and an inner surface of the recess forms a hemispherical space. A method for forming metal protrusions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57199203A JPS5988860A (en) | 1982-11-12 | 1982-11-12 | Formation of metallic projection to metallic lead |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57199203A JPS5988860A (en) | 1982-11-12 | 1982-11-12 | Formation of metallic projection to metallic lead |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5988860A JPS5988860A (en) | 1984-05-22 |
| JPH0214779B2 true JPH0214779B2 (en) | 1990-04-10 |
Family
ID=16403851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57199203A Granted JPS5988860A (en) | 1982-11-12 | 1982-11-12 | Formation of metallic projection to metallic lead |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5988860A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917707A (en) | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
| US6624648B2 (en) | 1993-11-16 | 2003-09-23 | Formfactor, Inc. | Probe card assembly |
| JP3387930B2 (en) * | 1994-11-15 | 2003-03-17 | フォームファクター，インコーポレイテッド | Method of mounting a spring element on a semiconductor device and testing at a wafer level |
| DE69635083T2 (en) * | 1995-05-26 | 2006-05-18 | Formfactor, Inc., Livermore | PREPARATION OF COMPOUNDS AND APPARATUSES USING A SURGERY SUBSTRATE |
| US6441315B1 (en) | 1998-11-10 | 2002-08-27 | Formfactor, Inc. | Contact structures with blades having a wiping motion |
| US7084650B2 (en) | 2002-12-16 | 2006-08-01 | Formfactor, Inc. | Apparatus and method for limiting over travel in a probe card assembly |
| US7528618B2 (en) | 2006-05-02 | 2009-05-05 | Formfactor, Inc. | Extended probe tips |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56147680A (en) * | 1980-04-16 | 1981-11-16 | Kurita Water Ind Ltd | Treatment of waste water |
-
1982
- 1982-11-12 JP JP57199203A patent/JPS5988860A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56147680A (en) * | 1980-04-16 | 1981-11-16 | Kurita Water Ind Ltd | Treatment of waste water |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5988860A (en) | 1984-05-22 |
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