JPH02147263A - Head driving ic - Google Patents

Abstract

PURPOSE:To increase the speed of gradation recording due to a density pattern method by mounting function for binarizing the gradation data of an image signal according to the density pattern method in a driving IC. CONSTITUTION:A head driving IC stores an inputted image signal in a line memory 5 and reads the gradation data stored in said memory 5 and a density pattern matrix is selected by a density pattern generating means 7 and selects the certain row from inputted position data in a sub-scanning direction to determine binarized data which are, in turn, outputted parallelly. The parallelly inputted binarized data are subjected to series/parallel conversion by the shift registers 4 respectively connected to said data and stored in a latch 3 by an inputted STB signal. A driver selectively drives a recording body corresponding to the output of the latch to finish the recording on that line of a recording apparatus.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention is a recording device that originally performs binary recording, in which gradation information is binarized using a density pattern method and multi-gradation expression is performed using an area gradation method. The present invention relates to a head drive IC that can be widely applied to electrophotographic recording devices using LED arrays and liquid crystal shutter arrays, thermal transfer recording devices, and the like.

Conventional technology Originally, in order to record multi-gradation image signals in a recording device that performs binary recording, there is an area gradation method that expresses halftones by varying the number of recorded dots, and there are also various density pattern methods. It is described in literature, etc. (For example, gradation and color reproduction method in hard copy 1 Journal of Television Society V
o137) Problems to be solved by the invention However, when expressing halftones using the density pattern method, one pixel is expressed by multiple dots, so as the number of gradations increases, the matrix size for expressing one pixel also increases. It is necessary to transfer recording information for the number of lines of the recording device determined by the density pattern matrix size for each line of the image signal. For example, a 6-bit gradation signal (64 gradations) is transferred to an 8 x 8 density pattern. When expressed in a matrix, if one line of the image signal has 256 pixels, one line of the recording device has 2048 dots, and it is necessary to transfer 8 lines of 2048 dots. Therefore, in order to solve the problem of long recording times due to limitations in the speed of drive circuits and memory, the recording speed can be shortened by installing multiple processing circuits and performing data transfer in parallel. There is a problem in that the peripheral circuitry becomes large-scale and the cost increases.

In view of the above problems, the present invention provides a head drive IC with a function of binarizing the gradation information of an image signal using a density pattern method.
The purpose of this is to speed up gradation recording using the density pattern method and to perform recording without increasing the size of peripheral circuits.

Means for Solving the Problems In order to solve the above problems, the head drive IC of the first invention includes a line buffer for storing 1tJ information, and a line buffer that stores 1tJ information.
A density pattern generating means for outputting a value D, a plurality of shift registers connected to the output of the density pattern generating means, a latch for storing the output of the shift register, and a recording medium using the output of the latch. It is characterized by having a driver that is driven by electricity.

In addition, in order to solve the above problems, the head drive IC of the second invention includes a line buffer that stores gradation information, and a threshold that outputs a threshold according to input positional information in the main scanning direction and sub-scanning direction. a storage means, a comparison means for comparing the gradation information of the line buffer and the output of the threshold value storage means, a shift register for serial-to-parallel conversion of the output of the comparison means, and a latch for storing the output of the shift register;
The present invention is characterized in that it includes a driver that energizes and drives the recording body using the output of this latch.

Operation The head drive IC according to the first aspect of the invention has the above-mentioned configuration, stores the input image signal in the line buffer inside the IC, reads out the gradation information stored in this line buffer, and performs gradation based on this gradation information. The density pattern generation means selects a density pattern matrix according to the tone, determines the binary data by selecting the column of the density pattern matrix from the input position information in the sub-scanning direction, and generates the binary data. Output in parallel.

The binary data output in parallel is converted into serial/parallel data by the shift registers connected to each, and the input STB
The signal is stored in the latch. Then, the driver selectively drives the recording medium in accordance with the output of the latch to finish recording on that line of the recording apparatus.

In the next line of the recording device, the tone information is read out from the line buffer again, and the density pattern generation means selects the same density pattern matrix for a certain pixel as in the previous line, but the input position information in the sub-scanning direction changes. Therefore, binary data is determined according to the position information. By repeating the same operation a number of times corresponding to the number of lines determined by the size of the density button matrix, recording of one line of the image signal is completed.

In addition, in the second invention, the operation of reading the gradation information from the line buffer is the same as in the first invention, but the gradation information is
The behavior of converting to a value is different. That is, based on the input position information in the main scanning direction and the input position information in the sub-scanning direction, the threshold storage means outputs a threshold according to the position information, and the comparison means compares the gradation information and the threshold to perform binarization. While reading the gradation information of one pixel from the line buffer, the position information in the main scanning direction changes a number of times equivalent to the number of dots determined by the size of the density pattern matrix, and a threshold value is set according to the position information. is output from the threshold storage means and compared with the gradation information of that pixel by the comparison means.
Value data is determined.

The binary data output from the comparison means is converted into serial/parallel data by a shift register, and stored in a latch according to the input STB signal. Then, the driver selectively drives the recording medium in accordance with the output of the latch to finish recording on that line of the recording apparatus.

In the next line of the recording device, the position information in the sub-scanning direction also changes, so the gradation information of that pixel is further compared with a different threshold value to determine binary data. By performing the same operation a number of times corresponding to the number of lines determined by the size of the density pattern matrix, recording of one line of the image signal is completed.

Embodiment Below, a first embodiment of the present invention will be explained with reference to the drawings. In the first embodiment of the present invention, gradation information of m pixels each consisting of bits is stored and serially stored. Line buffer to read and k-bit gradation information to iXj
(iXj-"2k) size density pattern matrix, there is a raster scan counter that counts j lines in the sub-scanning direction of the recording device, and a raster scan counter that counts j lines in the sub-scanning direction of the recording device, and a A density pattern generating means for outputting i-bit binary data in parallel, i shift registers connected to the output of the density pattern generating means, and n (n=iXm) bits for storing the output of the shift registers. latches and n drivers that energize and drive n dot recording bodies by the output of the latches, and the S-th (S=0 to 1-1) shift register among the i shift registers generates a density pattern. The Sth output of the means is serial-parallel converted, and the output is the (IXi+5)th (1=O~m-)th output of the latch.
1) Connected to the th input.

Furthermore, to make the explanation easier to understand, k=4.1=j=
This method binarizes a 4-bit gradation signal using a 4x4 density pattern matrix, m-32,
The case where n=128 and the total number of dots in the line head is 4096 dots will be described.

FIG. 1 is a block diagram of a head drive IC of the present invention.

2 is 128 drive circuits that drive the line head, 3 is a 128-bit latch corresponding to drive circuit 2, and 4 is 4 shift registers SRO~ with a length of 32 bits.
SR3 is a 128-bit long shift register, 5 is a 4-bit wide line memory that stores gradation information for 32 pixels and functions as a line buffer, and 6 is a clock signal (
16 is ST
A 2-bit raster scan counter counts up in response to the B signal, and 7 is a density pattern generation ROM that stores 24 density pattern matrices of 4×4 size. The output of the SRO of the shift register 4 is sent to the 0th, 4th, ..., 124th dot of the latch 3, and the output of SRI is sent to the 1st, 5th, ..., 125th dot of the latch 3.
The output of SR2 is the second, sixth, ..., twelfth of latch 3.
6 dots, the output of SR3 is the 3rd, 7th, .
..., respectively connected to the 127th dot, and the 4-bit output PO1P of the density pattern generation ROM7
1, R2, R3 are 5RO1SR1 of shift register 4,
They are connected to the inputs of SR2 and SR3, respectively.

FIG. 2 shows a head drive circuit constructed using the head drive IC of the present invention.

1 is a line head with a recording body of 4096 dots, 2
0 is 5 for the head drive IC 117 of this embodiment shown in FIG.
This is a decoder that decodes a bit address into 32 signals.

In this embodiment, the line head 1 has 1024 pixels, that is, 4096 dots, and each head drive IC 2
Since 0 has the ability to drive 32 pixels, that is, 128 dots, 32 head drive ICs 20 are required to drive all the dots of the line head 1. The 4-bit data bus, the lower 5 bits of the 10-bit address bus, the clock signal (CLK), the initialization signal (CLR) for the address counter 6 and raster scan counter 16, and the latch signal (STB) are used by all ICs. is commonly input to
The upper 5 bits of address input (Ain) are sent to decoder 1.
7, it is decoded into a 32-bit select signal and applied to the CE large input of each head drive IC 20.

With the above circuit configuration, 32 head drive ICs 2 are used.
The line memory 5 in 0 is expanded to a line memory of 1024 pixels, and 4-bit 16-gradation data can be randomly accessed through the data bus and address bus.

Next, the operation inside the head drive IC 20 will be explained.

In this embodiment, a density pattern generation ROM 7 storing 24 4×4 density pattern matrices is used as the density pattern generating means, and the contents are shown in FIG. A density pattern based on a Bayer-type matrix was used.

In FIG. 3, H2 to H5 are the outputs of the line memory 5 and represent the gradation of each pixel, and HO to H1 are the outputs of the raster scan counter 16 and represent position information.

Further, PO to P3 are data of 1'' or 0'', respectively, stored in the density pattern ROM, and a set of four represents one column of binary data of the density pattern matrix. That is, H2 to H5 and HO to H1 select a density pattern matrix and a line in the density pattern matrix as addresses of the density pattern generation ROM 7, respectively, and generate binary data PO to according to the gradation information and position information.
P3 are output in parallel to SRO to SR3 of the shift register 4, respectively.

For example, if the tone information recorded by a certain pixel is 6, H2
=0, H3=1, H4=1, H5=O, and the sixth matrix of the density pattern generation ROM 7 is selected, and the HO
= 0, H1 = 0, the data in the first column of the matrix, that is, PO = 1, P1 = 0, P2 = 1, P3 = 0, is output, and HO = 1.81 = O, the data in the second column of the matrix is output. data, i.e. po=o, P1=,1, P2=O1P
30 and so on are output.

The 4-bit gradation information written in the line memory 5 is read out continuously for 32 pixels using the 5-bit address given by the address counter 6. When the address counter 6 completes one cycle and all the contents of the line memory 5 are read out, the binary data sent to the shift register 4 by the STB signal is stored in the latch 3, and the drive circuit 2 is activated according to the output of the latch 3. The recording medium is selectively driven to finish recording that line. Then, as the recording device advances to the next line in the sub-scanning direction, the output of the raster scan counter 16 counts up, so the position information changes, and the density pattern generation ROM 7 shifts the binarized data corresponding to the position information. It will be sent to register 4. In this way, the gradation information of each pixel stored in the line memory 5 between 4 lines in the recording device is binarized in a 4×4 matrix by the density pattern method, and one line of the image signal is converted into 4 lines in the recording device. Record with .

In this example, the line head 1 with 4096 dots is
Since recording can be performed simultaneously using two head drive ICs 20 and 4-bit parallel processing is performed, the speed can be increased by at least 32×4 times compared to the conventional example. In reality, since the line memory 5 is included in the IC, there is less delay due to wiring and external bus driving, and even higher speeds are possible.

Although a line memory is used as the line buffer in this embodiment, it may also be configured with a shift register of 4 bits wide and 32 bits long and a selector.

Next, a second embodiment will be described.

In the second embodiment, each pixel is composed of bits m
A line buffer that stores and serially reads out pixel gradation information, and a line buffer that stores k-bit gradation information at 1Xj (iXj = 2k)
A raster scan counter that counts j lines in the sub-scanning direction of the recording device in order to binarize with a density pattern matrix of size, a clock counter that counts i dots of clocks in the main scanning direction, and ixj k-bit thresholds. threshold storage means for storing and outputting a threshold according to the position information obtained by the outputs of the raster scan counter and the clock counter; a bit comparison means for comparing the gradation information and the threshold; and serial-parallel conversion of the output of the comparison means. n(
n=iXm) bit latch and the output of the latch
The n drivers for energizing and driving the dot recording medium are arranged unevenly.

Furthermore, to make the explanation easier to understand, k=4.1=J=
In other words, a 4-bit gradation signal is binarized using a 4×4 density pattern matrix, m=32,
The case where n=128 and the total number of dots in the line head is 4096 dots will be described.

FIG. 4 is a block diagram of a head drive IC according to a second embodiment of the present invention.

2 is a drive circuit, 3 is a latch, 30 is a 128-bit first shift register, and 16 is a raster scan counter that counts up by the STB signal and whose outputs E2 and E3 are connected to the upper two bits of the address of the threshold ROM. , 31 is a 4-bit width 3 that stores tone information for 32 pixels.
A 2-bit long second shift register 32 is used as a 4-bit input of the second shift register 31 to input Din and the second shift register 32.
A selector 33 that selects either the output Dout of the shift register 31 counts up by the CLK signal, outputs EO1E1 to the lower two bits of the address of the threshold ROM, and the inverted signal of El to the second shift register. 34 is connected to the clock input of the second shift register 31 and the threshold value RO.
A comparator compares the outputs of M and serially sends data to the first shift register 30, 35 is a threshold ROM that stores a 4-bit width threshold, and 36 is an inverter that inverts El.

FIG. 5 shows a head drive circuit constructed using the head drive IC of the present invention.

1 is a line head, 21 is a head drive IC shown in FIG.
It is.

In this embodiment, the line head 1 has 1024 pixels, or 4096 dots, and the head drive IC 21 is responsible for driving 32 pixels, or 128 dots. Therefore, in order to drive all the dots on the line head 1, it is necessary to drive the head IC
21 requires 32 pieces.

In addition, the input (SEL) of the selector 32, the clock signal (
CLK), raster scan counter 16 renewal signal (
CLR) and latch signal (STB) are commonly input to all ICs.

In this embodiment, the line buffer is composed of a second shift register 31 and a selector 32.

When writing data to the line buffer, by setting the SEL signal given to the selector 32 of each IC to Din, 32 second shift registers 31 in the head drive IC 21 are connected in cascade, and the entire 4 bit width 1
024 pixel shift register is constructed. Then, the 4-bit data is given to the input of the first head drive IC 21, and the output is given to the input of the next head drive IC 21, so that 4-bit 16-gradation data can be serially written for 1024 pixels.

When reading data from the line buffer, the SEL signal given to the selector 32 of each IC is set to Dout, and a ring buffer is formed in which the input and output of the second shift register 31 are connected in a ring shape.

Since the inverted signal *E1 of the output E1 of the clock counter 33 is connected to the clock input of the second shift register 31, the first shift register 30 performs shift registration once every four times. Become. The same data can be read out many times in a 32-pixel period. When the second shift register 31 has read out 32 pixels continuously, that is, when it has sent 128 dots of data to the first shift register 30, the STB
By applying a signal, the data stored in the first shift register 30 is stored in the latch 3, and at the same time, the output of the raster scan counter 16 is counted up, and the contents of the shift register 31 of the cylinder 2 are read out again from the beginning.

Next, the operation within the head drive IC 21 in this embodiment will be explained.

In this embodiment, the means for binarizing the gradation signal using the density pattern method is composed of a comparator 34 and a threshold value ROM 35.

FIG. 6 shows the threshold values stored in the threshold value ROM 35 in decimal notation, and four threshold values of the same E2 and E3 represent one column of the matrix, making up a 4×4 matrix as a whole. It is arranged like this. In addition,
In this example, a 4×4 Bayer type threshold matrix was used.

BO to B3 read from the second shift register 31
The gradation information is compared with the outputs CO to C3 of the threshold ROM 35 by the comparator 34, and if BO to B3 is larger, "1'" is set, and if smaller, 0" is set to the first shift register 30.
sent to. When the CLK signal is input, the output EO1E1 of the clock counter 33 counts up, and the threshold ROM 35 stores the threshold value C of the next row in the same column of the matrix.
Outputs O to C3. In addition, the second shift register 31
outputs the gradation information of the next pixel every time *E1 is input, whereas the threshold ROM 35 outputs the threshold of the next row every time the CLK signal is input, and the first shift register 30
Since the shift register is performed every time the CLK signal is input, the 4 data that are compared with the 4 threshold values in the same column and determined to be 1'' or 0'' for the gradation information of one pixel are the first It is sent serially to the shift register 30.

The 4-bit gradation information of the second shift register 31 is 32
When the pixels have been read out, the binary data sent to the shift register 4 by the STB signal is stored in the latch 3, and the drive circuit 2 selectively drives the recording medium according to the output of the latch 3 to record that line. Finish. The second shift register 31 reads out the same data every 32 pixels, while the outputs E2 and E of the raster scan counter 16
3 is incremented every time the STB signal is input, so the threshold ROM 35 outputs the threshold of the next column. In this way, the gradation information of each pixel stored in the line buffer between the four lines of the printing device is compared with all the threshold values of the density pattern matrix and binarized in a 4×4 matrix by the density pattern method.

In this embodiment, all the signals are of positive logic, but by changing the comparison conditions of the comparators, they can also be constructed of negative logic. Of course, a line memory may be used as the line buffer.

In this embodiment, since the 1024-pixel line head 1 can simultaneously record with 32 head drive ICs 21, the speed can be increased at least 32 times compared to the conventional example. In reality, since the line buffer is constituted by a shift register that is inherently high speed, it is possible to increase the speed several times more than that using a RAM outside the IC.

In addition, in this embodiment, compared to a case where a density pattern generation ROM is used as a binarization means for binarizing using a density pattern matrix, the threshold ROM only stores the threshold value, so the number of gates constituting the IC is small. Furthermore, since a shift register is used for the line buffer, the number of gates configuring the IC can be reduced compared to an IC using a line memory.

Note that in both the first and second embodiments, the density pattern generation ROM
, a threshold value ROM and a ROM are used, but a gate IC may be used to output data similar to that of the ROM.

Effects of the Invention By using the density pattern head drive IC having the above-mentioned configuration, the present invention enables the density pattern head drive IC to be used only once for each line of the image signal, regardless of the number of lines of the recording device determined by the size of the density pattern matrix. It is only necessary to transfer the image signal, and the transfer time can be extremely short.

Regarding recording, one head drive IC is usually in charge of driving 32 to 64 pixels, and one line consists of several dozen, so the generation of density patterns requires several dozen head drive ICs. Each pixel group can be processed simultaneously. Therefore, the recording time is reduced to 1/the number of ICs compared to the conventional method. Furthermore, compared to the conventional transfer from the line memory to the head drive IC, all the processing is performed within the same chip, making the transfer faster.

Additionally, as the number of pixels in the line head increases, the degree of simultaneous processing increases proportionally, so the recording time is not affected by the number of pixels in the line head, allowing high-resolution images with a large number of pixels to be recorded at high speed. Become. Furthermore, since it is possible to record images even when the number of gradations is extremely large, which precludes conventional methods from the point of view of recording speed, that is, when the size of the density pattern matrix is increased, it is possible to record high image quality with good gradation. A recording device that records images at high speed can be easily configured. Furthermore, it has great practical effects, such as eliminating the need for large-scale peripheral circuits in order to perform high-speed recording.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 shows a head drive IC according to a first embodiment of the present invention.
2 is a block diagram of a head drive circuit configured using this IC, FIG. 3 is a diagram showing binarized data stored in the density pattern generation ROM in the first embodiment, and FIG. The figure is a block diagram of a head drive IC in a second embodiment of the present invention, FIG. 5 is a block diagram of a head drive circuit configured using this IC, and FIG. FIG. 3 is a diagram showing stored threshold values. 1---Line head, 2---Drive circuit, 3---
-Latch, 4--shift register, 5-line memory (
line buffer), 7--density pattern generation ROM,
20.21--Head drive IC130--First shift register, 31-1-Second shift register, 34
-m- comparator (comparison means), 34--one threshold RO
M. Name of agent: Patent attorney Shigetaka Awano

Claims (2)

[Claims] (1) A line buffer that stores gradation information, a density pattern generation unit that outputs binary data according to the gradation information of the line buffer and position information in the sub-scanning direction, and an output of the density pattern generation unit. A head drive I characterized by comprising: a plurality of shift registers connected to each other; a latch for storing the output of the shift register; and a driver for selectively energizing and driving a recording medium using the output of the latch.
C. (2) A line buffer for storing gradation information, a threshold storage means for outputting a threshold according to positional information in the main scanning direction and the sub-scanning direction, and a threshold storage means for outputting the gradation information of the line buffer and the output of the threshold storage means. Comparing means for comparison, a shift register for serial-parallel converting the output of the comparing means, a latch for storing the output of the shift register, and a driver for selectively energizing and driving the recording medium by the output of the latch. A head drive IC featuring: