JPS6067987A - Halftone expression - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for representing halftone images on display devices, printers, etc. capable of inputting binary power.

[Prior art]

Conventionally, as a method of binarizing and reproducing a gradation image, a storage device such as a ROM is stored with threshold levels that correspond to pixel divisions with one and two images and that are regularly distributed in two dimensions at high and low levels. Store the data, determine the read address of the storage device based on the two-dimensional address of the input analog signal, and read the threshold data [2. Convert this data to an analog signal and use it as input] There is a method of adjusting the level with the analog signal and converting it into a binary value based on the high-low relationship between the two, or converting the input analog signal to a digital signal and using the read address of the storage device based on the two-dimensional address of the input. A so-called systematic dither method is generally used in which threshold data is read out and binarized based on the magnitude relationship between the two.

With such a conventional method, the image quality deteriorates considerably in a general document consisting of five characters and Φ lines. Further, it is necessary to make a one-to-one correspondence between the number of input data and the number of output data. In order to eliminate this drawback, the same manual data is used several times (for example, 2x2 times) to inflate the data, and for each time, the thread/no-shold value of a different address is read out, and the binary values are obtained by comparing the values. A method has been proposed to do this. In this case, it is not suitable for high-speed operation because it is necessary to compare the number of output dots with the threshold.

〔the purpose〕

An object of the present invention is to take advantage of the expressive power of systematic dithering, prevent deterioration of character data, etc., and enable high-speed processing and real-time processing.

An important object of the present invention is to obtain a high-quality image with excellent gradation and resolution.

[% mark]

In order to achieve this objective, the present invention divides an image into large blocks (ft, for example, 8 x 8 squares), and further divides each of the large blocks into a plurality of (for example, 16) small blocks (for example, 2 x 2 dots). The data for one input pixel is made to correspond to the small block, and the output data (for example, 2×2) corresponding to the input data value is selected in one process, and this process is repeated multiple times (for example, 16 times) to express a large block.

In other words, the resolution is improved by the number of samplings of the input image using a small block (e.g. 2x2), the resolution is improved by the number of tones than a large block (e.g. 8x8), and then the main processing can be implemented in real time.

Structure] FIG. 1 shows an embodiment of the present invention, which is an array of IU input signal data, in which pixels are represented by a matrix in which α is a horizontal component and b is a vertical component. This is a memory in which a small block pattern of two images (for example, 2×2) is stored in advance.Selection of this memory is a value obtained by binary coding a data value of 1 (for example, 6
bit), and X, which is the position data of the input pixel, as shown by the following formula.

The binary value (4 bits) of y is used as an address signal.

x = a mod 4 y = b tn, od 4
(1) (αmad 4 is the quotient of α divided by 4) These data are used as an address signal and 17 to select a small block pattern. This selection is 1
Number 3 is the result of 4 consecutive tests performed 6 times). The aligned block pattern is 8×8 and 2×2 with one pixel. Next, Figure 2 shows an example of a ROM dither pattern that has been stored in advance.

It is something that (a,) - shows a Bayer dither pattern as an example. Based on this pattern, the ROM
Develop the pattern. (/11, (C1, look back, R
The pattern serving as the content of the OM is shown as an 8×8 configuration. It is actually selected as a pattern of #-t2X2, but by writing the above Z and 7/ in parallel, 8X8 butter 7
and 17. In other words, (b) is for input data 1)
If the value is 1 or more compared to the reference pattern, the value less than 1.1 is treated as 0, and a binary pattern is constructed.

Here, only the upper left is 1 and it becomes (lllto.) (C) When the input data value is 32, the slope is when the input data value is 64, and the binarization pattern is configured.The pattern selection is 2 × 2 The standard 8×8 is constructed by 16 selections.

If the 16 data values are equal, then )(c
A certain gradation is expressed by an 8x8 large block pattern as shown in (d), but if there is different data, the small block pattern corresponding to that value will be used to represent that data. The part corresponding to the value will be selected.

Although the small block pattern has been described as 2×2 dots and the large block pattern as 8×8 dots, the present invention is not limited to these. for example.

If the large block pattern is 4×4, the input data can also be composed of 4-bit data. Also, if the small block pattern is set to 1, the same result as a general systematic dither can be obtained.

FIG. 3 shows a specific embodiment of the present invention, which is an A/D comparator for converting an input signal input as a 4-digit analog signal into a digital signal. The digital data (6 bits in the example) output from the A/D converter is stored in a high-speed ROM.
As the address input in step 5, the outputs of the horizontal counter 6 and vertical counter 7 for selecting the location of the small block pattern are also used as addresses in the high speed ROM, and a pre-stored small block pattern is selected and output. The small flock pattern output from J'lOM 5 is slowed down by the high-speed shift register 8 multiple times (for example, 4 times) and sent to the RAM 11 as parallel data (16 data) by RC. Make me remember. RAMK 11 stores all the binary data to be output to the 10 dot printers in real time. In order to output to the dot printer No. 10, the reader is output via the alignment circuit No. 9, and output to the dot printer to form the gradation side.

〔effect〕

As described in detail above, the present invention makes it possible to configure high-quality images with excellent gradation and ease of use using a very simple circuit, and furthermore, it is possible to configure high-quality images with excellent gradation and ease of use. The RAM capacity can be kept to a minimum. In other words, even when inputting data of 6 bits per pixel or 8 bits, the RAM capacity can store 4 bits per pixel.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of halftone image binarization according to the present invention. FIG. 2 is a diagram showing an example of a dither/Z-turn configuration of a ROM, and FIG. 3 is a block diagram showing a specific example of the configuration of an embodiment of the present invention. Applicant: Epson Corporation Figure 1 Figure 2

Claims (1)

[Claims] In binary halftone representation of an image, when selecting multiple (for example, 2×2) binary data from a storage device based on one input pixel data value, the position information and pixel data of one pixel are A halftone expression method characterized by specifying an address and selecting the binary data.