JPH02146855A - Clock information processing system for electronic exchange system - Google Patents

Abstract

PURPOSE:To identify and interrupt a fault at the fault of a specific hardware clock and to continue the collation processing with a remaining hardware clock by providing a software clock adopting timer interruption as a reference and duplicated hardware clocks on a time collation system and using the decision logic of a time difference between the three timers. CONSTITUTION:A software clock 2 is provided in a memory section in a central processing unit CPU 11 and hardware clocks 3, 4 incorporating a high accuracy oscillator are connected to a CPU 1. The software clock 2 and the hardware clocks 3, 4 are collated periodically by the CPU 1, which calculates time differences T 1, T 2, T 3, T 4. When the difference T 1 resulting from the collation between the hardware clock 3 and the software clock 2 is smaller than the difference T1 and the difference T 2 between the hardware clocks 3 and 4 is smaller than the difference T2, both the hardware clocks 3, 4 are regarded to be normal to correct the software clock 2 by a prescribed correction method. Moreover, when the difference T 2 is larger than the T2, either of the hardware clocks 3, 4 is decided to be faulty.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processing system that performs billing calculations based on clock information held by the system.

In particular, it relates to electronic switching systems.

[Conventional technology]

Conventionally, system internal clocks (referred to as software clocks) in information processing systems such as electronic switching systems are clocked by the central processing unit (CP) at fixed intervals (4ms, 8ms, etc.).
A method is adopted in which steps are taken based on the timing interrupt from U). However, this timing interrupt is C
Affected by the operating status of the program inside the PU1
For example, if the state in which 2 interrupts are disabled continues for 1 second, no 2 interrupts will occur during that time, so the software clock will not advance for 1 second, resulting in a delay from the time in the natural world.

In systems such as switchboards, which measure call time and calculate charges based on the time indicated by a software clock, this delay in the software clock is a problem.

Since this may lead to loss of reliability of the billing information itself, a highly reliable external hardware clock is installed separately, and the hardware clock and software clock are checked periodically. Corrects delays in software clocks and detects software clock failures9.

Figure 4 shows the system configuration of such a system.
, CPU 1 is equipped with a software clock 2.
, CPU 1 is connected to the lead clock. To check the clock, as shown in FIG. 5, the difference between the two values is calculated at regular intervals.

The processing machine in accordance with the difference between the two clocks is shown in FIG. T
While 4 is less than T1, nothing is done as a permissible error. If it is larger than TI or T1 and less than 12.

It is determined that correction is necessary and the value of the software clock is brought closer to the value of the hard clock by T3. The reason why the software clock value is not completely matched to the hard clock value during correction is to prevent detection from being delayed in the event of a failure that would cause the hard clock to be delayed. Also,
When the difference (T,) becomes larger than T2, it is determined that the hardware clock is malfunctioning.

Since the system clock is in a faulty state, the machine will be operated using only the software clock until the hard clock is repaired.

Note that the values of T1 e T2 p T3 are determined by the accuracy of the system clock and the verification cycle, but in general [problem to be solved by the invention] In the conventional verification processing method described above, the Because it is single layered, there is a high probability of system clock failure.
Driving using only the software clock (billing information cannot be obtained accurately)
There is a problem that the period becomes long.

[Means to solve the problem]

The clock verification method of the present invention has a software clock based on timer interrupts and a duplicated hardware clock, and detects a specific hardware clock failure based on the logic for determining the time difference between these three. In some cases, the faulty side is identified and isolated, and the matching process is continued with the remaining hardware time.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

A software clock 2 is installed in a memory section (not shown) in a central processing unit (CPU) 1, and hardware clocks 3 and 4 each having a built-in high-precision oscillator are connected to the CPU 1. These software clocks 2 and software clocks 3 and 4 are C
Verified periodically by PU 1.

The time difference (T41 #T421 T,s) is calculated (FIG. 2).

The logic of failure identification of the duplicated hardware clocks 3 and 4 will be explained with reference to FIG. 3 as well. First, node clock 3
(ACT system) and software clock 2 (difference numerator,
1). Difference between TJl and node clocks 3 and 4 (Ta
When 2) is smaller than T2, both the clocks 3 and 4 are considered normal. In this case, correction processing of the software clock 2 is performed using Tj1 as a reference.

The correction is performed by bringing the value of the software clock 2 closer to the hard clock 3 by Tx (<TI) when Tj1≧T. Next, when TI2 is greater than T2, it is determined that one of the node clocks 3.4 is malfunctioning. in this case.

By comparing the difference (fax) between the software clock 2 and the node clock 4 (SBY system) with TI1, the one with the larger difference from the software clock 2 is determined to be faulty. Next, T7.
When is larger than T2, the bar P clock 3 immediately determines that it is malfunctioning, and calculates the difference numerator Δ3 between it and the hard clock 4. T.I.
When 3 is smaller than T2, the node clock 4 is assumed to be normal, and thereafter this hard clock 4 is operated as a new ACT hard clock. When T45 is greater than T2, the node clocks 3 and 4
Since both cannot be trusted, it is determined that there is a double failure.

〔Effect of the invention〕

As explained above, in the present invention, the external hardware clock that corrects the software clock is duplicated, and since the hardware clock that has failed is identified, the period during which verification is not possible due to a hardware clock malfunction is greatly reduced. It can be shortened to As a result, those who operate the system and provide sales services to users have the advantage of being able to carry out two billing tasks more efficiently.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a system configuration in an embodiment of the present invention, FIG. 2 is a diagram showing a verification method between two clocks, and FIG. 3 is a diagram showing failure determination logic as a result of verification. FIGS. 4 to 6 are diagrams for explaining conventional examples. 1... Central processing unit (including memory), 2... Software clock (soft clock), 3, 4... Nodeware clock (). Fourth

Claims (1)

[Claims] 1. An electronic switching system that has a software clock and an external hardware clock that are updated using timed interrupts from a central processing unit, and that corrects delays in the software clock by comparing the software clock and the external hardware clock. and the external hardware clock has first and second external hardware clock sections, and the software clock is compared with the first and second external hardware clock sections, and the software clock is A clock information processing method for an electronic exchange system, characterized in that the clock information of a clock is corrected.