JPH02146453U - - Google Patents
Info
- Publication number
- JPH02146453U JPH02146453U JP1989055489U JP5548989U JPH02146453U JP H02146453 U JPH02146453 U JP H02146453U JP 1989055489 U JP1989055489 U JP 1989055489U JP 5548989 U JP5548989 U JP 5548989U JP H02146453 U JPH02146453 U JP H02146453U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- solder
- mounting structure
- periphery
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Description
第１図は本考案による実施例の半導体素子の実
装構造を示す断面図、第２図は本考案による実施
例の作用を示す断面図、第３図は第２図の半導体
素子を示す平面図、第４図は他の実施例を示す断
面図、第５図はさらに他の実施例を示す断面図、
第６図は従来の半導体素子の実装構造を示す断面
図である。 １……半導体素子、２……ヒートスプレツダ、
３……半田、５……回路基板。
装構造を示す断面図、第２図は本考案による実施
例の作用を示す断面図、第３図は第２図の半導体
素子を示す平面図、第４図は他の実施例を示す断
面図、第５図はさらに他の実施例を示す断面図、
第６図は従来の半導体素子の実装構造を示す断面
図である。 １……半導体素子、２……ヒートスプレツダ、
３……半田、５……回路基板。
Claims (1)
- 回路基板上にヒートスプレツダを接合し、さら
に該ヒートスプレツダの上に半導体素子を半田に
て接合する半導体素子の実装構造において、該半
導体素子の周辺部下方の半田の厚みを、前記周辺
部下方以外の半田よりも厚くすることを特徴とす
る半導体素子の実装構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989055489U JPH02146453U (ja) | 1989-05-15 | 1989-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989055489U JPH02146453U (ja) | 1989-05-15 | 1989-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02146453U true JPH02146453U (ja) | 1990-12-12 |
Family
ID=31578486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989055489U Pending JPH02146453U (ja) | 1989-05-15 | 1989-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02146453U (ja) |
-
1989
- 1989-05-15 JP JP1989055489U patent/JPH02146453U/ja active Pending