JPH02143997A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a switching noise at an output buffer circuit at the time of performing the verification of a program and to stably perform an operation by bi-secting a MOSFET into two parts, operating only a divided MOSFET on one side at the time of performing the verification, and operating both divided MOSFETs in ordinary readout. CONSTITUTION:A semiconductor integrated circuit device is provided with first and second MOSFETs 1 and 2 connected between an output terminal and a power source Vcc, third and fourth MOSFETs 3 and 4 connected between the output terminal and the ground, NAND gates 5 and 6 which drive the MOSFETs 1 and 2, respectively, and NOR gates 7 and 8 which drive the MOSFETs 3 and 4. The verification of the program in which the level of the power source Vcc is increased higher than that in the ordinary readout is performed by reducing the capacity of the output buffer circuit to 1/2. In such a way, it is possible to reduce the switch-noise at the output buffer, and to stably perform a program verify operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application j] This invention relates to an output buffer circuit for a semiconductor integrated circuit device.

[Prior art 1] Figure 4 is a circuit diagram of seven output buffer circuits of a conventional semiconductor integrated circuit device.
P-channel lAOSFET connected to Vcc),
(3) is the U channel/L connected between the output terminal and ground
/IJ OS FET, (5) is P channel/L
' Iil OS FET (1) is driven by NAN
The D gate (7) is a NOR gate that drives the N-channel vosraT (3).

Next, the operation will be explained using F; P ROIil.

For EPROIJ, normal readout is Vcc = 5 V and output control signals Oe and p signals are each 1H"'
When the internal data signal is #H#, the output of the NAND gate (5) becomes L#, and the output of the oR gate (7) also becomes #L#, so P channel 3M! 081;'ET(1
) conducts, and N-channel MOS li' g T (
3) becomes non-conductive and 'H#' appears at the output terminal. Also, when the internal data signal is RL#, the NANJ) gate (5
) output becomes “H#” and the output of the NOR gate also becomes “1H”, and the P-channel MO8FET (1) becomes non-conductive and N
Channel /l/MO8Ii''ET (3) becomes conductive and 1L# appears at the output terminal.Thus, when the output control signals Oe and convex are respectively #L #ITH#, the internal data is Whether the signal is #H# #L 11, the output of the NAND gate (5) is "H" NO
The output of R gate (7) becomes 1L", channel) L/1
1! OS F g T(1) and a Nayane IL/! 1!
OSF E T (3) are both non-conductive) and the output terminals are in a floating or high impedance state.

EPROM has 8 or 16 output buffer circuits as described above.
For normal Vcc = 5 Vm, all output buffer circuits must operate stably and at high speed. Also, when writing, gPROV stores data in units of one byte or several bytes, and reads the data to confirm whether the writing was successful. This is called "program verification." Normally, when writing Power supply for writing vp
Apply 12.5V to p, and increase Vcc from 6■ to 6.5V
Write (program) and program verify after #J.

The reason why the 10 ghum verification is performed at a voltage higher than Vcc 5 V during reading is to confirm that the memory sale after writing is written in seconds. The 1 value of the memory cell after normal writing is higher than the read gate voltage (Vcc), but whether writing with sufficient margin has been done can be determined by increasing this gate voltage, that is, by raising Vcc and reading. This can be confirmed by doing the following. However, when operating at a raised Vcc, switching noise due to output charging/discharging current, through current, etc. in the output buffer circuit increases compared to when operating at Vcc 5 V.

Furthermore, since there are a large number of them, such as 8 or 16, noise problems must be taken into consideration when operating with this Vcc raised.

[Problem to be Solved by the Invention j] Since the conventional KFROM output buffer circuit is configured as described above, when operating with Vcc raised during program verification, switching noise in the output buffer circuit is reduced compared to during normal readout. This causes problems such as interfering with the stable operation of program verify, and in the page write method that began to be used in 1' JEPROM, the data to be written is latched within 4 bytes and the data latched at the same time. There was a problem that the contents of this latch could be destroyed if there was a large amount of noise during programming.

This invention was made in order to solve the above-mentioned problems, and it reduces switching noise in the output buffer circuit during program verification and enables stable operation of the KPRO! [Means for Solving the Problem 1] An output buffer circuit for an EPROM according to the present invention divides the MO8F'ET between the output terminal and the power supply into two, 2
MO8F'ET, and MO81i between the output terminal and ground.
'ET is also divided into two to form the third and fourth MO8F'ET, and one of the divided MO8F'ETs is used during program verification.
Only Li'P2T is operated, and during normal readout, the MOS rETt- of the divided screen is operated.

[Use 1] The output buffer circuit according to the present invention can reduce the capacity by half by halving the size of the output buffer during program verification compared to during normal reading, and can reduce switching noise in the output buffer V.

[Embodiment j Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, (1) and (2) are the output terminal and the power supply (Vc
c) first and second 1dO3F'E connected between
T , (3) and (4) are @3 and 4th 140 S F E T , (5) connected between the output terminal and grounding.
, (6) respectively MOSFET (1) and (2
), and (7) and (8) are NOR gates that drive '/10 S F E T (3) and (4), respectively. oe, o6 are output control signals, v
8 and n are the outputs of the power supply (VCC) voltage detection circuit. Also, is Figure 2 the power supply in Figure 1? FIG. 2 is a circuit diagram showing one embodiment of a voltage (Vcc) detection circuit.

Next, the operation will be explained.

The 'rJL source voltage (Vcc) detection circuit shown in Figure 2 is (
9), (10), (ll), (12 Nah M O
Power supply voltage (Vcc) due to cascade connection of SFET
outputs VRES, which is the level shift 2 voltage, and this VR
ES becomes an input to the next stage Pch MOS FET (43) and Nch IJO8F ET (14). This OS E" E T has an open chain VINV formed by (13) and (14), and VREF'
The output is transmitted to the invert p (15) by the value. The inverter (15) performs waveform shaping and amplification and outputs VS, and the inverter (16) receives VS as input and outputs 6, which is an inverted signal. Figure 3 shows the above VRES and VINV.
A characteristic diagram showing the relationship between and power supply voltage (Vcc)! i!
The one-wing value voltage VINV of the inverter according to OS F E T (13) and (14) is the power supply (V
As shown in Table 1, the voltage is set to a value exceeding the voltage (Vcc = 5V) and less than the voltage of the power supply (Vcc = 6 to 6.5V) during program verification.

From the above, in FIG. 1, during normal reading, Vcc
= 5 V TeVS, VS are 'L' and 'H, respectively.
", and if the oe and oe times signals are respectively "H" and 'L', when the internal data signal is "H", the NAND gate (
The outputs of 5) and (6) both become L#, and the NOR gate (
The outputs of 7) and (8) are both L#, and the first and second
MOSFETs (1) and (2) are conductive and the third and fourth MOSFETs (1) and (2) are conductive.
VOSFET (3) and (4) become non-conductive, and H# appears at the output terminal. Similarly, when the internal data signal is L#, the outputs of NAND gates (5) and (6) are both #H#, and the outputs of υNOR gates (7) and (8) are also both #H#, and the 1 and 2nd MOSFET
(1) and (2) are non-conducting third and fourth MOS F
E T (3) and (4) become conductive and "L#" appears at the output terminal. In the above case, the first to fourth % of the output
108 FET (1) (2) (3) (4)
Since everything works, there is no big difference from the conventional operation.

Next, we will explain about program verification)
cc = 6 V (or V at 6.25-(,5v)
S and VS each become #H"'L". If the OE% signal is IT HS # L #, then HAN
The D gate (6) outputs #H# whether the internal data signal is H" or L#, and the second 1,40SF'ET (
2) is always non-conducting. Similarly, NOR gate (8)
Whether the internal data signal is H'''L'', the output is #L
", and the fourth MOSFET (4) is always non-conductive. At this time, the NAND gate (5) and the NOR gate (
7) operates in the same way as normal reading, so the first MO
8F'ET (1) and the third 11! OS FET (
3) becomes conductive or non-conductive according to the internal data signal, and H# or L" appears at the output terminal. However, VOSF"E
Since both l and T operate only half of the normal read operation, the output switching noise is reduced.

Since the access time during program verification may be slower than the normal access time, there is no problem even if the size of the output sofa circuit is halved.

The explanation of other operations is the same as the conventional one, so the explanation will be omitted.

Table 2 (Operation of the output buffer circuit of the present invention)
In the above embodiment, the case of switching noise of the output buffer during program verification of FJPROM was described, but this invention provides @f'! Similar effects can be achieved in other semiconductor integrated circuit devices having a wide if source voltage range.

[Effect of the invention 1] As described above, according to the present invention, the capacity of the output buffer circuit is halved during program verification, which is performed with Vcc higher than during normal reading, so that switching in the output buffer is reduced. EPRO that can reduce noise and enable stable program verification operation
There is an effect that M can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output buffer circuit of a semiconductor integrated circuit device showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the power supply voltage (Vcc) detection circuit in FIG. 1, and FIG. The figure is a characteristic curve diagram of the relationship between VRES, VINV, and Vcc in Figure 2, Figure 4 is a circuit diagram of an output buffer circuit of a conventional semiconductor integrated circuit device, and Figure 5 is a VG diagram of the erase and write state of the memory transistor of an iEPROM. It is a diagram showing -VD characteristics. In the figure, (1) is the first li! 08Ii”ET, (
2) is the second ViOS F' E 'I', (3)
is the third IA OS r I T , (4) is the fourth M OS FET , (5) and (6) are NAND
gates, (7) and (8) are NOR gates, (9) to (1
2) is an N-channel 1i (O8FET), (13) is a P-channel/l/IAO8FET, and (14) is an N-channel MOSFET.

Claims (1)

[Claims] The above-mentioned power supply voltage detection circuit has a power supply voltage detection circuit, and is composed of first and second MOSFETs connected between the output terminal and the power supply, and third and fourth MOSFETs connected between the output terminal and ground. When the first power supply voltage is detected, the first, second, third and fourth MOSFETs become conductive or non-conductive depending on the internal output signal, and output a control signal to output a signal from the output terminal. , when the second power supply voltage is detected, the first and third MOSFETs become conductive or non-conductive depending on the internal output signal, and the second and fourth MOSFETs output a control signal that always makes them non-conductive. A semiconductor integrated circuit device characterized by: