JPH02143768A - Fault information transmission system - Google Patents

Abstract

PURPOSE:To stop the invalid processing of a terminator with respect to invalid information quickly by sending fault information to a terminator from a line adaptor with prescribed part of a frame synchronizing bit and discriminating the validity of the information sent from the line adaptor to the terminator with the rest of a frame synchronizing bit immediately. CONSTITUTION:A frame synchronizing bit extraction means 100 extracts a frame synchronizing bit reached from a digital transmission line 1 and sends it to a terminator 6. A fault information insertion means 200 detects a fault generated in the digital transmission line 1 and inserts the fault information representing the occurrence of a fault to part of the frame synchronizing bit extracted by the frame synchronizing bit extraction means 100. Thus, the fault information is sent directly from the line adaptor 20 to the terminator 6 with part of the frame synchronizing bit and the validity of the information sent from the line adaptor 20 to the terminator 6 with use rest of the frame synchronizing bit is discriminated immediately. Thus, the invalid processing of the terminator 6 with respect to the invalid information is quickly stopped.

Description

[Detailed Description of the Invention] [Summary] Regarding a failure information transmission method in a line compatible device used when a digital transmission line is accommodated in a digital exchange, the present invention relates to a failure information transmission method in a line compatible device used when a digital transmission line is accommodated in a digital exchange. For the purpose of making the determination possible, a line-compatible device that accommodates a digital transmission path and connects to a communication path device that constitutes a digital exchange extracts frame synchronization bits that arrive from the digital transmission path and transmits them via the communication path device. frame synchronization bit extracting means for transmitting the frame synchronization bits to the terminating device; and detecting a fault occurring in the digital transmission path, and inserting fault information indicating the occurrence of the fault into a predetermined part of the frame synchronization bits extracted by the frame synchronization bit extraction means. The configuration is such that a failure information insertion means is provided.

[Industrial application field]

The present invention relates to a failure information transmission method in a line compatible device used when a digital transmission line is accommodated in a digital exchange.

[Conventional technology]

FIG. 3 is a diagram showing an example of a digital exchange to which the present invention is applied, and FIG. 4 is a diagram illustrating the data format of the digital transmission path in FIG. 3.

In FIGS. 3 and 4, the digital signal transmitted via the digital transmission path 1 accommodated in the digital exchange is divided into 24 time slots each for transmitting information such as voice, as shown in FIG. TSI to TS24
and the frame synchronization bit FS constitute a frame F, which is repeated at a period of 125 microseconds.

Further, the frame synchronization bit FS constitutes a multi-frame every 24 frames F, and the 4th frame F4, the 8th frame F1%, the 12th frame Fez, and the 16th frame F16.
, the frame synchronization bit FS of the 20th frame F2° and the 24th frame F24 is set to logic “0” 0 to detect frame synchronization and multi-frame synchronization, respectively.
", "1", "0"1" and "l", and the second frame FZ, the sixth frame Fb, the tenth frame F1°, the fourteenth frame l"+4, and the eighteenth frame Fi
The frame synchronization bit FS of l+ and the 22nd frame F22 is used as error detection and correction bits CI to C6 within the multiframe, and the remaining odd frames Fl, F3
,...,F2. frame synchronization bin corresponding to )FS
is used as a message bit D for transmitting maintenance information, etc. between the two stations accommodating the digital transmission line 1. Therefore, the message bit D has a transmission rate of 4 kilobits per second.

The digital exchange converts the time slots TSI to TS24 and frame synchronization pins FS in each frame F arriving from the digital transmission line 1 to the digital terminal (
DT) 2 and time slots TSI to TS2.
4, the call processing device (CPR) 7 is a channel device (DSM)
The frame synchronization bit FS is transmitted to a digital terminal (DT) 4 accommodating, for example, another digital transmission path 5 via a communication path having a communication speed of 64 kilobits per second, which is set within 4 sets. Terminal(
multiplexed with frame synchronization bits FS from DT) 2;
6 per second, which is fixedly set in the channel device (DSM) 3.
The data is transmitted to the terminating device (TM) 6 via a communication path having a communication speed of 4 kilobits.

The terminal device (TM) 6 is a digital terminal (DT)
Call route bag from 2! A message bit D having a communication speed of 4 kilobits per second is extracted from the frame synchronization bit D having a communication speed of 8 kilobits per second transmitted via the communication path in (DSM) 3, and is transmitted from the opposite station. Edit and output the maintenance message.

FIG. 5 is a diagram showing an example of a conventional digital terminal.

In Figure 5, five sets of digital terminals (DT
) 2 to the communication path device (DSM) 3 (FIG. 3), an interface device (INF) 8, not shown in FIG. 3, is shown.

In Figure 5, a bipolar-unipolar conversion circuit (B
UC) 21 converts the bipolar format digital signal arriving from the digital transmission line 1 into unipolar format,
Clock extraction circuit (CEX) 22 and unipolar N
It is transmitted to the RZ conversion circuit (UNC) 23.

The clock extraction circuit (CEX) 22 extracts a clock signal from the unipolar digital signal transmitted from the bipolar-unipolar conversion circuit (BUC) 21 and transmits it to the unipolar-NRZ conversion circuit (UNC) 23.

The unipolar/NRZ conversion circuit (UNC) 23 converts the unipolar digital signal transmitted from the bipolar/unipolar conversion circuit (BUC) 21 into N RZ (No.
nReturn to Zero) format digital signal, and sends it to the frame synchronization circuit (FSY) 2.
4. The signal is transmitted to the multi-frame synchronization circuit (MFS) 25, the alarm detection circuit (ALD) 26, and the frame synchronization bit extraction circuit (FSD) 27.

The frame synchronization circuit (FSY) 24 is unipolar/NR
Frame synchronization is detected from the unipolar digital signal transmitted from the Z conversion circuit (UNC) 23.1. Further, the multi-frame synchronization circuit (MFS) 25 detects multi-frame synchronization from the unipolar format digital signal transmitted from the unipolar/NRZ conversion circuit (UNC) 23, and furthermore, the alarm detection circuit (ALD) 26 detects multi-frame synchronization from the unipolar digital signal transmitted from the unipolar/NRZ conversion circuit (UNC) 23 Using the unipolar digital signal transmitted from the conversion circuit (UNC) 23, fault information regarding the digital transmission path 1, such as an abnormality in signal reception transmitted from the opposite station, is detected.

If the frame synchronization circuit (FSY) 24 cannot detect frame synchronization, the multiframe synchronization circuit (MFS) 2
5 cannot detect multi-frame synchronization, it outputs fault information indicating frame synchronization failure or multi-frame synchronization failure, respectively, and outputs failure information indicating failure of frame synchronization or multi-frame synchronization, and sends it to the channel device (DSM) together with the failure information detected by the alarm detection circuit (ALD) 26. )3 (
(Figure 3) via call processing equipment (CPR)? (Figure 3)
to communicate.

On the other hand, the frame synchronization bit extraction circuit (FSD) 27 branches the frame synchronization bit FS from the unipolar format digital signal transmitted from the unipolar/NRZ conversion circuit (UNC) 23, and outputs the frame synchronization bit FS to the elastic store circuit (ES).
28 in the order of arrival.

On the other hand, a counting circuit (CNT) 81 provided in the interface device (INF) 8 counts the clock signals used in the digital exchange, and calculates the elastic store circuit (CNT) in each digital terminal (DT) 2 to be multiplexed. E
S) 28.

As a result, the frame synchronization bits FS stored in each elastic store circuit (ES) 28 are extracted in the order of storage in synchronization with the clock signal within the digital exchange and transmitted to the multiplex circuit (MPX) 82. .

The multiplex circuit (MPX) 82 includes an elastic store circuit (ES) 28 of five sets of digital terminals (DT) 2.
The frame synchronization bits FS transmitted from the terminal are multiplexed and sent to the terminating device (TM) 6 (Fig. 3) via a communication path fixedly set in the communication path device (DSM) 3 (Fig. 3). introduce.

On the other hand, when the call processing device (CPR) 7 receives fault information from the digital terminal (DT) 2, the call processing device (CPR) 7
The data is transferred to the terminal device (TM) 6 connected via the communication path within the DSM) 3, and then transferred to the digital terminal (DT) 2.
It is notified that the frame synchronization bit FS transmitted via the communication path in the communication path device (DSM) 3 is abnormal.

When the terminating device (TM) 6 receives failure information from the call processing device (CPR) 7, it sends the digital terminal (TM)
The message bit D in the frame synchronization bit FS transmitted from DT) 2 is determined to be invalid, and editing and output of the maintenance message is stopped.

[Problem to be solved by the invention]

As is clear from the above description, in conventional digital terminals, only the frame synchronization signal (FS) including the message bit/node D is transmitted via the communication path in the communication path device (DSM) 3 to the termination device (TM). ) 6, and fault information indicating various faults occurring in the digital transmission path 1 is transmitted to the call processing device (CPR) 7.
was being transferred to the terminal device (TM) 6 again, so the timing at which the terminal device (TM) 6 determines that the message bit D transmitted from the digital terminal (DT) 2 is invalid is delayed. There was a risk that the messages would be edited and output.

SUMMARY OF THE INVENTION An object of the present invention is to enable a terminating device to determine the invalidity of a transmitted frame synchronization bit as quickly as possible.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 1 is a digital transmission path, 20 is a line compatible device accommodating the digital transmission path 1, 3 is a communication path device constituting a digital exchange, and 6 is a termination device.

Reference numeral 100 denotes frame synchronization bit extraction means provided within the line compatible device 20.

Reference numeral 200 denotes a fault information insertion means provided in the line compatible device 20 according to the present invention.

[Effect]

The frame synchronization bit extraction means 100 extracts the frame synchronization bit arriving from the digital transmission path l, and transmits it to the termination device 6 via the communication path device 3.

The fault information insertion means 200 detects a fault occurring in the digital transmission path 1 and inserts fault information indicating the occurrence of the fault into a predetermined part of the frame synchronization bits extracted by the frame synchronization bit extraction means 100.

Therefore, fault information is directly transmitted from the line compatible device to the terminating device using a predetermined portion of the frame synchronization bits, and the validity of the information transmitted from the line compatible device to the terminating device is determined by the remaining frame sync bits. Immediate determination can be made, and invalidation processing of the terminal device for invalidation information can be quickly stopped.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a digital terminal according to an embodiment of the present invention. Note that the same reference numerals refer to the same objects throughout the plan. The target digital exchange is as shown in Figure 3, and the data format of the digital transmission line is the 4th one.
As shown in the figure.

In FIG. 2, a frame synchronization bit extraction circuit (F
A failure information insertion circuit (ALI) 29 is provided as the failure information insertion means 200 in FIG.

Also in FIG. 2, a bipolar digital signal arriving from the digital transmission path 1 is transferred to a bipolar-unipolar conversion circuit (BUC) 21 as in FIG.
is converted to unipolar form by
It is converted into an NRZ format digital signal by the RZ conversion circuit (UNC) 23, and then sent to the frame synchronization circuit (FSY) 24.
, a multi-frame synchronization circuit (MFS) 25, an alarm detection circuit (ALD) 26, and a frame synchronization bit extraction circuit (
FSD) 27.

The frame synchronization circuit (FSY) 24 detects frame synchronization from the unipolar format digital signal transmitted from the unipolar/NRZ conversion circuit (UNC) 23, as in FIG.
S) 25 is also unipolar N as in FIG.
Multi-frame synchronization is detected from the unipolar digital signal transmitted from the RZ conversion circuit (UNC) 23, and the alarm detection circuit (ALD) 26 also converts the unipolar/NRZ conversion circuit (UNC) as in FIG. 23
Fault information regarding the digital transmission path 1, such as an abnormality in signal reception transmitted from the opposite station, is detected by the unipolar digital signal transmitted from the opposite station.

If frame synchronization diagram 1 (FSY) 24 cannot detect frame synchronization, multiframe synchronization circuit (MFS) 2
5 cannot detect multi-frame synchronization, it outputs fault information indicating frame synchronization failure or multi-frame synchronization failure, respectively, and outputs fault information indicating fault information detected by alarm detection circuit (ALD) 26 as well as fault information insertion circuit ( ALr)
29.

As a result of the above, unipolar/NRZ conversion circuit (UNC) 2
Frame synchronization bits transmitted from FSO 3, 4th, 8th, 12th, 16th, 20th and 24th frames used for frame synchronization F4, Fil, F1□
, FI6%F2° and F24 frame sync bit F
S, and second, sixth, tenth, fourteenth, eighteenth and twenty-second frames F2, F6 used for error detection and correction.
, Fl. , F14, Flll and F2□ frame synchronization bits FS, i.e. even frames Fz, F4,...
, F24's frame synchronization bit FS has achieved its purpose and is no longer needed.

On the other hand, the frame synchronization focus extraction circuit (FSD) 27
As in the figure, a unipolar/NRZ conversion circuit (U
The frame synchronization bits FS branched from the unipolar digital signal transmitted from the NC) 23 are stored in the elastic store circuit (ES) 28 in the order of arrival, and then stored in the counting circuit provided in the interface device (INF) 8. (CNT) 81 is extracted in the order of accumulation in synchronization with a clock signal generated by the fault information insertion circuit (ALI) 29.

The fault information insertion circuit (ALI) 29 inserts the frame synchronization circuit (FSY) 24, The fault information transmitted from the multi-frame synchronization circuit (MFS) 25 and the alarm detection circuit (ALD) 26 is inserted, and the interface device (I
It is transmitted to a multiplex circuit (MPX) 82 in NF) 8.

The multiplex circuit (MPX) 82 multiplexes the frame synchronization bits FS transmitted from the failure information insertion circuits (ALI) 29 of the five sets of digital terminals (DT) 2, and transmits the frame synchronization bits FS to the channel equipment (DSM) 3 (FIG. 3). The information is transmitted to the terminating device (TM) 6 (FIG. 3) via a communication path that is fixedly set within the terminal.

The terminal device (TM) 6 is a digital terminal (DT)
The frame synchronization bit FS transmitted from 2 to the channel in the channel device (DSM) 3 is set to an odd frame F, ,
F, ,..., for F23 and even frames FZ, F4,
..., separated into F24 and even frames F, ,F
4. When detecting that fault information has been inserted into the frame synchronization bit FS of F24, the message information inserted into the frame synchronization bit FS of odd frames F+, F:l, ..., FZ3 is detected. Bin) D is determined to be invalid, and editing and output of maintenance messages are stopped.

As is clear from the above description, according to this embodiment, fault information indicating the occurrence of a fault in the digital transmission path 1 is inserted into the frame synchronization bit FS of the even numbered frame F, and inserted into the frame synchronization bit FS of the odd numbered frame F. The received message bit D is directly transmitted to the terminating device (TM) 6 via the communication path set in the communication channel device (DSM) 3, so the terminating device (TM) 6 receives the received message bit D. It becomes possible to immediately determine that D is invalid, and it becomes possible to immediately stop processing for invalid message bit D.

Note that FIGS. 2 to 4 are only one embodiment of the present invention, and for example, the data format of the digital transmission line 1 is not limited to that shown in the figures, and many other modifications may be considered. However, the effects of the present invention remain the same in either case. Furthermore, the configuration of the line compatible device 20 (FIG. 1) is not limited to the illustrated digital terminal (DT) 2, and many other modifications may be considered; however, the effects of the present invention can be achieved in any case. remains unchanged.

〔Effect of the invention〕

As described above, according to the present invention, in the line compatible device, failure information is directly transmitted from the line compatible device to the terminating device using a predetermined part of the frame synchronization bits, and the remaining part of the frame synchronization bit is transmitted to the line compatible device. The validity of the information transmitted from the to the end device can be immediately determined,
Invalidation processing of the terminal device for invalid information can be quickly stopped.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing a digital terminal according to an embodiment of the present invention, Fig. 3 is a diagram showing an example of a digital switching device to which the present invention is applied, and Fig. 4 is a diagram showing the digital terminal according to an embodiment of the present invention. 3 is a diagram illustrating the data format of the digital transmission line in FIG. 3, and FIG. 5 is a diagram illustrating an example of a conventional digital terminal. In the figure, ■ and 5 are digital transmission paths, 2 and 4 are digital terminals (DT), 3 is a channel device (DSM), 6 is a termination device (TM), 7 is a call processing device (CPR), and 8 is an interface. Equipment (INF)
, 20 is a line compatible device, 21 is a bipolar-unipolar conversion circuit (BUC), and 22 is a clock extraction circuit (CE).
X), 23 is a unipolar/NRZ conversion circuit (UNC)
, 24 is a frame synchronization circuit (FSY), 25 is a multi-frame synchronization circuit (MFS), 26 is an alarm detection circuit (ALD), and 27 is a frame synchronization bit extraction circuit (FSY).
SD), 28 is an elastic store circuit (ES),
29 is an error information insertion circuit (ALI), 81 is a counting circuit (
CNT), 82 is a multiplex circuit (MPX), 100 is a frame synchronization bit extraction means, 200 is a failure information, 446B
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■ 31m1m, 31m1m, 6m, 9m, 7m, 7m, 3m, %m

Claims (1)

[Claims] A line compatible device (2) that accommodates a digital transmission path (1) and connects to a communication path device (3) constituting a digital exchange.
0), a frame synchronization bit extraction means (10) extracts a frame synchronization bit arriving from the digital transmission path (1) and transmits it to the termination device (6) via the communication path device (3);
0), detecting a failure occurring in the digital transmission line (1),
A fault information transmission system comprising: fault information insertion means (200) for inserting fault information indicating the occurrence of the fault into a predetermined part of the frame synchronization bits extracted by the frame synchronization bit extraction means (100). .