JPH02143605A - Variable impedance circuit - Google Patents

Abstract

PURPOSE:To decrease number of components and to simplify the constitution by controlling the current flowing to a 1st and a 2nd transistor (TR) managing the control performance of the impedance with a 3rd transistor (TR). CONSTITUTION:Bases and collectors of transistors (TRs) Q1 - Q4 are connected respectively in common. Then a control current Ir is fed to a common base connecting point of the TRs Q3,Q4 and a bias current is supplied to an emitter connecting point. Thus, the emitter of the TRs Q3,Q4 acts like an imaginary ground point and the shunt of the impedance is implemented by the emitter of the TR Q1 and a resistor R1, and the emitter of the TR Q2 and a resistor R1'. Through the constitution above, the current division is controlled smoothly by arranging the Trs Q3,Q4 to the most effective imaginary ground point and the impedance change and the linearity equal to the ladder circuit network using lots of components are realized with a few component number.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a control current to a base common connection point of a plurality of transistors of the same polarity whose bases and collectors are respectively commonly connected. This invention relates to improvements in variable impedance circuits that control the impedance between the emitters of each transistor.

(Prior art) As is well known, the variable impedance circuit as shown in the beginning is
Conventionally, it has been configured as shown in FIG. That is, the bases and collectors of the NPN transistors Q1 to Q6 are commonly connected. And transistor Q5. A control current Ir is supplied to the base common connection point of QB.

Also, between the emitters of transistors Ql and Q3, transistor Q3. Q5, between the emitters of transistors Q2. Q4
and between the emitters of transistor Q4. Resistors R1, R2, R1', and R2' are interposed and connected between the emitters of QB, respectively. Furthermore, transistor Q5. Q[i
Resistors R3 and R3' are connected in series between the emitters, forming a ladder network as a whole. Also,
A bias current I is supplied to the connection point of the resistors R3° and R3'.

Such a variable impedance circuit controls gIJ current I
When increasing gradually from 0, first transistors Q5 and Q8 become conductive, then transistor Q3
．． Q4 becomes conductive, and finally transistors Ql and Q
2 is in a conductive state, and the change in impedance with respect to the change in control current 1r is controlled to have maximum linearity.

However, the conventional variable impedance circuit as described above has a problem in that the structure is complicated and economically disadvantageous due to the large number of elements. Furthermore, since a ladder circuit network is formed, it is difficult to set the value of each resistor and the bias current I. In particular, since the current diversion amount is determined by the resistor and the emitter impedance of the transistor, it is difficult to stabilize the impedance against temperature fluctuations.

Therefore, recently, as shown in Japanese Patent Publication No. 63-36162, for example, it has been considered to form a ladder network in a distributed constant manner using special lateral PNP transistors.

According to such means, although the element area becomes slightly larger, it is possible to form a ladder circuit network with one element,
The configuration can be simplified. Furthermore, if the resistance value and bias current are set appropriately, there is an advantage that they can be automatically determined from the element characteristics with respect to the control current.

However, in variable impedance circuits in which special lateral PNP transistors are used to form a ladder network with distributed constants, impedance stabilization against temperature fluctuations has not yet been improved. be. Additionally, since the frequency characteristics of lateral PNP transistors are basically inferior, the impedance becomes capacitive in the high frequency band, and when used as the impedance between the emitters of a differential transistor, the frequency characteristics tend to peak, making it undesirable. There is also the problem of not having one.

(Problems to be Solved by the Invention) As described above, in the conventional variable impedance circuit, it is not possible to stabilize the impedance against temperature fluctuations, and there are also disadvantages due to the use of transistors with poor frequency characteristics. There is a problem.

Therefore, this invention was made in consideration of the above circumstances, and it is possible to simplify the configuration by reducing the number of elements, stabilize impedance against temperature fluctuations, and improve frequency characteristics. It is an object of the present invention to provide an extremely good variable impedance circuit that does not require the use of inferior transistors.

[Structure of the Invention] (Means for Solving the Problems) A variable impedance circuit according to the present invention includes first and second transistors having the same polarity and having bases and collectors connected in common, and the first and second transistors having the same polarity. a third transistor having the same polarity as the second transistor and whose base and collector are commonly connected to the bases and collectors of the first and second transistors, respectively; a first resistor and a second resistor respectively interposed and connected to the emitter of the transistor, supplying a control current to a common connection point of the bases of the first and second transistors, and supplying a control current to a common connection point of the bases of the first and second transistors; A bias current is supplied to the transistor, and the amount of current flowing to the first and second transistors is controlled by the third transistor.

(Function) According to the above configuration, since the third transistor controls the amount of current flowing through the first and second transistors that govern impedance controllability, a ladder circuit network is not configured. However, it is possible to achieve impedance change and linearity equivalent to a ladder circuit network using a large number of elements with a small number of elements, simplifying the configuration, and reducing impedance against temperature fluctuations. It can be stabilized, and it becomes unnecessary to use transistors with poor frequency characteristics.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as in FIG. 3 are indicated with the same symbols. That is, from FIG. 3, transistor Q5. Q6 and resistance R2, R3, R2°, R
3° and transistor Q3. The emitter of Q4 functions as a virtual ground point, and impedance shunting is performed only by the emitter of transistor Ql and resistor R1, and by the emitter of transistor Q2 and resistor R1'.

According to such a configuration, although no ladder circuit network is configured, transistors Q3. Q4
By arranging the transistors, the amount of current in the current shunt can be smoothly controlled, that is, the amount of current flowing through the transistors Ql and Q2, which govern the controllability of impedance, can be sufficiently controlled. , impedance change and linearity equivalent to a ladder circuit network using a large number of elements can be realized with a small number of elements, and the configuration can be simplified.

In this case, when the base-emitter voltages of the transistors Ql-Q4 are equal to each other, no current flows through the resistor R1°Rlo. In other words, in this state, if the emitter areas of transistors Q1 to Q4 are equal, the current flowing through the base-emitter junction is the bias current!
is realized when it is equal to . This clearly shows that if the bias current I is stable, the impedance in this state is also stable or easily stabilized.

Also, like the lateral PNP transistor mentioned above,
Since it can be configured with NPN transistors without using special elements with poor frequency characteristics, the impedance is less likely to be tolerant in a high frequency band.

Next, FIG. 2 shows another embodiment of this invention.

That is, in this case, transistors Q3Q4 are replaced with one transistor Q7. In this case, by making the emitter area of transistor Q7 twice the emitter area of transistors Ql and Q2,
The same operation as the embodiment shown in FIG. 1 can be performed, and the number of elements can be further reduced.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to simplify the configuration by reducing the number of elements, stabilize impedance against temperature fluctuations, and improve frequency characteristics. It is possible to provide an extremely good variable impedance circuit that does not require the use of transistors with inferior quality.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of a variable impedance circuit according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional variable impedance circuit. FIG. Applicant's Representative Patent Attorney Takehiko Suzue

Claims (1)

[Claims] first and second transistors having the same polarity and having bases and collectors commonly connected to each other; a third transistor commonly connected to the collector; and first and second resistors interposed and connected between the emitter of the third transistor and the emitters of the first and second transistors, respectively. supplying a control current to a base common connection point of the first and second transistors, supplying a bias current to the emitter of the third transistor, and supplying a bias current to the emitter of the third transistor;
and a variable impedance circuit configured to control the amount of current flowing through the second transistor.