JPH02141801A - Multiplexing controller - Google Patents

Abstract

PURPOSE:To synchronize controller outputs without a complicated synchronizing circuit or the like by using the output of an astable multivibrator constituted by combination of logic circuits as the synchronizing clock. CONSTITUTION:In this multiplexing controller, controllers 1a and 1b are provided with exclusive OR circuits (EXOR) 6a and 6b and frequency dividing circuits 7a and 7b. These two EXORs 6a and 6b constitute the astable multivibrator. Respective output signals S3a and S3b have frequencies divided by frequency dividing circuits 7a and 7b and are applied to arithmetic circuits 2a and 2b as synchronizing clocks S2a and S2b. Controllers 1a and 1b are synchronized by this simple constitution. Consequently, a synchronizing circuit having a complicated constitution is unnecessary, and the number of elements is considerably reduced, and the reliability of the multiplexing controller is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a multiplex control device suitable for synchronizing multiple control devices for process control.

(Prior Art) In recent years, control devices used for process control that require high reliability are often multiplexed. The outputs of the multiplexed control devices are selected by a selection circuit and output to the process as control outputs. In this selection circuit, the outputs of each multiplexed control device must be output in synchronization, and if the arithmetic operation of the control device is controlled by a clock, the synchronous circuit links the multiplexed control devices. Conventionally, a method has been used to synchronize the calculation operations of the control device.

FIG. 4 shows a conventional configuration of such a multiplex control device. Arithmetic circuits 2a, 2 of duplicated control devices 1a, lb
Control calculation is performed at b, and the result is the control device output 8.
1a and Szb are outputted to the selection circuit 3. In this selection circuit 3, the output of one of the control devices is outputted to the process 4 to be controlled. At this time, if the control device output 81a * S x b output to the selection circuit 3 needs to be synchronized such as pulse output, a synchronization circuit 5 that generates a common lock is provided, and the generated synchronization clock S
2 is applied to the multiplexed control devices 1a and lb. Then, each arithmetic circuit 2a,
By controlling the operation of S1.2b, the control output S1. , Slb are synchronized.

(Problems to be Solved by the Invention) However, in the above conventional multiplex control device,
The synchronous circuit becomes a complex circuit including a clock oscillator, a frequency divider circuit, etc. For this reason, failures tend to occur in the synchronous circuit, and even if the control devices are multiplexed to improve reliability, this complicated synchronous circuit poses a problem in that it becomes an obstacle to reliability.

Further, in the conventional multiplex control device, a synchronization circuit type must be added when multiplexing the control devices, which is not easy when multiplexing the control devices as necessary.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplex control device that can achieve synchronization between control devices with an extremely simple configuration.

[Structure of the Invention] (Means for Solving the Problem) The present invention provides a logic circuit that inverts and outputs the signal level input to each control device, and inverts the output of the logic circuit provided in one control device. The logic circuits between each control device constitute an unstable multivibrator as an input to the logic circuit provided in the other control device, and each control device uses the output of the logic circuit as a synchronization clock.

(Function) By configuring an unstable multivibrator between multiplexed control devices by combining logic circuits and using its output as a synchronization clock, the outputs of each control device can be synchronized without using complicated synchronization circuits. can be done.

That is, it is possible to cope with multiplexing of control devices with a simple configuration of adding a logic circuit to the multiplexed control device.

(Embodiment) FIG. 1 is a configuration diagram of a multiplexing control device showing an embodiment of the present invention. In FIG. The difference from the configuration shown in FIG. 4 is that each control device 1a, Ib
The main difference is that they each include exclusive OR circuits (hereinafter abbreviated as EXOR) 6a, 6b and frequency dividing circuits 7a, 7b. One input terminal of EXOR6a has “H”
” level signal is input, and the other input terminals are EXOR
6b's output signal S 3 b is input. Also, EXO
[Lj level signal is input to one input terminal of R6b, and the output signal 53 of EXOR6a is input to the other input terminal.
m is input. Therefore, these two EXOR6a,
6b constitutes an unstable multivibrator. In addition, the output signal 82a of each EXOR6a, 6b
eS3b is frequency-divided by frequency dividing circuits 7a and 7b, respectively, and then converted into a synchronous clock 82a + S2b.
is applied to each arithmetic circuit 2a, 2b as follows.

Although the control devices 11a and Ib each have an internal clock and operate at independent sampling times, it is assumed that these internal clocks are substantially synchronized.

Now, as shown in FIG. 2(a), the sampling time based on the internal clock of the control device 1a is
t13 T ta+..., while the control device 1b
It is assumed that the internal clocks of the two control devices 1a and 1b are substantially synchronized with the phase difference shown in the figure. In this state, the sampling time t on the control device 121a side
When the output signal S 311 of EXOR6a rises to rH,1 at ax, this output signal Sffa becomes EXOR6b
is input into EXORGb at sampling time jbt on the control bag 5i1b side, and exclusive OR operation with the other input signal rlJ is performed. As a result, its output signal S at the next sampling time tbz.

, rises to "H". This signal Sib is EXOR6a
becomes the input, and the sampling time t on the control device la side
It is taken into the EXOR 6a at a3, and an exclusive OR operation with the other input rH is executed. As a result, the output signal 83M becomes “L” at sampling time ta4.
"fall into. Thereafter, by similarly changing the signal level of the output signal 33M of EXOR6a, EXOR
The output signal level of 6b changes and the result is output again to EXO.
The operation reflected in the level change of the output signal of R6a is repeated. In this way, each EXOR 6a, 6b outputs rH at a period T determined by the internal clock at that time.
Clock signal S3a whose level changes to J, rJ
y S 3 b is obtained.

The period T of this clock signal S x a * S 3 b
is expressed as T=6F, where F is the period of the internal clock of each control device 1a, lb. On the other hand, when there is no phase shift between the two internal clocks and they are completely synchronized, the maximum value is T=8F.

In other words, the period T of the clock signal Sags Ssb is T
≦8F...(1).

By the way, these clock signals 83 a + 53
b are synchronized with a certain phase difference, as shown in FIG. 2(a). This phase difference is determined by the clock signal S,...
By dividing S and b through frequency dividing circuits 7a and 7b, it is possible to make them relatively small.

For example, if the frequency dividing circuits 7a and 7b are 1/4 frequency dividing circuits, the phase difference between the clock signals S 3 a t S 3 b will be approximately π/2 to π/2, as shown in FIG. 2(b). It decreases to 16.

Therefore, the output S 2 a of the frequency dividing circuits 7a and 7b
By using eS2b as a synchronization clock, a synchronized control device output S□atsxb can be taken out from each control device 1a, lb to the selection circuit 3. Of course, if the phase difference between the clock signals S 311 t S 3 b is allowable, it goes without saying that the frequency dividing circuits 7a and 7b can be omitted.

In this way, each control device g (la, lb has an EXO
The control devices fila and lb can be synchronized with a very simple configuration in which R6a and R6b are provided and each output is returned to each other's input side to form an unstable multivibrator. Therefore, according to this configuration, there is no need for a synchronous circuit with a complicated configuration that was required in the past, and the number of elements can be significantly reduced compared to the conventional configuration, reducing the failure rate and significantly improving reliability. can.

Further, according to the configuration of this embodiment, EXOR6a.

In the output of 6b, the side inputting "H" to one input takes the lead, and the side inputting "L" follows the former.

This makes it possible to perform priority control, such as setting the calculation output of the control device that precedes the EXOR output as the clock as the regular side, and setting the calculation output of the control device of the following clock as the standby side.

In addition, in this embodiment, an example using EXOR as the logic circuit was shown, but the rH of the gate output of the groove control device
r[, the output is "H" according to J.

The effect is the same if it is a logic circuit that inverts "L", and specifically, the negative logical AND (l (AND) circuit,
It can also be realized using a NOR) circuit. Furthermore, although this embodiment has described a duplex configuration, by combining similar techniques,
For example, by connecting EXORs provided in each control device in a ring shape, it is possible to apply the present invention to a triplex or higher multiplex configuration.

Further, by simply incorporating EXOR into each control device in advance, the configuration can be easily changed to a multiplexed configuration later.

By the way, according to the above embodiment, if one side of the duplicated control device fails and the EXOR output is no longer updated, the EXOR output of the normal control device of the other system will also not be updated, and therefore one system will fail. Sometimes, there are problems that even normal control devices become unusable. FIG. 3 shows an embodiment in which such a problem is eliminated and the EXOR output can be used as a clock in a normal control device even when the first system control device is abnormal. In the figure, the same symbols as in Figure 1 are the same.
In the figure, only the part that generates the synchronization tack on the side of one control device la is shown. In this figure, one input of the EXOR 6a is connected to the EX of the other control groove device 1b.
Input the output Sib of OR6b, and input the output S of EXOR6a.
This embodiment is similar to the embodiment shown in FIG. 1 in that the signal 3a is output to the other control groove device 1b. Furthermore, in this figure, one input of EXOR in FIG.
was input, the output S1 of the output monitoring circuit 8a
．． is being entered. This output monitoring circuit 8a normally
” or outputs the determined value of rLJ, but EXO
Output S3 of R6a. input, and it is rH for a certain period of time or more.
If the output 83M continues for a certain period of time, it outputs ``L'', and if the output 83M continues for a certain period of time, it outputs ``H'', and can be constructed from an on-delay timer and a gate circuit. That is, when the low control device fails and the HXOR output Sah of the low control device becomes "L", the normal output of the output monitoring circuit 8a is "H", E
XOR output S output a remains rHJ (7).

If this [Hj continues for a certain period of time or more, the output monitoring circuit outputs S. becomes [L], so the output S of EXOR6a. becomes rLj. Similarly, the output S 31 of EXOR6a
1 continues at rJ, the output S4.
returns to rHJ, and the output S of HXOR6a becomes "H".The fixed time period monitored by this output monitoring circuit 8a is as follows. 1/ of the maximum clock period F, shown in equation (1)
By setting the number of clocks to 2 or more, even if one system of the duplicated control devices becomes abnormal, a clock with approximately the same period can be obtained using only one system of the normal control devices.

[Effects of the Invention] As described above, according to the present invention, a multiplex control device that requires synchronization can be realized by adding extremely simple circuits. As a result, it is possible to improve the reliability and efficiency of the multiplex control device by increasing the reliability of the synchronization circuit.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a multiplexing control device showing one embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the clock section of the multiplexing control device, and FIG. 3 is a diagram showing another embodiment of the present invention. FIG. 4 is a block diagram of a main part of a multiplex control device showing an example. FIG. 4 is a block diagram of a conventional multiplex control device. la, lb...control device, 2a, 2b...arithmetic circuit, 3...selection circuit, 4...process, 6a, 6b
-EXOR, 7a. 7b... Frequency dividing circuit, 8a... Output monitoring circuit. Agent Patent Attorney Crest 1) Makoto / Figure 2 (b) lb Figure 1 Figure 3 1b Figure 4

Claims (1)

[Claims] In a multiplex control device that synchronizes the outputs of each control device by applying a synchronous clock to each arithmetic circuit of a plurality of control devices, the signal level input to each control device is inverted. By providing a logic circuit that outputs an output signal, and by sequentially connecting the output side of one logic circuit to the input side of the other logic circuits, the entire logic circuit provided in each control device can be connected in a ring shape. A multiplex control device forming an oscillation circuit and using the output of the logic circuit as a synchronization clock in each control device.