JPH0214142U

JPH0214142U -

Info

Publication number: JPH0214142U
Application number: JP9011388U
Authority: JP
Priority date: 1988-07-07
Filing date: 1988-07-07
Publication date: 1990-01-29

Description

[Brief explanation of drawings]

図面は本考案の半加算器を示す回路図である。６，７，２７……インバータ、１１，３１……
第１の論理ゲート、１６，３６……第２の論理ゲ
ート、２１……ＡＮＤゲート、２２，４１……Ｎ
ＡＮＤゲート、４２……ＮＯＲゲート。 The drawing is a circuit diagram of a half adder according to the present invention. 6, 7, 27... Inverter, 11, 31...
First logic gate, 16, 36... Second logic gate, 21... AND gate, 22, 41...N
AND gate, 42...NOR gate.

Claims

[Claims for Utility Model Registration] (1) In a half adder that adds N (N: natural number) bits of input data and a previous stage carry to obtain N bits of output data and a subsequent stage carry, the N bit input Lower n in the data (1≦n≦N
-1, n: natural number) bits and the carry of the previous stage, and input data of the lower 1 bit of the input data of the N bits, the carry of the previous stage, and the N bits. a second logic gate that receives input data of the lower n+1 bits of the input data and the output of the first logic gate and outputs the N-bit output data, and inputs the N-bit input data. A half adder comprising: a third logic gate; and a fourth logic gate that inputs the outputs of the previous stage carry and the third logic gate and outputs the latter stage carry. (2) The half adder according to claim 1, further comprising a buffer for inputting the previous stage carry to the first logic gate.