JPH02140847A - System for controlling cache memory in multi-processor - Google Patents

Abstract

PURPOSE:To reduce the confliction of the check of rewritten addresses in respec tive cache memories and an access from a processor by permitting a processing unit rewriting a main memory to output specified information. CONSTITUTION:The processing units 1-3 rewriting the main memory 5 outputs a write address and cache memory storage information being information whether non-contradinction security control is required (a block including rewritten data is set to be an object for storage for cache memories 11, 21 and 31) or not. The other processing units 1-3 check the write address and make it to be invalid (or rewrite) only when data to be the object for storage in the self cache memory is rewritten by the information. Thus, the number of times for checking the write address, which is performed in respective processing units 1-3, is reduced, and the confliction of the check of the write address and the access from the processors 10-30 to the cache memories 11, 21 and 31 can be reduced.

Description

[Detailed description of the invention] [Industrial application field]

The present invention provides a multiprocessor having a plurality of processing units each having a processor and a cache memory, and a main memory interconnected with them via a system bus. The present invention relates to a cache memory control method for performing consistency guarantee control for data.

[Prior art 1] In a multiprocessor system in which a plurality of processing units share a main memory, when each processing unit has a cache memory, the data in the main memory rewritten by the processing unit A is transferred to the cache memory. It is essential to perform consistency guarantee control (-number control) between the data in the cache memory of each processing unit and the data in the main memory so that the processing unit does not execute incorrect processing. It is. Generally, cache memory consists of multiple entries,
Each entry consists of a tag section that stores block address information, a data section that stores block data, and a valid section that indicates whether the contents stored in the tag section and data section are valid or invalid. It consists of. When the processing unit rewrites data in the main memory specified by address a, rewriting between the cache memory and the main memory within the processing unit is controlled by the processing unit. Consistency guarantee control between the cache memory and main memory of other processing units is performed as follows. That is, the cache memory inputs the rewritten address a (write address) of the main memory and searches for the tag part of the entry marked as valid in the valid part. As a result of the search, when a block containing the data specified by the write address a exists in the cache memory, the valid part of the entry storing the block is set to invalid. As mentioned above, in the conventional cache memory and main memory consistency guarantee control method, it is checked whether data in the main memory that has been rewritten by another processing unit exists in the cache memory, and if the data exists in the cache memory. If there was, the data would have been invalidated. [Problems to be Solved by the Invention] However, in the case of the conventional method described above, in the cache memory of each processing unit, for all write addresses from other processing units, the block containing the write address is stored in the cache memory. It was necessary to check whether it was stored or not. As a result, the following contention occurs, resulting in the time it takes for the processor to access the cache memory. (1) Conflict between the input of a write address to the cache memory for performing consistency guarantee control and the input of an address for the processor to access data in the cache memory. (2) Conflict between the tag section search for performing consistency guarantee control for write addresses and the tag section search for the processor to access data in the cache memory. As a method for reducing the above-mentioned contention, a method has conventionally been proposed for the contention (1) in which a dedicated bin is provided for inputting a write address into the cache memory. In addition, in order to deal with the conflict in (2), a method has been proposed in which 211M tag sections are provided to store the same information in the cache memory, one is used for access from the processor, and the other is used for checking the write address. . However, the method of providing dedicated bins has the disadvantage that the number of bins in the cache memory increases. Furthermore, the method of providing two tag sections has the disadvantage that redundant information is included in the cache memory. Therefore, it is an object of the present invention to propose a new cache memory control method for a multiprocessor that does not have the above-mentioned drawbacks.

[Means to solve the problem]

According to the cache memory control method in a multiprocessor according to the present invention, the processing unit that rewrites the main memory needs to perform consistency guarantee control along with the write address (the block containing the rewritten data is to be stored in the cache memory). ), and other processing units output cache memory storage information, which is information on whether data is stored in their own cache memory (data that is not prohibited to be stored in their own cache memory). The write address is checked and invalidated (or rewritten) only when the stored data is rewritten.

[Action/effect]

Therefore, when data that is not to be stored in its own cache memory is rewritten by another processing unit, the cache memory does not need to perform consistency guarantee control for the write address, and each process The number of write address checks performed by the unit is reduced, and contention between write address checks and accesses from the processor to the cache memory can be reduced.

【Example】

Next, an embodiment of a cache memory control method in a multiprocessor according to the present invention will be described. FIG. 1 shows an embodiment in which cache memory storage information is stored in a processor using a main 11 memory control method in a multiplexer according to the present invention. The cache memory storage information consists of 24 entries, and each entry consists of 3 bits of information. In this case, the main memory is divided into 16 (2') parts, each of which corresponds to 3 bits of cache memory storage information. The first bit of the 3-bit cache memory storage information specifies whether storage in the cache memory of processing unit 1 is prohibited (rOJ) or permitted (“1”);
The second bit specifies whether to prohibit (rOJ) or permit (rlJ) storage in the cache memory of processing unit 2, and the third bit prohibits storage in the cache memory of processing unit 3 (rOJ). (NJ
). When the processor accesses an arbitrary address, the processor outputs 3-bit cache memory storage information stored in the entry specified by the upper 4 bits of address A along with the address information. FIG. 2 shows an embodiment of a cache memory control method in a multiprocessor according to the present invention. In FIG. 2, 1.2.3 indicates a processing unit. 4 indicates a system bus. 5 indicates main memory. 6 indicates a bus master controller. 10.20.30 indicates a processor. 11.21 and 31 indicate cache memories. 12.22.32 indicates the bus controller. 13.23.33 shows an AND circuit. 41 indicates an address bus. 42 indicates a data bus. 43 indicates a block request bus. 44 indicates a transfer response bus. 45 indicates a cache memory storage information bus of the processing unit 1. 46 indicates a cache memory storage information bus of the processing unit 2. Reference numeral 47 indicates a cache memory storage information bus of the processing unit 3. 48 indicates a rewriting instruction bus. 100.200.300 does not indicate a processor bus. 102.202.302.103.203.303.1
04.204.304.105.205.305 indicates a signal line. The cache memory 11.21.31 consists of a plurality of entries, each of which includes a tag section that stores block address information, a data section that stores block data, and whether the contents stored in the entry are valid. It consists of a valid part that indicates whether it is invalid. Transfer of blocks that are permitted to be stored in the cache memory is performed as follows. Processor 10 has address r10110100101J
(hereinafter referred to as a), the processor 0 outputs the address a of the data to be read onto the processor bus 100, and also outputs the cache memory storage information "110" (storage permission "1"). . The first bit of cache memory storage information r110J is “
1" and storage of the block in the cache memory is permitted. Therefore, if data at address a is stored in cache memory 1, cache memory 1 stores data at address a via chip bus 100. data is transferred to processor 0. If the data at address a is not stored in cache memory 1, the block is transferred from main memory 5 to cache memory 1 of processing unit 1 as follows. Since block B containing the data at address a requested from processing unit 1 via processor bus 100 does not exist in cache memory 1, cache memory 1 requests block transfer to bus controller 12 via signal line 101. instruct them to do so. The bus controller 12 notifies the bus master controller 6 of a request to use the system bus 4 via the signal line 102. The bus mask controller 1-0-controller 6 applies only one bus controller to the system bus 4 according to a predetermined procedure.
Grant permission to use. Permission to use the system bus 4 is granted via the signal line 103.
When given to bus controller 12, address bus 4
1, a block transfer request signal "1" is output to the block request bus 43, and a value "0" instructing readout is output to the fortune change instruction bus 48. The main memory 5 learns that a block is requested based on the value output on the block request bus 43 and the value output on the rewrite instruction bus 48, and writes the address output on the address bus 41. Block 3a containing data a is read and transfer of block 3a is started. The main memory 5 notifies the processing unit 1 via the transfer response bus 44 that the transfer of the block Ba is to be started, and outputs the block B onto the data bus 42. The bus controller 12 learns that the block B requested via the transfer response bus 44 is output on the data bus 42, and transfers the block B8 output onto the data bus 42 via the processor bus 100. The data is input to the cache memory 11. According to a predetermined procedure, the cache memory 11 writes the tag information of the address a into the tag section of the selected entry, writes the block B input via the chip bus 100 into the data section, and further, The valid part indicates validity and writes the value "1". When the block transfer is completed, the bus controller 12
Via the signal line 102, the bus master controller i-roller 6 is informed that the use of the system bus 4 has ended. Transfer of data that is prohibited from being stored in the cache memory is performed as follows. The processor 10 selects address r (LOOOllololo
When reading data of ``lolololololooloooooooolJ'' (hereinafter referred to as ""), the processor 10 outputs the address b of the data to be read onto the processor bus 100 and outputs the cache memory storage information "010". Since the first bits 1 to 1 of the cache memory storage information ro10J are "0" and storage of the block in the cache memory is prohibited, the data at address b is not stored in the cache memory 11 and the main memory 5
The transfer of data from to the processor 10 of the processing unit 1 takes place as follows. The bus controller 12 notifies the bus master controller 6 of a request to use the system bus via the signal line 102. Permission to use the system bus 4 is granted via the signal line 103.
When given to bus controller 12, address bus 4
1, a block transfer request signal "0" is output to the block request bus 43, and a value "0" instructing readout is output to the rewriting instruction bus 48. The main memory 5 learns from the block request signal output on the block request bus 43 that the block is not requested, reads the data at address b output on the address bus 41, and transfers it. Start. The main memory 5 instructs the processing unit 1 via the transfer response bus 44 to start transferring the data of the 7th address b.
and outputs the data on the data bus 42. The bus controller 12 learns that the requested data will be output onto the data bus 42 via the transfer response bus 44, and inputs the data output onto the data bus 42 to the processor 10 via the processor bus 100. do. When the data transfer is completed, the bus controller 12 notifies the bus master controller 6 via the signal line 102 that the use of the system bus 4 has ended. As described above, storage of block data in the cache memory is performed only when the value assigned to the own cache memory in the cache memory storage information output from the processor is "1". An operation in which the processor 10 replaces the data specified by the address a of the main memory 5, and a consistency guarantee i between the data in the main memory 5 rewritten by the processor 10 and the data in the cache memory 11.211.31, 11111 is performed as follows. When the processor 10 rewrites the data at address a on the main memory 5, the processor 10 outputs address bus rewrite data and cache memory storage information r110J to the processor bus 100. The cache memory 11 inputs the address a and the replacement data output on the processor bus, and searches the tag section of the entry storing information indicating that the valid section is valid. If there is an entry storing block B containing the data specified by address a, then the block

[Rewrite the data specified by address a included in cock B8 with the rewrite data input from the processor bus. If there is no internal entry for storing block B8 containing the data specified by address a, no replacement is performed. The bus controller 12 notifies the bus mask controller 6 of a request to use the system bus via the signal line 102. When permission to use the system bus 4 is given to the bus controller 12 via the signal line 103, the bus controller 1
2 outputs the address a on the address bus 41, outputs rewrite data on the data bus 42, further outputs a write instruction signal "1" on the write instruction bus 47, and also outputs the write instruction signal "1" on the write instruction bus 47. 1iiiI "110" is output on the information bus 45. The main memory 5 receives the write instruction on the white fill instruction bus 47 and writes the rewrite data output on the data bus 42 to the address a output on the address bus 41. In the processing unit 2, an AND circuit 23 combines the value of the internal instruction bus 48 and the second value of the cache memory stored information.
The value of the cache memory storage information bus 46 from which the bit is output is input, the value "1" is input to the cache memory 21 via the signal line 204, and the value "1" is input to the cache memory 21 via the signal line 204.
Informs that it is necessary to perform consistency guarantee control on the rewrite information output to the The cache memory 21 inputs the address a on the address bus 41 via the signal line 205, and receives an instruction (value "1") via the signal line 204 that it is necessary to perform consistency guarantee control. Then, block B containing data at address a. It is checked whether block B is stored in the cache memory 21, and if block B is stored, information indicating invalidity is written in the valid part of the entry in which block B is stored. In the processing unit 3, the AND circuit 33 connects the write instruction bus 48 and the cache memory storage information bus 47 to which the third bit of the cache memory storage information is output.
and input the value of signal line 3 to cache memory 31.
A value "0" is input through the system bus 4 to notify that there is no need to perform consistency guarantee control on the rewrite information output to the system bus 4. When the cache memory 21 receives address a on the address bus 41 via the signal line 205 and is instructed via the signal line 204 that it is necessary to perform consistency guarantee control, the cache memory 21 includes the data at the address a. It is checked whether block B is stored in the cache memory 21, and if block Ba is stored, information indicating invalidity is written in the valid part of the entry in which block B8 is stored. When the processing unit 1 finishes rewriting the main memory 5, the bus controller 12 notifies the bus master controller 6 via the signal line 102 that the use of the system bus 4 has ended. As a result, in order to perform consistency guarantee control, for all main memory addresses that have been rewritten by other processors, a check is performed to see if a block containing the address is stored in each cache memory. This eliminates the need for checking the swapped addresses in each cache memory and reduces contention between accesses from the processor. [Effect] As described above, according to the cache memory control method in a multi-process tree according to the present invention, for all main memory addresses that have been enriched by a processing unit, the block containing the address has not been rewritten. There is no need to check whether the address is stored in the cache memory of another processing unit that has not been used, and the number of times the rewritten address is checked in each cache memory can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment in which cache memory storage information is stored in a block by a cache memory control method in a multi-processor 4 according to the present invention. FIG. 2 is a systematic connection diagram showing an embodiment of a cache memory control method in a multiprocessor according to the present invention. 1.2.3... Processing unit 4... System bus 5...
・・・・・・・・・・・・Main memory 6・・・・・・
・・・・・・・・・Bass mask controller 10.2
0.30 ・・・・・・・・・・・・Processor 11.21
．． 31 ・・・・・・・・・・・・・・・Cache memory 12
．． 22.32 ・・・・・・・・・・・・・・・Bass control 13
．． 23.33 ・・・・・・・・・・・・AND circuit 41...
・・・・・・・・・・・・Address bus 42・・・・・・
・・・・・・・・・Data bus 43・・・・・・・・・
...Block request bus 44...
...Block transfer response bus 45...
. . . Cache memory storage information bus 46 of processing unit 1 . . . Cache memory storage information bus 47 of processing unit 2 . . . ......Main 11 memory storage information bus 48 of processing unit 3...Write instruction bus 100, 200, 300...・・・・・・・・・Figure 1 in front of Prosena bus

Claims (1)

[Claims] A multiprocessor having a plurality of processing units each having a processor and a cache memory, and a main memory interconnected with these units via a system bus, wherein the main memory is divided into a plurality of blocks. The processor has cache memory storage information for each block of the main memory that can uniquely specify whether or not to store the block in the cache memory of each processing unit; When reading data, the cache memory storage information is output together with the address of the data to be read, and the cache memory does not store the data to be read by the processor, and the cache memory storage information is transferred to its own cache memory. If the storage of data is not prohibited, transfer the block containing the data requested by the processor from the main memory to its own cache memory, and
] If the cache memory storage information prohibits storage in the own cache memory, the processing unit that performs the rewriting does not transfer the block from the main memory to the own cache memory. When rewriting the main memory, the (N-1) processing units output the cache memory storage information output by their own processor onto the system bus and do not rewrite the main memory. If the cache memory storage information output on the system bus does not prohibit storing the block containing the data to be rewritten in the local cache memory, the data in the local cache memory and the block that has been rewritten are not prohibited. A cache memory control method in a multiprocessor, characterized by performing control to guarantee consistency with data in the main memory.