JPH02135728A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform a selectively epitaxial growth at a relatively low temperature and formation of a metal silicide layer by forming an amorphous film, then heat-treating it to form a crystalline metal silicide and simultaneously selectively epitaxially growing silicon not used for silicifying on the surface of a silicon single crystalline region. CONSTITUTION:After an insulating film 2 covering the surface of a P-type Si substrate 1 is formed, an opening is formed the film 2, and the exposed face 1a of the Si single crystalline region is obtained. Then, an amorphous film 3 containing Si and remaining metal as constituent elements is formed by a sputtering method, etc., and N-type impurity ions 4 are implanted to the surface of the film 3. Thereafter, a noncrystalline film except the region containing the opening of the insulating film is removed by etching by an RIE method. Further, it is heat-treated at a relatively low temperature of 900 deg.C or lower. Thus, the amorphous film becomes a crystalline MoSi2 film 6. Simultaneously, an epitaxial layer 5 is grown on a single crystalline Si by crystal growing energy difference. In this manner, a selectively epitaxial growth of the silicon is conducted at a relatively low temperature, and simultaneously a metal silicide layer can be formed.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, the present invention relates to a method for manufacturing a semiconductor device. This relates to a manufacturing method that performs simultaneous formation in a consistent manner.

(Conventional technology) Technological progress toward higher integration and higher speeds in bipolar LSIs and other devices is remarkable.The so-called selective epitaxial growth technology in the element isolation process forms a relatively thick insulating film (oxide film) on an Sl substrate and performs RIE ( Etch an opening almost vertically in the insulating film using a reactive ion etching method, use the insulating film as an element isolation region, and form an element active region in a self-aligned manner on the silicon single crystal region exposed in the opening using a selective epitaxial growth method. It's technology. Such a selective epitaxial growth method facilitates higher integration and higher speed of semiconductor devices, and has therefore come into general practice. The conventional selective epitaxial growth method for silicon is
The vapor phase growth method is generally used. This selective epitaxial vapor phase growth involves reduction of SiC1m with hydrogen, s; H2c+2 or
A method such as thermal decomposition of iH4 is used.

However, in the above method, the selectivity is determined by the concentration of an impurity gas such as PH, or a gas containing a halogen element such as CI or Br. For example, when trying to form a device active region containing a high concentration of impurity elements, impurity! tl
The higher the lJ1 degree, the more part of it will adhere to the element isolation part,
Selectivity is reduced.

Further, a high temperature of 1000'C or more is required as the optimum growth temperature. Therefore, changes in impurity concentration caused by so-called auto-doping during growth, out-diffusion of impurities in the substrate, etc. become a major problem. In particular, when forming a high-speed bipolar device, the impurity concentration distribution in the depth direction and the junction depth largely control the device characteristics, so it is necessary to minimize changes in the impurity concentration distribution during the manufacturing process.

(Problems to be Solved by the Invention) In conventional selective epitaxial growth techniques, vapor phase growth is generally used, but as mentioned above, the optimum growth temperature is 10
A high temperature of 00° C. or higher is required, and there is a problem in that selectivity decreases when an epitaxial layer with a high impurity concentration is formed.

On the other hand, if solid phase growth is used, epitaxial growth is possible even at relatively low temperatures. When amorphous silicon is used, SOI growth (Si On I) is performed at approximately 600°C.
n5lator) is possible (J, o
f Appl, Phys, 54, 1983.2847
).

There is a strong market need for higher integration and higher speed of semiconductor devices, and therefore it is an important issue to further develop self-alignment technology and to establish a selective epitaxial growth method with a low optimum growth temperature.

An object of the present invention is to provide a semiconductor that can be applied to microscopic devices such as high-speed bipolar elements, and that can perform selective epitaxial growth of silicon at a relatively low temperature and at the same time form a metal silicide layer in contact with this epitaxially grown layer. An object of the present invention is to provide a method for manufacturing a device.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a silicon single crystal region exposed on the main surface of a substrate (including a Si substrate, an SOI substrate, etc.) containing six constituent elements.
A process of forming an amorphous film consisting of not less than 8ato1% (atomic percentage) of Sl and the remaining metal, and a heat treatment, which converts the amorphous film into crystalline metal silicide and at the same time prevents it from being used for silicidation. A method for manufacturing a semiconductor device, comprising a step of selectively epitaxially growing silicon on a surface of the silicon single crystal region.

(Function) The metal element M contained in the amorphous film is MSi. Ti, W which can form type metal silicide.

It must be a metal such as Mo, 'r''a, Co, N+, Fe, Or, etc. Silicide, which is a metal compound of the above metal and St, contains more Si than MSi type 2 metal silicide. And there is no thermodynamically stable metal silicide, so S i 68 ato1%
Above is the chemistry behind the remaining metal amorphous film! It contains theoretically excessive Si atoms.

depositing an amorphous film of the above constituent elements on the Si single crystal region,
When heat treatment is performed, crystalline metal silicide is generated, and at the same time, the excess S1 atoms that are not used for silicidation selectively grow epitaxially on the Si single crystal surface where crystal growth energy is low. The heat treatment temperature at this time is 900℃, although it varies depending on the type of metal silicide.
Relatively low temperatures below are sufficient.

If necessary, impurity ions to become N-type or P-type are implanted into the surface of the amorphous film, and the amorphous film is selectively etched away leaving the Sl'f' crystal region, followed by heat treatment. N type or P type with metal silicide electrode
A type selective epitaxial layer can be formed in a self-aligned manner, which is a desirable embodiment.

Also, the number of S1 atoms contained in the amorphous film is 68 aton%
If it is less, trial results show that a Si epitaxial layer of substantially usable thickness may not be obtained, which is inappropriate.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

The sectional view shown in FIG. 1 shows an embodiment for explaining the basic configuration of the present invention.

First, as shown in FIG. 2A, after forming an insulating film 2 (for example, Si 02 M >) covering the surface of a P-type Si substrate 1, an insulating film 2 (for example, Si 02 An opening with vertical side walls is provided to obtain an exposed surface 1a of the Si single crystal region.

Next, as shown in the same figure (b), 8 of 68 aton% or more
1 and the remaining metal as constituent elements, for example, Si
An amorphous film 3 containing Mo at 75 at.01% and Mo at 25 at.1% is formed by sputtering or the like. For the sputtering method, for example, S i 75atoI! %, M02
A hot press molded product of a mixture having a composition of 5ato11% was used for Targera 1-. Next, ion implantation 4 of an N-type impurity (for example, As) is performed into the surface of the amorphous film 3.

Next, as shown in FIG. 3(c), the amorphous film other than the area including the opening of the insulating film is etched away by the well-known tE method. Next, heat treatment is performed.

The conditions for this heat treatment vary depending on the type of metal silicide formed by the heat treatment, but a relatively low temperature of 900° C. or lower is sufficient. When the amorphous film is composed of Si and MO, heat treatment at 800° C. for about 190 minutes in a N2 atmosphere is appropriate.

This heat treatment turns the amorphous film into a crystalline MoSi2 film 6, but stoichiometrically there is an excess of 25ato11% of Sl which is not used to form the MoSi2 film 6.

This is because Mo silicide, which is thermodynamically stable and contains more Si than MoSi2 type metal silicide, does not exist, so it precipitates as crystalline Si, and especially in the area where single crystal S1 is exposed, single crystal Si is deposited due to the crystal growth energy difference. Crystal S1
epitaxially grown on top. The thickness of the epitaxial layer 5 at this time is approximately 7
There are 00 people.

Further, the N-type impurity ion-implanted into the surface of the amorphous film is
During the heat treatment, the epitaxial layer becomes N-type because it is distributed almost uniformly within the epitaxial layer, and a PN junction is formed between it and the P-type Si substrate 1.

FIG. 2 shows an example in which the present invention is applied to the emitter portion of a self-aligned bipolar transistor having a base electrode. A base region 12 is provided. A polycrystalline silicon layer 13 doped with P-type impurities is connected to this base region through an opening in an insulating film 14. The polycrystalline silicon layer 13 is a lead-out base electrode and is covered with an insulator [17].

The present invention is applied to forming the emitter region.

That is, the insulating film 17 is opened by dry etching to expose a part of the P type base region 12 of silicon single crystal.
Next, an amorphous film containing 75 aton% of Si and 25aton% of W is formed by sputtering.

Next, N-type impurity ions were implanted and the amorphous film other than the area including the opening was etched away, and then etched at 750°C.
Heat treatment is performed for about 120 minutes. With this heat treatment,
An epitaxial layer 15 containing N-type impurities and a tungsten silicide <W 3 i ) electrode 16 are formed. Note that reference numeral 18 indicates an insulating film, and reference numbers 19 and 20 indicate conductive films Jl!, which serve as base ti and emitter electrodes, respectively. (A.I.
).

The base and emitter are separated by an insulating film 17,
Since the epitaxial layer 15 is used as an emitter region, the base-emitter junction surface is substantially flat.

Further, the heat treatment conditions during epitaxial growth are as described above, and with this degree of heat treatment, the impurity distribution in the P type base region 12 hardly changes, so that a shallow base-collector junction, that is, a small base width can be maintained. In addition, since the emitter electrode is made of tungsten silicide, which has a lower resistance than conventionally used polycrystalline silicon (for example, about 1 geta), it is effective in reducing emitter resistance, which is extremely advantageous for increasing the speed of transistors. It is.

The above is an example in which the present invention is applied to a high-speed bipolar transistor, but the present invention is advantageous in that as long as there is a region where the single crystal S1 is exposed, it is possible to form a selective epitaxial layer that joins to metal silicide in a self-aligned manner. The range of applications is extremely wide.

For example, as shown in FIG. 3, a single-crystalline silicon layer 23 is provided on an insulating film 22 covering a silicon substrate 21 through an opening. By selectively opening the insulating film 24 deposited on the single crystal silicon layer 23, it is possible to easily form a device having a metal silicide electrode 26 and a selective epitaxial layer 25 on the exposed single crystal region.

Furthermore, by forming a metal silicide and an epitaxial layer in contact with the metal silicide through heat treatment, and then removing the metal silicide, the method can also be used to form an epitaxial layer conventionally used in bipolar transistors.

Furthermore, since the interface between the selective epitaxial layer and the metal silicide is also formed in a self-aligned manner, even when attempting to form a Schottky barrier diode using this interface, the Schottky barrier inherent to the interface between the metal silicide and Si Diodes with barrier height can be formed with good reproducibility.

The thickness of the selective epitaxial layer, which is a self-aligned layer, can be easily controlled by the composition and thickness of the amorphous film that is the starting material, and by using this as the device active region,
It is very advantageous not only for high integration of elements but also for high speed.

[Effects of the Invention] As explained above, by using the method for manufacturing a semiconductor device of the present invention, selective epitaxial growth of silicon can be performed at a low temperature of 900° C. or lower, and at the same time, it is also possible to form a metal silicide layer in contact with this epitaxial layer. becomes. Further, in the manufacturing method of the present invention, the selective epitaxial layer is formed in a self-aligned manner on the silicon single crystal region exposed on the main surface of the substrate, and the metal silicide layer is formed in contact with this selective epitaxial layer in a self-aligned manner. Therefore, by using the present invention, the miniaturization of elements can be further improved, and as the elements are miniaturized, the speed of the elements can be further increased.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process for explaining the basic structure of the manufacturing method of the present invention, FIG. 2 is a cross-sectional view of an embodiment of a semiconductor device to which the present invention is applied, and FIG. FIG. 3 is a cross-sectional view when applied to a single crystal silicon film on an insulating film. 1 11 21...Silicon substrate, 1a...Exposed surface of silicon single crystal region, 2,14.1718.22
．． 24... Insulating film, 3... Amorphous film, 5.15.
25...Selective epitaxial layer, 6゜1626...
・Metal silicide. (b) Figure 2 (C) Figure 3 Figure 1

Claims (1)

[Claims] 1. A step of forming an amorphous film consisting of silicon with a constituent element of 68 atom % or more and the remaining metal on a silicon single crystal region exposed on the substrate surface, and a heat treatment to convert the amorphous film into a crystalline film. A method for manufacturing a semiconductor device, comprising the step of selectively epitaxially growing silicon that is not used for silicide on the surface of the silicon single crystal region at the same time as converting it into metal silicide.