JPH02135318A - Active matrix type display device - Google Patents

Abstract

PURPOSE:To make a large-capacity display and a high-definition display by providing scan bus lines or data bus lines a half as many as display rows or display columns. CONSTITUTION:A 1st switching element Tn which turns on when a positive scan voltage is applied and a display electrode En which is driven by it, and a 2nd switching element Tp which turns on when a negative scan voltage is applied and a display electrode Ep which is driven by it are connected to each intersection of a scan but line SB and a data bus line DB. Further, two display cells Lcn and Lcp provided at a bus line intersection part are driven alternately with positive and negative scan voltages which are applied on a time-division basis to the scan bus line SB. Therefore, the number of the data bus lines can be reduced to a half as large as that of the display columns. Further, the number of the scan bus lines is reduced to a half as large as that of the display rows. Consequently, the large-capacity display and high-definition display are realized.

Description

[Detailed Description of the Invention] [Summary] Regarding an active matrix type display device using a facing matrix method, an object of the present invention is to reduce the number of bus lines of the facing matrix type active matrix to be smaller than the number of rows or columns of pixels. It has a pair of insulating substrates that face each other with a medium in between, one of which has a plurality of data bus lines arranged thereon that also serve as common electrodes constituting display cells, and the other substrate which is orthogonal to the data bus lines. A matrix type display in which a plurality of scan canvas lines and display electrodes constituting the display cells are connected to the intersections of the scan bus lines and data bus lines via switching elements for driving the cells. In the configuration, a first switching element that becomes conductive when a positive scanning voltage is applied to an intersection of each of the scan canvas lines orthogonal to a data bus line, and a first switching element that is driven thereby, and a negative scanning A second switching element that becomes conductive when a voltage is applied and the display electrode driven by the second switching element are connected, and the intersection of the bus lines is controlled by positive and negative scanning voltages that are applied to the scan bus lines in a time-division manner. The structure is such that two display cells provided in the section are driven alternately.

[Industrial application field]

The present invention relates to an active matrix display device of a facing matrix type in which bus lines for data input and scan lines for line addresses are separately provided on a pair of opposing glass substrates.

This type of active matrix type liquid crystal display device is used as a thin display device for information terminals, along with a simple matrix type liquid crystal display device, and liquid crystal is used as the display medium.

Comparing the characteristics of the two, when the display capacity increases with the increase in the number of lines, the simple matrix type lowers the driving duty ratio, resulting in a decrease in contrast and viewing angle, but the active matrix type has a large number of Since each pixel can be driven independently, there is an advantage that such a problem does not occur.

On the other hand, in order to address the problems of reduced manufacturing yield and increased costs caused by the complexity of the active matrix type structure, an opposed 7-trix method has been developed that eliminates the intersection of scan bus lines and data bus lines.

The present invention attempts to convert the driving circuit of such a facing matrix type active matrix liquid crystal display device into an hour wheel.

[Conventional technology]

FIG. 5 shows a conventional facing matrix type active matrix liquid crystal display device proposed in Japanese Patent Application No. 60-274011, in which (a) is an equivalent circuit diagram and (b) is an exploded perspective view.

As can be seen in FIGS. 12(a) and (b), the active matrix liquid crystal display device of the opposing matrix type has a display electrode E of a liquid crystal cell LC and its source on a first glass substrate 1. Thin film transistors (TPT) 2 with electrodes connected are arranged in a matrix, and a scan canvas line SB is provided corresponding to each row to commonly connect the gate electrodes of the TFTs arranged in the row direction. One side of the substrate formed in this manner is placed against a TPT substrate.

On the other hand, a second glass substrate 1'' placed opposite to this
On the top, data bus lines DB, which also serve as common electrodes facing the display electrodes E, are arranged corresponding to each column of the liquid crystal cells LC, and this substrate is referred to as a counter substrate P'. Then, a liquid crystal is sandwiched between the TPT substrate and the counter substrate P° to form a liquid crystal display panel.

Further, Ts in FIG. 5(b) is a terminal electrode of the scan canvas line SB, and Tc is a terminal electrode of a ground bus line (common bus line) that commonly connects the drain electrodes of each TPT to ground.

The scan bus line SB and the data bus line DB are formed so as to be orthogonal to each other, but since they are formed separately on the first and second glass substrates 1.1" which are arranged opposite to each other, a general-purpose TFTi board P like the conventional panel
There is no risk that these two bus lines will cross each other, improving manufacturing yield.

[Invention tries to solve! ! [8] The facing matrix type solves the manufacturing yield problem in this way, but unlike a beam-addressed display device such as a CRT, multiple It is necessary to provide a terminal electrode for each scan bus line SB and data bus line DB, and to connect each of these many terminal electrodes to an external drive circuit.

Since the terminal electrode is connected to a lead wire led out from the drive circuit, its width must be considerably larger than the width of the bus line. Furthermore, drive circuits are also required depending on the number of bus lines.

Therefore, there is a limit to increasing the capacity and high definition of the facing matrix type liquid crystal display device, and there is a problem that the cost becomes extremely high.

This problem arises from the fact that a scan bus line is required for each pixel row and a data bus line is required for each column.

Therefore, in view of the above-mentioned conventional situation, the present invention aims to reduce the number of bus lines in the opposing matrix type active matrix display 'Jrll to a number smaller than the number of rows or columns of pixels.
Therefore, it is an object of the present invention to provide a new matrix display device that can realize large capacity and low cost.

[Means to solve the problem]

The present invention has a pair of insulating substrates facing each other with a display medium in between, one of which has a plurality of data bus lines arranged thereon that also serve as common electrodes constituting a display cell, and the other substrate with which the data is stored. A plurality of scan canvas lines orthogonal to the bus line and a display electrode constituting the display cell connected to the intersection of the bus line and the data bus line via a switching element for driving the cell are arranged. In the matrix type display configuration, a first switching element that becomes conductive when a positive scanning voltage is applied to an intersection of each of the scan canvas lines orthogonal to a data bus line, and the display electrode that is driven by the first switching element; A second switching element that becomes conductive when a negative scanning voltage is applied and the display electrode driven by the second switching element are connected, and positive and negative scanning voltages are applied to the scan canvas lines in a time-division manner. Accordingly, the two display cells provided at the intersection of the bus lines are alternately driven.

[For production]

When the scanning voltage applied to one scan canvas line SB is positive, the first switching element Tn connected to this scan canvas line is turned on, so display data is transmitted to one display cell LCn via this element. When the scanning voltage is input and then changed to a negative voltage, the second switching element TP connected thereto is turned on, and display data is input to another display cell LCp through this element.

Therefore, the two display electrodes En and Ep driven by the two switching elements Tn and Tp with different properties are arranged adjacently in the extending direction of the same scan canvas line SH and face the common data bus line DB. In such a display device, the number of data bus lines can be reduced to 1/2 of the number of display digits.

In addition, in a display device in which the two display electrodes En and Ep are arranged on both sides of the same scan canvas line SB and faced the same data bus line DB, the number of scan canvas lines is reduced to 1/2 of the number of display lines. be able to.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

The layout diagram schematically showing the positional relationship of each part in FIG. 1 and the drive waveform diagram in FIG. 2 are explanatory diagrams of the first embodiment of the present invention.

As described above, in this embodiment, each scan bus line SB+
(1=1~N) and data bus line D B J (J
=1-M), two pixels are arranged at each intersection. Therefore, the gate electrode (
a pixel consisting of an N-type transistor Tn as a first element that becomes conductive when a positive voltage is applied to the control electrode) Gn, and a display electrode En connected to the source electrode Sn of the N-type transistor Tn;
A pixel consisting of a P-type transistor 'p as a second element that becomes conductive when a negative voltage is applied to the gate electrode cp and a display electrode EP connected to its source Sp is
A plurality of them are arranged alternately along the scan canvas line SB. The gate electrodes Gn and Gp of these transistors Tn and Tp are connected to the same scan line S B +
and connect the drain voltages JIDn and Dp to the same common bus line CBI. 2 adjacent in the above row direction
A plurality of data bus lines DB are arranged to commonly face the two display electrodes En and Ep.

The N-type and P-type transistors Tn and Tp are made of amorphous silicon (a-3i) or polycrystalline silicon (pol).
In the case of a P-type transistor Tp, the contact layer of the source/drain electrode is a semiconductor layer doped with a P-type impurity such as boron (B), and in the case of an N-type transistor T, n In the case of phosphorus (P)
The structure is an N-type semiconductor layer doped with an N-type impurity such as or arsenic (8S).

To realize such a structure, both types of transistors are formed by separately implanting ions of boron or arsenic into the semiconductor layer of the source and drain portions using a resist film or the like as a mask.

Next, the operation of this embodiment configured as described above is illustrated in FIG.
) to (d) will be explained using the drive waveforms.

Note that this operation is performed on the scan canvas line S B of the first line.
The following description will focus on the data bus line DBJ and the data bus line DBJ in the J-th column.

Scan canvas line SB, first +vA1 then -v
A positive and negative pulse-like scanning signal V311 having a peak value of A is applied (see FIG. 2(a)), and in synchronization with this, first +■o is applied to the data bus line DB.

Next, a positive and negative pulsed data voltage VDATA having a peak value of -vD is applied, and each common bus line CB
A reference voltage (Ov) is applied to + (see (b) in the same figure).

When positive (VA'') scanning signals ■ and 3 are applied, the N-type transistor Tn connected to the display electrode En turns on, and the liquid crystal cell LCn composed of the data bus line DB J and the display electrode En becomes data bus line DB,
voltage +VD and common bus line CB + voltage (Ov
) [liquid crystal cell voltage VLCM shown in (C) of the same figure].

Then, a negative (-VA) scanning signal V! When l is added, the P-type transistor Tp connected to the display type FiEp turns on, and the data bus line DBJ and the display electrode E
A liquid crystal cell LCp composed of data bus line D
B, voltage = VIl and common bus line CBl voltage (0
(2)) [liquid crystal cell voltage VLCP shown in (d) of the same figure].

The voltages written in the liquid crystal cells LCn, f, and Cp are held until the next scanning signal is applied, that is, for one frame. The driving of the liquid crystal cell is shown in (b) to (d) in the same figure.
As shown in the figure, the polarity of the data voltage is reversed every frame to perform AC driving.

As explained above (in the first embodiment, the data voltage for two pixels is supplied in a time-division manner and is applied to two adjacent pixel columns via one data bus line. Therefore, the number of data bus lines can be reduced to half the number of display digits.

In the first embodiment, an example was explained in which the polarity of the data voltage supplied in a time-division manner is reversed for each pixel, but the polarity may be the same, that is, within a certain frame, positive and negative scanning signals Correspondingly, V IIATA is both positive,
In the next frame, both VIIATAs can be negative.

It is also possible to make the address period using the same scan canvas line the same polarity, and to reverse the polarity each time the scan canvas line to be addressed changes.

Next, the second embodiment is shown in FIGS. 3 and 4 (a) to (d).
This is explained by:

This second embodiment is an example in which two pixels adjacent in the column direction can be selectively driven by one scan canvas line SB. In the TPT substrate, one N-type transistor and one P-type transistor Tn and one P-type transistor Tp are provided on both sides of the scan canvas line SB. These N type and P type
Source electrodes Sn and Sp of the type transistor are connected to display electrodes En and Ep, respectively, and drain electrodes Dn and Dp are connected to display electrodes En and Ep, respectively.
is a separate common bus line C provided in parallel between the scan canvas line and adjacent scan canvas lines on both sides of the relevant scan canvas line.
Connected to BNI and CB r +. The common bus lines CB N l and CBP+ each have a voltage of 10 V.
It can be connected to voltage sources with different polarities, such as -V, and controlled by different potentials.

Further, on the counter substrate, N-type and P-type transistors Tn are alternately arranged in the column direction.

A plurality of data bus lines DBJ are provided which commonly face the Tp-related display electrodes En and Ep.

In this case, two liquid crystal cells LCn and LCp are driven by N-type and P-type transistors Tn and Tp arranged adjacently on both sides of the scan canvas line SB.
The book can be scanned independently using the scan canvas lines SB, and therefore the number of scan canvas lines can be reduced to half the number of display lines.

The operation of the second embodiment configured in this way is shown in FIG. 4(a).
This will be explained using the drive waveforms in ~(d).

A positive and negative pulse-like scanning signal VSa similar to that of the first embodiment described above is applied to the scan line SB [see figure (a)], and in synchronization with this, the data hash life DB
J to +Vs+ +Vo, -Vm -V.

Positive and negative pulsed data voltages are applied, and a reference voltage (+v, ) is applied to the negative common bus line CB□.

A reference voltage (-■I) is applied to the other common bus line CBPI (see FIG. 3(b)).

Scanning signal v! When ll is +vA, the N-type transistor T
n is turned on, and the liquid crystal cell LCn composed of the display electrode En and the data bus line DB is at the voltage +Vm+V of the data bus line DB.

and the voltage of the common bus line CB Hl (liquid crystal cell voltage VLCN in FIG. 3(C)).

Scanning signal V! When II is -vA, the P-type transistor T
p is turned on, and the liquid crystal cell LCp constituted by the display electrode Ep and the data bus line DB has the voltages -V and -V of the data bus line DB.

and the voltage of the common bus line CB□=■ (liquid crystal cell voltage VLCF in FIG. 3(d)).

The voltages written in the liquid crystal cells LCn and LCp are held until the next scanning signal is applied, that is, for one frame, as in the first embodiment.

In this way, in the second embodiment, since two pixels adjacent in the row direction are sequentially scanned in a time-division manner using one scan canvas line, the number of scan canvas lines can be reduced to half the number of display lines. can.

Furthermore, in this second embodiment, the N-type and P-type transistors Tn and Tp are connected to separate common bus lines CB□ and CB□, respectively, so that different reference potentials are applied to both. The operating point of the type of transistor can be set to the operating point that matches the characteristics of each type,
It is also possible to improve drive characteristics such as drive margin.

Although the above two embodiments have been described with reference to liquid crystal display devices, the present invention is not limited to this, but can also be applied to EL display devices and the like.

[Effects of the invention]

As explained above, according to the present invention, in a facing matrix display device, the number of scan canvas lines or data bus lines can be reduced to half the number of display lines or display digits, which facilitates board manufacturing and mounting. , it is possible to achieve a large-capacity display and a high-definition display, which is a practically beneficial effect.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the configuration of the first embodiment of the present invention, and FIG. 2 (
a) to (d) are drive waveform diagrams of the first embodiment, FIG. 3 is a configuration explanatory diagram of the second embodiment of the present invention, and FIGS.
(d) is a drive waveform diagram of the second embodiment, and FIG. 5(a)
, (b) are explanatory diagrams of a conventional facing matrix type liquid crystal display device. In the figure, 1.1° indicates the first and second insulating substrates (glass substrates), and 2 indicates TPT. SB and SB are scan canvas lines DB and DI
3. are the data bus lines CB, CB+, CBN+, and CB ) Dn, D
p is the other controlled electrode (drain electrode) En, Ep is the display electrode LC, LC, and LCp is the liquid crystal cell. - Loquat Ichiryu 3's 4th bow) Momo Ku - Sun rjLn] 1st Figure ti2 Sc Figure 5 Chapter 5, Intersection of electrode-M Matsoksu PL-f9j4 display Pi 1-Whisino υ face No. 5 figure

Claims (3)

[Claims] (1) A pair of insulating substrates (1,
1'), on one substrate there are arranged a plurality of data bus lines (DB_J) which also serve as common electrodes constituting display cells, and on the other substrate there are arranged a plurality of data bus lines (DB_J) which are orthogonal to the data bus lines. A matrix type display configuration in which a scan bus line (SB_I) and a display electrode constituting the display cell connected to the intersection of the scan bus line (SB_I) and the data bus line through a switching element for driving the cell are arranged. , a first switching element (Tn
) and the display electrode (En) driven thereby, and a second switching element (Tp) that becomes conductive when a negative scanning voltage is applied and the display electrode (Ep) driven thereby. Therefore, the two display cells (LCn, LCp) provided at the intersection of the bus lines are alternately driven by positive and negative scanning voltages applied to the scan bus line (SB_I) in a time-division manner. Features an active matrix type display device. (2) A display electrode (En) connected to the first switching element (Tn) and one controlled electrode thereof, and a display electrode (En) connected to the second switching element (Tp) and one controlled electrode thereof The display electrodes (Ep) are arranged adjacent to each other in the extending direction of the same scan canvas line (SB_I), and both display electrodes (En, E
p) facing a common data bus line (DB_J),
In addition, the control electrodes of both switching elements (Tn, Tp) are commonly connected to the scan canvas line (SB_I), and the other controlled electrode thereof is connected to a reference potential parallel to the scan canvas line. 2. The active matrix display device according to claim 1, wherein the active matrix display device is connected to a common bus line (CB_I) for connection. (3) A display electrode (En) connected to the first switching element (Tn) and one controlled electrode thereof, and a display electrode (En) connected to the second switching element (Tp) and one controlled electrode thereof The display electrodes (Ep) are arranged adjacent to each other in the extending direction of the same data bus line (DB_J), and both switching elements (Tn, T
The control electrodes of p) are commonly connected to the data bus line (DB_J) in a sandwiching relationship from both sides thereof, and the other controlled electrodes are connected adjacently to both sides of the scan bus line (SB_I). A common bus line (CB_N_I,
2. The active matrix type display device according to claim 1, wherein the active matrix display device is connected to CB_P_J).