JPH02134867A - Miss type semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To easily improve the degree of integration and increase capacitance by effectively making use of a space above a source area of an LDD transistor by providing a groove-shaped capacitive electrode on the upper portion of a gate electrode of the LDD type MIS transistor through an insulating film. CONSTITUTION:In a MIS type semiconductor memory device having a memory cell including an LDD type MIS transistor provided on one principal surface of a first conductivity type semiconductor substrate 1 and a groove-shaped capacitor provided on a groove section formed on said one principal surface, a capacitive electrode 17 with said groove-shaped capacitor is provided extending above a gate electrode 6-1 of the LDD type MIS transistor through insulating films 13, 15. Hereby, the degree of integration of a memory cell can be raised by a fraction corresponding to a reduce occupation area of a source area 11-1 of the LDD type MOS transistor. Otherwise, the capacitance of the groove-shaped capacitor can be increased by providing a capacitive electrode 17 extending onto the gate electrode 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MIS type semiconductor memory device and a method for manufacturing the same, and more particularly to a semiconductor memory device having an LDD type MO3) transistor and a trench type capacitor and a method for manufacturing the same.

[Conventional technology]

FIG. 4 is a pattern layout diagram of a memory cell of an MO3 type semiconductor memory device for explaining a conventional example, and FIGS. 5 and 6 are lines A-A' and B-B' in FIG. 4, respectively. FIG. 3 is a cross-sectional view of the semiconductor chip cut at a corresponding portion. This M
In the O3 type semiconductor memory device, the source region of the LDD type MOS transistor is simply used as a source region, and the space above it is not used effectively. To form a type capacitance, a capacitance storage charge region 16, a capacitance electrode (first
After forming the polycrystalline silicon film 17), the gate ring &
6 is formed, and further a low concentration source/drain region 7 and a high concentration source/drain region 11 are formed to form an LDD structure MOS transistor.

[Problem that the invention seeks to solve]

The above-described conventional MIS type semiconductor memory device has the disadvantage that it is difficult to improve the degree of integration or increase the capacitance value because the space above the source region of the LDD type MO3 transistor of the Momeri cell is not effectively utilized.

In addition, in the conventional manufacturing method of MIS type semiconductor memory devices, in order to form an oxide film sidewall on the side surface of the gate electrode as a mask for forming high concentration source/drain regions by ion implantation, a CVD oxide film growth fetch-back method is used. At this time, current CVD
Because the uniformity of the oxide film is poor, some areas where the film is thin may damage the semiconductor substrate surface (low concentration source/drain regions). In particular, even minute damage to the source region connected to the capacitance storage charge region deteriorates the characteristics.

Furthermore, after forming the capacitor electrode, the gate electrode is formed by depositing and buttering a polycrystalline silicon film, for example, so that the insulating film 11 has an inverted tapered shape on the side surface of the capacitor electrode, as shown in the figure. Since the polycrystalline silicon film underneath is difficult to remove by etching, it is necessary to taper the sides of the capacitor electrode to prevent short-circuits between adjacent gate electrodes, or to remove short-circuit points between adjacent gate electrodes. There is a drawback that it is necessary to add a step of cutting again.

Means for Solving Problem C] The MIS type semiconductor memory device of the present invention includes an LDD type MIS transistor provided on the entire surface of a first conductivity type semiconductor substrate, and an LDD type MIS transistor provided in a groove portion dug from the first main surface. In a MIS type semiconductor memory device having a memory cell including a trench-type capacitor, a capacitor electrode of the trench-type capacitor is connected to the LDD.
It is provided extending above the gate electrode of the M type S transistor with an insulating film interposed therebetween.

Further, the method for manufacturing a tIS type semiconductor memory device of the present invention includes forming a first conductive film and a first conductive film on a first conductive type semiconductor substrate in which a gate insulating film is formed on the surface of an element formation region partitioned by a field insulating film. A step of depositing a two-layer film made of an insulating film and then patterning it into a predetermined shape to form a gate electrode;
A process of performing ion implantation using the two-layer film as a mask to form low concentration source/drain regions, and after depositing a second insulating film, the second insulating film is removed from the two-layer film by anisotropic etching. a step of removing the field insulating film except for side portions; a step of performing ion implantation using the field insulating film, the two-layer film, and the second insulating film as a mask to form high concentration source/drain regions; the field insulating film; Said 2
The method includes a step of forming a groove-type capacitor by forming a groove using an etching mask including a layered film and the second insulating film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the MIS type semiconductor memory device of the present invention.

This embodiment includes a memory cell including an LDD type MO3) transistor provided on the surface of a p-type semiconductor substrate 1 made of silicon, and a trench type capacitor provided in a trench dug from the surface. In the MIS type semiconductor memory device, the polycrystalline silicon film 17, which is the capacitor electrode of the trench type capacitance described above, is placed above the gate electrode 6-1 of the LDD type MIS transistor with an insulating film (13, 14) interposed therebetween. It is said that it is located in an extended manner.

Compared to FIG. 5, the degree of integration of the memory cell can be increased by reducing the area occupied by the source region (11-1) of the LDD type MOS transistor. Alternatively, in FIG. 5, by extending the capacitor electrode 17) above the gate electrode 6, the capacitance value of the trench type capacitor can be increased.

2(a) to 2(g) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the method for manufacturing an MIS type semiconductor memory device of the present invention, and FIG. 3 is a diagram showing the formation of a capacitive storage charge region. FIG. 3 is a plan layout diagram after a process of forming grooves for the purpose of forming the grooves.

First, as shown in FIG. 2(a), a field oxide film 2
A first conductive film shown as a polycrystalline silicon film 4 and a first silicon oxide film 5 are sequentially deposited on a p-type semiconductor (Si) substrate 1 on which a gate oxide film 3 is formed on the surface of an element formation region divided by . A two-layer film is formed by depositing using the CVD method.

Next, as shown in FIG. 2(b), a polycrystalline silicon film 4
A gate electrode 6 is formed by patterning a two-layer film made of first silicon oxide M5 into a predetermined pattern. Next, after implanting n-type impurity ions and performing heat treatment to form low concentration source/drain regions 7-1.7-2.7-3, a second silicon oxide film 8 is deposited by CVD. do.

Next, as shown in FIG. 2(c), the second silicon oxide IL 18 is etched back by anisotropic etching until the surface of the semiconductor substrate in the low concentration source/drain region is exposed, and the side surface of the gate electrode is etched back. An insulating sidewall made of a second silicon oxide film is formed. Next, the surface of the semiconductor substrate damaged by etchback is lightly anisotropically etched to remove about 20 to 50 nm.
A thin silicon oxide film 9 having a thickness of 20 to 30 nm is formed by light thermal oxidation. Next, an n-type impurity is implanted from above the thin silicon oxide film 9, and a high concentration source is implanted in a self-aligned manner.
Drain regions 11-1, 1.1-2 and 11-3 are formed.

Next, as shown in No. 21"J(d), a photoresist mask is formed on the surface of the semiconductor substrate other than the groove-type capacitance formation portion, and after etching and removing the thin oxide film 9 on the surface of the semiconductor substrate, a field oxide film is removed. Anisotropic silicon etching is performed using the silicon oxide film 13 on the surface of the electrode 2 and the gate I electrode as a mask to form a vortex 14 with a depth of 4 to 6 .mu.m.

Next, as shown in FIG. 2(e), a photoresist mask 1 is
2, a capacitive insulating film 15 is formed, and then an n-type impurity region is formed as a capacitive storage charge region 16 on the inner wall of the trench. Next, a conductive film that will become a capacitor electrode, for example, a first polycrystalline silicon film 17 doped with n-type impurities, is deposited. Next, the surface of the first polycrystalline silicon film 17 is oxidized to form a silicon oxide film 183, and then one second polycrystalline silicon film is deposited to fill the trench. If necessary, a third polycrystalline silicon film 20 is further formed. The purpose of dividing the process into two is to ensure that the grooves are filled.

Next, as shown in FIG. 2(f), the second polycrystalline silicon film 18 is exposed until the silicon oxide film 18 on the surface of the first polycrystalline silicon film is exposed. The third polycrystalline silicon film is etched back by anisotropic dry etching.

Next, as shown in FIG. 2(g), the first polycrystalline silicon film 17 and the silicon oxide film 18 thereon are patterned into a predetermined pattern to form trench-type capacitors 21-1 and 21-2. end.

After that, as shown in FIG. 1, the interlayer insulating film 22 is formed by a known method.
Then, an upper wiring 23 and a cover film 24 are formed to form an MO3 type semiconductor memory device.

Since the capacitor electrode is provided after the gate electrode is formed, there is no need for a special process for preventing short circuits between adjacent gate electrodes as in the conventional method, and the degree of integration or capacitance value can be increased.

Furthermore, since the damaged layer on the surface of the semiconductor substrate is removed by etching after the etch-back process for forming the insulating sidewalls on the side surfaces of the gate electrode, the characteristics of the LDD type MO3) transistor are improved.

〔Effect of the invention〕

As explained above, the MTS type semiconductor memory device of the present invention has the following features:
Since the capacitor electrode is provided extending above the electrode through an insulating film, it is possible to effectively utilize the space above the source region of the LDD transistor or to reduce the occupied area, thereby increasing the capacitance value or This has the effect of realizing a highly integrated structure.

Further, the method for manufacturing the MIS type semiconductor memory device of the present invention includes:
Since the capacitor electrode is provided after the gate electrode is formed, there is no need for a special process to prevent short circuits between adjacent gate electrodes.
This has the effect of simplifying the process.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor chip showing an embodiment of the MIS type semiconductor memory device of the present invention, and FIGS. 2(a) to (g) illustrate an embodiment of the method for manufacturing the MIS type semiconductor memory device of the present invention. 3 is a plan layout diagram after the step of forming a groove, and FIG. 4 is a pattern of a memory cell of a MOS type semiconductor memory device to explain a conventional example.・Layout diagram, Figures 5 and 6
The figures are cross-sectional views of the semiconductor chip taken along lines A-A' and B-B' in FIG. 4, respectively. 1...p-type semiconductor substrate, 2...field oxide film,
3... Gate oxide film, 4... Polycrystalline silicon film, 5
...first silicon oxide film, 6.6-1.6-2...
- Gate electrode, 7.7-1.7-2.7-3...Low concentration source/drain region, 8...Second silicon oxide film, 9...Thin oxide film, 11.11- 1,112.1
1-2.11-3...High concentration source/drain region 1
2... Photoresist mask, 13... 14.11-1.14-2... Groove, 15... Capacitive insulating film, 16... Capacitive storage charge region, 17... First polycrystalline silicon film, 18... Silicon oxide film , 19・
...Second polycrystalline silicon film, 20...Third polycrystalline silicon film, 21-1.21-2...Trench type capacitor, 22
...Interlayer insulating film, 23... Upper wiring, 24... Cover film.

Claims (2)

[Claims] (1) L provided on one main surface of the first conductivity type semiconductor substrate
In an MIS type semiconductor memory device having a memory cell including a DD type MIS transistor and a trench type capacitor provided in a trench portion dug from the one main surface, a capacitor electrode of the trench type capacitor is connected to the LDD. A MIS type semiconductor memory device, characterized in that the MIS type semiconductor memory device is provided extending above a gate electrode of a type MIS transistor with an insulating film interposed therebetween. (2) A two-layer film consisting of a first conductive film and a first insulating film was deposited on a first conductive type semiconductor substrate in which a gate insulating film was formed on the surface of an element formation region divided by a field insulating film. Thereafter, a step of patterning into a predetermined shape to form a gate electrode, a step of performing ion implantation using the two-layer film as a mask to form a low concentration source/drain region, and a second step.
a step of removing the second insulating film by anisotropic etching after depositing an insulating film except for side surfaces of the two-layer film; A process of performing ion implantation using the film as a mask to form highly concentrated source/drain regions, and forming a groove using an etching mask including the field insulating film, the two-layer film, and the second insulating film. 1. A method for manufacturing an MIS type semiconductor memory device, comprising the step of forming a type capacitor.