JP2913809B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS type semiconductor device, and
Related to the method of manufacturing M.

[Conventional technology]

Conventionally, as a structure of a dynamic RAM memory cell,
For example, a device using a stacked capacitor type cell is known. At this time, it is important to increase the capacity of the cell by increasing the area of the capacitor electrode in the portion to be the lower electrode, and to secure a sufficient amount of accumulated charge. A method of increasing the area was used.

However, the method of manufacturing the above-mentioned conventional stacked capacitor type cell is as shown in FIG.

That is, as shown in FIG. 3A, for example, a field oxide film is formed on a P-type silicon substrate 1 by a normal LOCOS method.
2 and a gate oxide film 3 are formed at 600 nm and 30 nm, respectively, and polycrystalline silicon is laminated at 400 nm, and then patterned to form a gate electrode 4. Thereafter, impurities of the opposite conductivity type to the substrate 1 are applied to the gate electrode 4. Self-aligned, for example, 70 ke of As
V, 1.0 × 10 ¹⁶ cm ⁻² ions are implanted to form a diffusion layer 6
To form Thereafter, as shown in FIG. 3B, for example, a 200 nm thick CVD silicon oxide film 7 is laminated as an interlayer insulating film. Thereafter, as shown in FIG. 3 (c), using the photoresist 8 as a mask, the CVD silicon oxide film 7 and the gate oxide film 3 in the portion where the contact hole in the source region of the cell is formed are removed by etching. Thereafter, as shown in FIG. 3D, a first conductive film, for example,
Then, a portion which is electrically connected to the source region and serves as a lower electrode of the capacitor portion is masked with the photoresist 11. Thereafter, as shown in FIG. 3E, the polysilicon 12 is removed by etching using the photoresist 11 as a mask, and then a capacitor insulating film 13 is formed on the polysilicon. Thereafter, as shown in FIG. 3 (f), a method is adopted in which a polycrystalline silicon layer 14 is deposited to a thickness of 150 nm, and then a portion other than a portion serving as an upper electrode is removed by etching to form a capacitor.

[Problems to be solved by the invention]

However, in this conventional method of manufacturing the electrode portion of the stacked capacitor type cell, as shown in FIG. 3 (d), the polycrystalline silicon film is thickened, the side area of the capacitor lower electrode is increased, and the capacitance is increased. Therefore, unless etching is performed for an extremely long time to remove the polycrystalline silicon 12 deposited thicker than the normal portion in the narrow portion of the gate electrode 4, the polycrystalline silicon 12 remains and a short circuit between the lower electrodes occurs. The disadvantage is that the CVD silicon oxide film 7 on the gate electrode 4 is exposed to the etching for a long time, so that the film quality deteriorates.

[Means for solving the problem]

According to the method of manufacturing a capacitor portion of a stacked capacitor type cell of the present invention, after forming a contact hole connecting a capacitor lower electrode and a diffusion layer, a thin first conductor film is formed, and a thick insulating film is formed thereon. The first thin conductive film serves as an etching stopper by forming and removing the thick insulating film at the portion where the capacitor lower electrode is to be formed, and the etching time of the thick insulating film is reduced. Even if it becomes longer, damage to the interlayer insulating film and the field oxide film on the gate electrode and the film are not reduced, and the second conductive film is formed on the first conductive film by removing the thick insulating film by etching. The first conductive film is etched by a method of burying the body film and then removing the thick insulating film on the first conductive film by etching using the second conductive film as a mask. The interlayer insulating film on the gate electrode and the field oxide film on the gate electrode do not decrease in film thickness, and the thinner first conductor film may be etched even in the narrow portion of the gate polysilicon interval. The feature is that a lower electrode having a large thickness can be formed.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (h) are longitudinal sectional views showing a first embodiment of the present invention.

As shown in FIG. 1A, for example, a field oxide film 2 and a gate oxide film 3 are formed on a P-type silicon substrate 1 by a normal LOCOS method at 600 nm and 30 nm respectively, and then polycrystalline silicon is laminated to 400 nm. And a CVD silicon oxide film 5
After laminating 150 nm, a gate electrode 4 is formed by patterning, and then an impurity of the opposite conductivity type to the substrate 1 is self-aligned with the gate electrode, for example, As is 70 keV, 1.0 × 10 ¹⁶ cm ^−2.
The diffusion layer 6 is formed by ion implantation.

Thereafter, as shown in FIG. 1B, a 200 nm thick CVD silicon oxide film 7 serving as a first insulating film is laminated.

Thereafter, as shown in FIG. 1 (c), using the photoresist 8 as a mask, the CVD silicon oxide film and the gate oxide film at the portion where the contact hole is to be formed in the source region of the cell are removed by anisotropic etching. At this time, the CVD silicon oxide film 5 remains on the gate electrode 4 and, as is well known, a side wall film on the side wall of the gate electrode 4.
The CVD silicon oxide film 7 remains.

Next, as shown in FIG. 1D, after removing the photoresist 8, a polycrystalline silicon layer 9 containing an n-type impurity, which is a first conductive film, is grown to a thickness of 100 nm. Then, a PSG film 10, which is a second insulating film, is deposited to a thickness of 800 nm, reflowed by heat treatment, and the surface is planarized. After the etching removal, the photoresist is removed.

Thereafter, as shown in FIG. 1 (e), a thick polycrystalline silicon 12, which is a second conductive film, is grown to a thickness of 1 μm and an n-type impurity such as phosphorus is diffused.

Thereafter, as shown in FIG. 1 (f), the polycrystalline silicon 12 is removed by etching until the surface of the PSG film 10 is completely exposed.

Thereafter, as shown in FIG. 1 (g), after the PSG film 10 is removed by etching, the polycrystalline silicon 9 is removed by etching, and then the capacitor insulating film 13 is formed by oxidizing the surface of the polycrystalline silicon 12, for example. I do.

Thereafter, as shown in FIG. 1 (h), after polycrystalline silicon 14, which is a third conductive film, is laminated to a thickness of 150 nm,
By patterning, a capacitor upper electrode is formed, thereby forming a capacitor.

In the present embodiment, the first conductive film (polycrystalline silicon 9) and the second conductive film (polycrystalline silicon 12) are made of the same material, but are formed of silicide and polycrystalline silicon. Different materials may be used as described above.

FIGS. 2A to 2G are longitudinal sectional views showing a second embodiment of the present invention.

As shown in FIG. 2A, for example, after a field oxide film 2 and a gate oxide film 3 are formed on a P-type silicon substrate 1 by a normal LOCOS method at 600 nm and 30 nm respectively, polycrystalline silicon is laminated to 400 nm. And a CVD silicon oxide film 5
A gate electrode 4 is formed by laminating and patterning 150 nm, and then an impurity of a conductivity type opposite to that of the substrate 1 is added to the gate electrode 4.
50 keV, 1.0 × 10 ¹³ cm
^The diffusion layer 6 is formed by ^{performing -2} ion implantation.

Thereafter, as shown in FIG. 2 (b), a CVD silicon oxide film 7, which is a first insulating film, is laminated to a thickness of 200 nm, and the cell portion is covered with a photoresist 8.

Thereafter, as shown in FIG. 2C, a side wall is formed by anisotropically etching the CVD silicon oxide film 7 in the peripheral transistor portion.
0 ¹⁶ cm ^-2 well-known LDD by ion implantation
A transistor is formed.

Thereafter, as shown in FIG.
Using the mask 11 as a mask, a portion of the source region of the cell where a contact hole is to be formed, the CVD silicon oxide film 7 and the gate oxide film 3
Is removed by anisotropic etching to form a sidewall made of the CVD silicon oxide film 7.

Next, as shown in FIG. 2 (e), after removing the photoresist 11, a polycrystalline silicon layer 9, which is a first conductive film, is grown to a thickness of 50 nm.
After n-type implantation by implantation of × 10 ¹⁴ cm ^−2, a PSG film 10 serving as a second insulating film is grown to 800 nm, and the photoresist 15 is reflected without reflecting the shape of the base without reflowing.
In the portion of the capacitor other than the lower electrode, and the PSG film 10
Is removed by anisotropic etching.

Thereafter, as shown in FIG.
After removing 15, selective growth of selective polysilicon 16 containing an n-type impurity, which is the second conductor film, is performed to about 800 nm until the hole formed by PSG film 10 is filled.

Thereafter, as shown in FIG. 2 (g), the PSG film 10 is removed by etching.

Thereafter, a memory cell is formed in the same manner as in the steps from FIG. 1 (g) in the first embodiment of the present invention.

〔The invention's effect〕

As described above, according to the present invention, after forming a contact hole connecting a capacitance lower electrode and a diffusion layer, a thin first conductor film is formed, and a thick second insulating film is formed thereon.
By adopting a method of etching and removing the second insulating film in the portion where the capacitor lower electrode is formed, even if the etching time of the second insulating film is long, the interlayer insulating film on the gate electrode and the field oxide film can be removed. Damage or film reduction does not occur because the first conductor film serves as an etching stopper, and a second conductor film is formed on a portion of the first conductor film where the second insulating film is removed by etching. The first conductive film serves as an etching stopper by burying and then removing the second insulating film on the first conductive film by etching using the second conductive film as a mask. The interlayer insulating film and the field oxide film on the electrode are not reduced in film thickness, and the thinner first conductor film may be etched even in the narrow portion of the gate polysilicon interval. It has become possible to formed.

[Brief description of the drawings]

1A to 1H are longitudinal sectional views of a first embodiment of the present invention, and FIGS. 2A to 2G are longitudinal sectional views of a second embodiment of the present invention. 1A to 1F are longitudinal sectional views showing a conventional manufacturing method. 1 ... P-type silicon substrate, 2 ... Field oxide film, 3
…… gate oxide film, 4… gate electrode, 5,7… CVD silicon oxide film, 6… diffusion layer, 8,11,15 …… photoresist, 9,12,14 …… polycrystalline silicon, 10 …… PSG film, 13 ……
Capacitance insulating film, 16 ... Select poly.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification symbol FI H01L 21/822 H01L 21/88 K 21/8242 27/04 (58) Fields investigated (Int.Cl. ⁶ , DB name) H01L 21/8242 H01L 21/822 H01L 27/04 H01L 27/108 H01L 21/768 H01L 21/28

Claims (2)

(57) [Claims] In a method of manufacturing a semiconductor memory device including a capacitor serving as an information storage section and an insulated gate field effect transistor, a step of forming an impurity diffusion layer of a reverse conductivity type with a substrate in a self-aligned manner with respect to a gate electrode. Forming a contact hole for electrically connecting the capacitor lower electrode and the diffusion layer after laminating the first insulating film; and electrically connecting to the diffusion layer via the contact hole. Forming a first conductive film, forming the first insulating film and a second insulating film thicker than the first conductive film, and forming a capacitor lower electrode. Etching the second insulating film in a region and embedding a second conductive film electrically connected to the first conductive film in a portion where the second insulating film is etched away And the second
Removing the insulating film by etching, removing the first conductive film in a portion other than forming the capacitor lower electrode by etching, forming a capacitive insulating film, and removing the third conductive film. Forming a capacitor upper electrode by forming and patterning the capacitor upper electrode. 2. The method according to claim 1, wherein said second insulating film is a PSG film.