JPH02133956A - Nonfusible memory device - Google Patents
Nonfusible memory deviceInfo
- Publication number
- JPH02133956A JPH02133956A JP63287926A JP28792688A JPH02133956A JP H02133956 A JPH02133956 A JP H02133956A JP 63287926 A JP63287926 A JP 63287926A JP 28792688 A JP28792688 A JP 28792688A JP H02133956 A JPH02133956 A JP H02133956A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous
- metal wiring
- film
- wiring parts
- nonfusible
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005275 alloying Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は非溶断半導体記憶装置の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a non-fusing semiconductor memory device.
従来、非溶断半導体記憶装置としては、第1の金属電極
配線上にアモルファスSi膜を形成し、該アモルファス
Si膜を挟んで更にその上に第2の金属配線を形成する
積層構造の非溶断半導体記憶装置があった。Conventionally, non-fusible semiconductor memory devices have a laminated structure in which an amorphous Si film is formed on a first metal electrode wiring, and a second metal wiring is further formed on top of the amorphous Si film with the amorphous Si film sandwiched therebetween. There was a storage device.
しかし、上記従来技術によるとアモルファスSi膜が予
じめ金属配線と合金し、初期にオフ状態であるべきとこ
ろがオン状態となってしまうと云う課題があった。However, according to the above-mentioned conventional technology, there is a problem in that the amorphous Si film is alloyed with the metal wiring in advance, and what should initially be an off state becomes an on state.
本発明は、かかる従来技術の課題を解決し、高い歩留り
の得られる非溶断半導体記憶装置構造を提供する事を目
的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art and provide a non-fuseable semiconductor memory device structure that can achieve high yield.
上記課題を解決するために、本発明は、非溶断記憶装置
に関し、金属電極配線間にアモルファスSi膜を形成す
る手段をとる。In order to solve the above-mentioned problems, the present invention relates to a non-fuseable memory device, and takes means to form an amorphous Si film between metal electrode wirings.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第1図は本発明の一実施例を示す非溶断半導体記憶装置
の要部の断面図である。すなわち半導体装置が形成され
ているSt基板1の表面には、Sin、膜を介してAg
等から成る金属配線3.3′が形成され、該金属配線3
.3′の0.1μm程度のギャップ間にアモルファスS
i4がプラズマCVD法等により形成されて成る。アモ
ルファスSi4は金属配線3.3′のギャップ間に最少
限あれば良く、本例図の如く、金属配線3.3′表面に
迄アモルファスS14が延在して形成しても良く、又、
アモルファスS14の膜を金属配線3.3′の表面を含
む全面に形成しても良い。FIG. 1 is a sectional view of a main part of a non-fuseable semiconductor memory device showing one embodiment of the present invention. That is, the surface of the St substrate 1 on which the semiconductor device is formed is coated with Sin and Ag via the film.
A metal wiring 3.3' is formed, and the metal wiring 3.
.. Amorphous S is placed between the gap of about 0.1 μm at 3′.
i4 is formed by plasma CVD method or the like. The minimum amount of amorphous Si4 is required between the gaps between the metal wirings 3.3', and the amorphous S14 may be formed extending to the surface of the metal wirings 3.3', as shown in this example figure.
The amorphous S14 film may be formed over the entire surface including the surface of the metal wiring 3.3'.
アモルファスS14の膜を全面に形成しても良い理由は
、非溶断記憶部は金属配線3.3′のギャップ間隙で定
められるのであり、Sin、膜2上の他の金属配線との
間隙が前記例を引例とすると、0.1μmの記憶部ギャ
ップに対し、0.3μm以上あれば充分、アモルファス
Siは絶縁体としての作用のみ持つ事になるからである
。尚金属配線3.3′の材質はAfIに限定される事は
なく、WET i N5Cu、及びDoped Po
1ySi等であっても良く、又、異種金属の組み合わせ
であっても良く、又、多層膜構造や、記憶部へのバソヤ
・メタル形成等の構造を取っても良い事は云うまでもな
い。The reason why the film of amorphous S14 may be formed over the entire surface is that the non-fuse memory area is determined by the gap between the metal wirings 3 and 3', and the gap between the film and other metal wirings on the film 2 is To use an example as a reference, for a storage gap of 0.1 μm, a gap of 0.3 μm or more is sufficient, since amorphous Si only functions as an insulator. The material of the metal wiring 3.3' is not limited to AfI, and may be WET i N5Cu or Doped Po
Needless to say, it may be made of 1ySi or the like, or may be a combination of different metals, or may have a multilayer structure or a structure in which a bathoya metal is formed in the storage portion.
第2図は本発明の他の実施例を示す非溶断記憶装置の要
部の平面図である。すなわち、金属配線13.13′の
ギャップ部は、少くともいずれか一方の金属配線に凸部
を設けて、つき合わせ、該ギャップを埋める形で、表面
に、アモルファス5i14の膜を形成したもので、ギャ
ップ部での放電を確実に行なわせる目的で電極に凸部を
形成したものである。FIG. 2 is a plan view of essential parts of a non-fuseable storage device showing another embodiment of the present invention. In other words, the gap between the metal wirings 13 and 13' is formed by providing a convex portion on at least one of the metal wirings, bringing them together, and forming an amorphous 5i14 film on the surface to fill the gap. , a convex portion is formed on the electrode for the purpose of ensuring discharge in the gap portion.
第3図は本発明のその他の実施例を示す非溶断記憶装置
の要部の平面図である。すなわち、金属配線23.23
′のギャップ部を並行して形成し、該ギャップ部表面に
、ギャップを埋める形でアモルファスS i 24を形
成したもので、非溶断記憶部であるギャップ部の長さを
長くして、電圧印加時に熔アモルファスSiが融解する
確率を多くして、確実なオン状態を実現する目的で本構
造を形成したものである。FIG. 3 is a plan view of essential parts of a non-fuseable storage device showing another embodiment of the present invention. That is, metal wiring 23.23
' gap parts are formed in parallel, and amorphous Si 24 is formed on the surface of the gap part to fill the gap.The length of the gap part, which is a non-fusing memory part, is lengthened and voltage is applied. This structure was formed in order to increase the probability that the molten amorphous Si melts, thereby realizing a reliable on state.
本発明により、アモルファスSiから成る非溶断記憶部
が金属配線後に形成することができ、余分な加熱処理に
よる非溶断部の書き込み前の合金化や熔融によるオン状
態の現出はなくなり、非溶断半導体記憶装置の歩留り向
上を計る事ができる効果がある。According to the present invention, a non-fusible memory region made of amorphous Si can be formed after metal wiring, and the occurrence of an on state due to alloying or melting of the non-fusible region before writing due to extra heat treatment is eliminated, and the non-fusible memory region is formed after metal wiring. This has the effect of increasing the yield of storage devices.
第1図は本発明の一実施例を示す非溶断半導体記憶装置
の要部の断面図。第2図及び第3図は、本発明の他の実
施例を示す非溶断半導体記憶装置の要部レイアウト平面
図。
第1図
1 ・ ・ −・ ・ ・ ・
2 ・ ・ ・ ・ ・ ・ ・
3.3’ 、13.
4.14.24・
・Si基板
・Sin、膜
1B’、23.23′
・金属配線
壷アモルファスSi
以
上
第2図
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉(他1名)第3図FIG. 1 is a sectional view of a main part of a non-fuseable semiconductor memory device showing an embodiment of the present invention. FIGS. 2 and 3 are layout plan views of main parts of a non-fuse semiconductor memory device showing another embodiment of the present invention. Figure 1 1 ・ ・ −・ ・ ・ ・ 2 ・ ・ ・ ・ ・ ・ 3.3', 13. 4.14.24 - Si substrate/Sin, film 1B', 23.23' - Metal wiring pot amorphous Si Above Figure 2 Applicant Seiko Epson Co., Ltd. Agent Patent attorney Masayoshi Kamiyanagi (and 1 other person) No. Figure 3
Claims (1)
る事を特徴とする非溶断記憶装置。A non-fusing memory device characterized by forming an amorphous S_i film between metal electrode wirings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63287926A JPH02133956A (en) | 1988-11-15 | 1988-11-15 | Nonfusible memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63287926A JPH02133956A (en) | 1988-11-15 | 1988-11-15 | Nonfusible memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02133956A true JPH02133956A (en) | 1990-05-23 |
Family
ID=17723517
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63287926A Pending JPH02133956A (en) | 1988-11-15 | 1988-11-15 | Nonfusible memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02133956A (en) |
-
1988
- 1988-11-15 JP JP63287926A patent/JPH02133956A/en active Pending
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