JPH02133927A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02133927A
JPH02133927A JP28912288A JP28912288A JPH02133927A JP H02133927 A JPH02133927 A JP H02133927A JP 28912288 A JP28912288 A JP 28912288A JP 28912288 A JP28912288 A JP 28912288A JP H02133927 A JPH02133927 A JP H02133927A
Authority
JP
Japan
Prior art keywords
photoresist
opening
substrate
forming
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28912288A
Other languages
Japanese (ja)
Inventor
Haruo Nakano
晴夫 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP28912288A priority Critical patent/JPH02133927A/en
Publication of JPH02133927A publication Critical patent/JPH02133927A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain an electrode whose width is narrower by a method wherein a first photoresist is formed on a substrate, a second photoresist is formed thereon, a first opening is formed in the second photoresist, the first photoresist is etched from the opening, a second taper-shaped opening which is widened with a distance from the substrate is formed and a metal film is formed on the substrate from the opening. CONSTITUTION:A first photoresist 2 is formed on a substrate 1; a second photoresist 3 is formed on the first photoresist 2. A first opening 4 is formed in the second photoresist 3 by using a deep UV light source. Then, the first photoresist 2 is etched by an ion beam using an Ar ion from a direction nearly perpendicular to the first photoresist 2 by making use of the second photoresist 3 as a mask; a second taper-shaped opening 5 is formed; thereby, a width, on the side of the substrate, of this hole becomes shorter than a width of the first hole 4. Then, the substrate 1 is wet-etched from the first opening 4; a recess part 6 is formed; in succession, a gate metal film 7 of Al or the like is deposited by evaporation by making use of the first photoresist 2 and the second photoresist 3 as a mask; a gate electrode 8 is formed by a lift-off method.

Description

【発明の詳細な説明】 fイン 産業上の利用分野 本発明は、半導体装置の製造方法に関し、特に微細な線
幅の電極や配Ml形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming electrodes and wiring lines with fine line widths.

(ロ)従来の技術 半導体装置の電極や配線全選択的に形成する方法として
、リフトオフがある□これは基板上にフォトレジスト全
塗布し、該フォトレジスト全選択的に露光し、現像して
フォトレジストを開孔シ、その上から電極材料全蒸着さ
せ、フォトレジストとフォトレジスト上の電極材料を除
去することで一フォトレジストの開孔部分のみで基板上
に電極全形成するものである。
(b) Conventional technology Lift-off is a method for selectively forming electrodes and wiring in semiconductor devices. This method involves coating the entire surface of a substrate with a photoresist, selectively exposing the entire photoresist to light, developing it, and photoresist. By opening a resist, completely depositing an electrode material thereon, and removing the photoresist and the electrode material on the photoresist, the entire electrode is formed on the substrate using only the opening of one photoresist.

一般にフォトレジストの選択的な露光はマスクを用いて
行われる。紫外線あるいは、遠紫外線による露光で開孔
されたフォトレジストをマスクとして用いて形成し九電
極の実現可能な最小線幅は0.5μm程度である。こn
以下の線@?得る手段としては、X線による露光、エキ
シマレーザによる露光、あるいはマスクを用いずにフォ
トレジストt−電子ビームで直接描画するものがある。
Generally, selective exposure of photoresist is performed using a mask. The minimum line width that can be realized by forming nine electrodes using a photoresist with holes opened by exposure to ultraviolet rays or deep ultraviolet rays as a mask is about 0.5 μm. This
The line below @? Examples of methods for obtaining the photoresist include exposure to X-rays, exposure to an excimer laser, or direct writing with a photoresist t-electron beam without using a mask.

しかし、X線露光の場合、X1m露光用マスクの製作が
難しく、多くの工程全必要とし製作コストが高く。
However, in the case of X-ray exposure, it is difficult to manufacture a mask for X1m exposure, and many steps are required, resulting in high manufacturing costs.

エキシマレーザ露光の場合、露光源が帰野命である等、
露光装置が確立していない。また、電子ビ−ムで直接描
画する場合は、描画時間が非常に長くなるので、製造能
率が極端に悪く量産には不向きであるといった欠点?有
している。これらの技術は5olid 5tate t
8chnology/日X版/August 1986
 P52〜59r高JGaAS  FETのtめのマイ
クロリソグラフィ技術」に詳しい0電界効果型トランジ
スタ(FETJ、特[GaA S 庖・用いたシロ”/
 トキatによるFETや、ヘテロ接合界面に蓄積する
高移動電子を利用し几HEMT、特にGaAS/AjG
aASへ?CI接合を有する)IEMTは高電子移動度
を有するので超高周波数素子として使用される。FET
やHEMTのマイクロ波特性會向上させる(特に雑音指
数の低下]には、ゲート長の帰線が必要である。
In the case of excimer laser exposure, the exposure source is not suitable for use, etc.
Exposure equipment has not been established. Also, when drawing directly with an electron beam, the drawing time is very long, so the manufacturing efficiency is extremely low and it is not suitable for mass production. have. These technologies are 5solid 5tate
8chnology/Japanese version/August 1986
P52~59rHigh JGaAS FET microlithography technology" 0 Field effect transistor (FETJ, special [GaAs S 庖・Used white")
FETs based on Tokiat and HEMTs using high-mobility electrons accumulated at the heterojunction interface, especially GaAS/AjG
To aAS? IEMTs (with CI junctions) have high electron mobility and are therefore used as ultra-high frequency devices. FET
In order to improve the microwave characteristics of a HEMT or a HEMT (particularly to reduce the noise figure), a return wire of the gate length is necessary.

←1 発明が解決しようとする課題 上述の如く、FET、)lft:MTのマイクロ波特性
を向上させる為にはゲート長を矧ぐする必要があるにも
かかわらず、その線Mはマスクパターンの転写で得られ
るフォトレジストの開孔−で制限されていた。更にX線
露光、エキシマレーザ露光、あるいは電子ビームによる
直接描画は技術が確立されてなかつ友り、生産性が悪く
量産には不向きであった。
←1 Problems to be Solved by the Invention As mentioned above, although it is necessary to shorten the gate length in order to improve the microwave characteristics of FET, )lft:MT, the line M is not connected to the mask pattern. It was limited by the openings in the photoresist obtained by the transfer of the photoresist. Furthermore, the techniques for direct drawing using X-ray exposure, excimer laser exposure, or electron beams have not yet been established, and the productivity is poor, making them unsuitable for mass production.

本発明は従来の紫外線あるいは遠紫外線等を用いた露光
によるマスタパターンのフォトレジストへの転写によっ
て得られる&I錦に制限される事なく、より挟い縣の電
極葡形成することを目的とするものである。
The present invention is not limited to the conventional &I brocade obtained by transferring a master pattern to a photoresist by exposure using ultraviolet rays or deep ultraviolet rays, but aims to form electrodes with more narrow edges. It is.

1+1  課Ut−解決するtめの手段本発明は基板上
に第1のフォトレジスト勿形成する工程と、@J記第1
のフtFVシスト上に第2のフォトレジスt’l−形成
する工程と、前記第2のフォトレジストに第1の開孔を
形成する工程と、前記第1の開孔からiU記第1のフォ
トレジストヶエッチングして基板から電量するに従い拡
がったテーパ状の第2の開孔を形成する工程と、前記第
2の開孔から前記基板上に金IR@lr形成する工程と
、を含むこと′に%徴とする半導体装量の製造方法であ
るり 1rN作用 第2図に示す如く第1のフォトレジストのエツチングレ
ートはイオンビームの入射角に依存し、入射角45°前
後でエツチングレートa最大となる□従って、第1のフ
ォトレジストヲ入射角90DI!ilI後で適当な条件
(真空f’に通常よりも低く設定する等)によりイオン
ビームエツチングすルト、イオンの乱反射が生じ、基板
に離間するに従い拡かつ之テーバ状の第2の開孔を形成
できる(例えばJ、Vac 、sci、’rechni
、 、VOl、12.NO,1。
1+1 Lesson Ut-Means for Solving the Problem The present invention includes a step of forming a first photoresist on a substrate, and a step of forming a first photoresist on a substrate, and
a step of forming a second photoresist on the FV cyst, a step of forming a first hole in the second photoresist, and a step of forming a first hole from the first hole. The method includes the steps of etching the photoresist to form a tapered second opening that widens as the amount of electricity is applied from the substrate, and forming gold IR@lr on the substrate from the second opening. As shown in FIG. Therefore, the incident angle of the first photoresist is 90 DI! After ILI, under appropriate conditions (such as setting the vacuum f' lower than normal), the ion beam etching causes diffuse reflection of the ions, forming a second tapered opening that widens as it gets farther away from the substrate. can (e.g. J, Vac, sci, 'rechni)
, , VOl, 12. NO, 1.

Jan、/Feb、1975  P28〜35#照)Q
この開孔を用いて金属膜を蒸着すると第1の開孔の悟よ
りも帰いゲート電極を形成することができる。
Jan, /Feb, 1975 P28-35 #sho)Q
If a metal film is deposited using this opening, a gate electrode can be formed from the first opening.

(へ)実施例 本発明の実施例を第1図tal乃至(eli参照しつつ
説明するり 一!!せた0EBR−I O00M )131に形成す
る。そして、波長〜260nm(7)Dee3 ptJ
v光源を用いて第2のフォトレジスト13+に0.5μ
m嘔の第1の開孔141ヲ形成する第1図(〜。このと
き、第2のフォトレジスト(31にのみ感光剤?入れて
いるから、光源の光強度等を適当に設定することにより
第2のフォトレジスト131のみに開孔全形成すること
ができる。
(F) Embodiment An embodiment of the present invention is shown in FIGS. And wavelength ~ 260 nm (7) Dee3 ptJ
0.5μ onto the second photoresist 13+ using a v light source.
Forming the first opening 141 (Fig. The entire opening can be formed only in the second photoresist 131.

ビームエウチングし、テーバ状の第2の開孔(51ヲ形
成するりイオンビームエツチングの条件はガス流@x 
o sc am、ガス圧カニ(v4X10  T。
The conditions for ion beam etching are gas flow @
o sc am, gas pressure crab (v4X10T.

rr、FIF’a力3(JOY、加速電圧200vであ
る。この第2の開孔15+の基板側の嗜は第1の開孔1
41の錦が0.5μmであっても約0.15μmとなる
rr, FIF'a force 3 (JOY, acceleration voltage 200v. The position of the second opening 15+ on the substrate side is the same as that of the first opening 1.
Even if the brocade of No. 41 is 0.5 μm, it becomes about 0.15 μm.

成し、この第1のフォトレジスト121 上に膜J11
.5pmの第2のフォトレジスト(例えば感光剤を含1
フズマエッチングして、リセス部16−全形成する。
A film J11 is formed on this first photoresist 121.
.. 5pm of a second photoresist (e.g. containing a photosensitizer)
The entire recessed portion 16 is formed by fusuma etching.

続いて第1のフォトレジスト12+及び第2のフォトレ
ジスH31全マスクとして、At等のゲート金属(金j
!11111)(7]全蒸着しく第1図c山)、リフト
オフ法によりゲート電極(8)全形成する(第1図C6
) ) 0(ト(@明の効果 本発明は以上の説明から明らかな如く第2の開孔の基板
側の幅は第1の開孔の唱よりも狭いものとなる7、よっ
て、従来のフォトエツチングで実現可能な#1幅よりも
七いゲート長のゲート電極を得ることができ、FET、
HEMTの特性の大喝な改善?図ることができる。
Subsequently, a gate metal such as At (gold j
! 11111) (7) Fully evaporated (Figure c in Figure 1), gate electrode (8) is completely formed by lift-off method (Figure C6 in Figure 1)
) ) 0(g(@Effect of Akira) As is clear from the above explanation, the width of the second opening on the substrate side is narrower than that of the first opening. It is possible to obtain a gate electrode with a gate length seven times longer than the #1 width that can be achieved with photoetching, and
Significant improvement in HEMT characteristics? can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図[al乃至+81蚕びは本発明方法を説明する定
めの工程費、明図2第2図は入射角度とエラチングレー
トの関係を示す図である。 II・・・基板%121・・・第1のフォトレジスト、
+31・・・第2のフォトレジスト、+41・・・第1
のf[L、+51・・・第2の開孔、Ifi l・・・
リセス邪、f7+・・・金R模。
Fig. 1 [al to +81] is a diagram showing the prescribed process costs for explaining the method of the present invention; II...Substrate%121...First photoresist,
+31...second photoresist, +41...first
f[L, +51...second opening, Ifi l...
Recess evil, f7+... gold R model.

Claims (1)

【特許請求の範囲】 1、基板上に第1のフォトレジストを形成する工程と、
前記第1のフォトレジスト上に第2のフォトレジストを
形成する工程と、前記第2のフォトレジストに第1の開
孔を形成する工程と、前記第1の開孔から前記第1のフ
ォトレジストをエッチングして基板から離間するに従い
拡がったテーパ状の第2の開孔を形成する工程と、前記
第2の開孔から前記基板上に金属膜を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 2、前記エッチングはイオンビームエッチングであるこ
とを特徴とする請求項1記載の半導体装置の製造方法。
[Claims] 1. Forming a first photoresist on the substrate;
forming a second photoresist on the first photoresist; forming a first hole in the second photoresist; forming a tapered second opening that widens as it moves away from the substrate; forming a metal film on the substrate from the second opening;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is ion beam etching.
JP28912288A 1988-11-15 1988-11-15 Manufacture of semiconductor device Pending JPH02133927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28912288A JPH02133927A (en) 1988-11-15 1988-11-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28912288A JPH02133927A (en) 1988-11-15 1988-11-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02133927A true JPH02133927A (en) 1990-05-23

Family

ID=17739052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28912288A Pending JPH02133927A (en) 1988-11-15 1988-11-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02133927A (en)

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