JPH02130984A - Semiconductor laser device - Google Patents

Semiconductor laser device

Info

Publication number
JPH02130984A
JPH02130984A JP28396788A JP28396788A JPH02130984A JP H02130984 A JPH02130984 A JP H02130984A JP 28396788 A JP28396788 A JP 28396788A JP 28396788 A JP28396788 A JP 28396788A JP H02130984 A JPH02130984 A JP H02130984A
Authority
JP
Japan
Prior art keywords
layer
semiconductor
active layer
inp
semiconductor laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28396788A
Other languages
Japanese (ja)
Inventor
Hiroyuki Nishimoto
浩之 西本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP28396788A priority Critical patent/JPH02130984A/en
Publication of JPH02130984A publication Critical patent/JPH02130984A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the parasitic capacitance inside a semiconductor laser for enhancing the high-frequency characteristics and the reliability by a method wherein the parts excluding the luminescent region are covered with high resistance semiconductor. CONSTITUTION:At InGaAsP active layer 2, a high resistance InP layer 3 and an InGaAsP cap layer 8 are included in an inverse mesa type protrusion part formed in a semiconductor InP substrate 1. A p-InP buried layer 4, an n-InP buried layer 5 are formed respectively on the left and right side of the inverse mesa type protrusion part. In such a structure, the active layer 2 being encircled by the high resistance semiconductor layers 3, almost the whole signal current fed from p side electrode 6 runs into the active layer 2 to reduce the parasitic capacitance. Consequently, the excellent high-frequency response and the reliability of the title semiconductor laser device can be enhanced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体レーザ装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor laser device.

〔従来の技術〕[Conventional technology]

■−v族化合物を用いた発光ダイオード、フォトダイオ
ード等の光半導体素子が作製され、光フアイバ通信、光
情報処理のキーデバイスとて用いられている。特に、半
導体レーデは長距離・大容量光ファイバ通信システムの
開発、実用化を実現する上で最も重要な素子であシ、近
年は特に高速化の検討が鋭意進められている。
(2) Optical semiconductor devices such as light emitting diodes and photodiodes using group V compounds have been produced and are used as key devices in optical fiber communications and optical information processing. In particular, semiconductor radars are the most important element for the development and practical application of long-distance, high-capacity optical fiber communication systems, and in recent years, efforts have been made to improve their speed.

゛半導体レーデの高速化を図るには高周波信号の漏れの
低減が必要であり、このためには発光領域である活性層
領域以外に存在する余分な容量(寄生容量)を小さくす
ることが重要であることが。
゛In order to increase the speed of semiconductor radars, it is necessary to reduce leakage of high-frequency signals, and for this purpose, it is important to reduce the extra capacitance (parasitic capacitance) that exists outside the active layer region, which is the light emitting region. There's something.

「昭58年春季電子通信学会総合全国大会講演論文集」
の論文番号918に於て、小林等によって指摘されてい
る。この寄生容量を低減させるには。
"Collection of Lectures at the Spring 1981 National Conference of the Institute of Electronics and Communication Engineers"
This was pointed out by Kobayashi et al. in paper number 918. To reduce this parasitic capacitance.

活性層の直上の半導体表面層以外の領域に比較的誘電率
の大きなSiO□等の絶縁膜を形成すれば良く。
An insulating film such as SiO□ having a relatively large dielectric constant may be formed in a region other than the semiconductor surface layer directly above the active layer.

このようKすることKよって半導体レーデは2Gb/s
程度の高速での変調が可能になっている。
By doing K like this, the semiconductor radar becomes 2Gb/s.
It is now possible to modulate at relatively high speeds.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、光通信用の光源として使用されている高性能な
埋め込み型半導体レーデは電流狭窄機構としてp−n逆
バイアス接合を用いているため。
However, high-performance embedded semiconductor radars used as light sources for optical communications use a pn reverse bias junction as a current confinement mechanism.

p−n接合容量が大きく高周波の信号電流はこのp−n
接合と半導体層の抵抗を介して活性層以外の領域に漏れ
てしまう。この為半導体層表面に5f02等の絶縁膜を
形成するだけでは超高速半導体レーザを得ることが困難
であった。又、 5io2自体も容量を持っており2例
えば通常の半導体レーザ素子の寸法程度の面積(300
X250μm )に、厚さ3000X程度のSiO□膜
を形成した場合、 5io2自身の持つ容量は109F
程度となり、5GHz以上の高周波変調に対しては十分
に小さな容量とは言えなくなってくる。さらに、 St
O□と半導体との熱膨張率は一桁程度違うので5i02
形成後に半導体内部に歪が残シ、半導体レーデの信頼性
に悪い影響を与えていた。
This p-n junction has a large p-n junction capacitance and the high-frequency signal current
It leaks to regions other than the active layer via the junction and the resistance of the semiconductor layer. For this reason, it has been difficult to obtain an ultrahigh-speed semiconductor laser simply by forming an insulating film such as 5f02 on the surface of the semiconductor layer. In addition, 5io2 itself has a capacitance2, for example, an area approximately the size of a normal semiconductor laser element (300
When a SiO□ film with a thickness of about 3000X is formed on the
Therefore, the capacity cannot be said to be sufficiently small for high frequency modulation of 5 GHz or higher. Furthermore, St.
The coefficient of thermal expansion between O□ and semiconductor is about one order of magnitude different, so 5i02
After formation, distortion remained inside the semiconductor, which had a negative impact on the reliability of the semiconductor radar.

本発明の目的は、このような問題点を解決し。The purpose of the present invention is to solve these problems.

半導体レーデ内部の接合容量を極力低減し、かつ。Reduce the junction capacitance inside the semiconductor radar as much as possible.

活性層に通じる電流経路以外の領域を高抵抗化すること
によシ、高周波電流を効果的に活性層に集中し、超高速
変調可能でかつ高信頼な′半導体レーデ装置を提供する
ことにある。
By increasing the resistance of areas other than the current path leading to the active layer, high-frequency current can be effectively concentrated in the active layer, thereby providing a highly reliable 'semiconductor radar device that is capable of ultra-high-speed modulation. .

〔課題を解決するための手段〕[Means to solve the problem]

本発明では、半絶縁性基板上に活性層、高抵抗半導体層
、キャップ層が順次積層された多層膜半導体基板のほぼ
中央に、半絶縁性基板を含むようにメサ状の突起部を残
し、この突起部の一方側において第1導電型半導体層を
、他方側において第2導電型半導体層で埋め込まれてい
る構成となっている。
In the present invention, a mesa-shaped protrusion is left approximately in the center of a multilayer semiconductor substrate in which an active layer, a high-resistance semiconductor layer, and a cap layer are sequentially stacked on a semi-insulating substrate, so as to include the semi-insulating substrate; One side of this protrusion is filled with a first conductive type semiconductor layer, and the other side is filled with a second conductive type semiconductor layer.

〔作用〕[Effect]

本発明は上記のように構成することにより2発光領域で
ある活性層の周囲は高抵抗半導体層で覆われているため
、いわゆる寄生容量の存在が極めて少ない。従って、半
導体内部を流れる信号電流は高周波域まで殆ど全て活性
層に供給され、高周波特性の優れた半導体レーデ装置と
なる。又、電極構造としては5i02等の比較的誘電率
の大きな絶縁膜を使用せずに十分高周波特性に優れる素
子得ることができるので、fロセスが容易であり、且つ
信頼性にも優れる。
By configuring the present invention as described above, the periphery of the active layer, which is the two light-emitting regions, is covered with a high-resistance semiconductor layer, so that the presence of so-called parasitic capacitance is extremely small. Therefore, almost all of the signal current flowing inside the semiconductor is supplied to the active layer up to the high frequency range, resulting in a semiconductor radar device with excellent high frequency characteristics. Further, since an element with sufficiently excellent high frequency characteristics can be obtained without using an insulating film with a relatively large dielectric constant such as 5i02 as an electrode structure, the f process is easy and the reliability is also excellent.

〔実施例〕〔Example〕

次に2図面によシ本発明の詳細な説明する。 Next, the present invention will be explained in detail with reference to two drawings.

第1図は本発明の実施例を模式的に示したものである。FIG. 1 schematically shows an embodiment of the present invention.

半絶縁性InP基板1上に形成された逆メサの突起部に
はInGaAsP活性層2.高抵抗InP層3 、 I
nGaAsPキャップ層8が含まれている。この逆メサ
の突起の左側はp−InP埋め込み層4.右側はn−I
nP埋め込み層5が形成されている。この構造では、 
InGaAsP活性層2の周囲は高抵抗半導体層である
のでp側電極6から注入された信号電流は殆ど全てIn
GaAsP活性層2に流れ、高周波応答特性に優れた構
造となっている。
An InGaAsP active layer 2. High resistance InP layer 3, I
An nGaAsP cap layer 8 is included. On the left side of this inverted mesa protrusion is a p-InP buried layer 4. On the right is n-I
An nP buried layer 5 is formed. In this structure,
Since the InGaAsP active layer 2 is surrounded by a high-resistance semiconductor layer, almost all of the signal current injected from the p-side electrode 6 is InGaAsP active layer 2.
It flows into the GaAsP active layer 2, resulting in a structure with excellent high frequency response characteristics.

第2図(、)〜(f)に本実施例の製作工程を示す。FIGS. 2(a) to 2(f) show the manufacturing process of this embodiment.

まず第2図(a)に示すように、半絶縁性InP基板l
上K InGaAsP、活性層2をQ、l μ+ffl
 、高抵抗InP層3を2 Am 、 InGaAsP
キャップ層8を0.5μm、MO−CVD装置を用いて
順次成長し多層膜半導体20を形成する。
First, as shown in FIG. 2(a), a semi-insulating InP substrate l
Upper K InGaAsP, active layer 2 is Q, l μ+ffl
, the high resistance InP layer 3 is 2 Am, InGaAsP
A cap layer 8 having a thickness of 0.5 μm is sequentially grown using an MO-CVD apparatus to form a multilayer semiconductor 20.

次に第2図(b)に示すように、窒化シリコン膜11を
マスクとして多層膜半導体層20のほぼ左半分をエツチ
ングする。この時エツチングの深さは少なくとも半絶縁
性InP基板1に達する必要があり2本実施例では約2
.5μmであった。この時マスクストライプの方向は(
100)方向であり、エツチング液としてブロムメチル
溶液(ブロム0.2 c cとメチルアルコール100
ccの混合容液)を用いているので第2図(b)に示す
ように逆メサ状のエツチング面が形成される。
Next, as shown in FIG. 2(b), approximately the left half of the multilayer semiconductor layer 20 is etched using the silicon nitride film 11 as a mask. At this time, the etching depth needs to reach at least the semi-insulating InP substrate 1, and in this embodiment, the etching depth is approximately 2.
.. It was 5 μm. At this time, the direction of the mask stripe is (
100) direction, and the etching solution was a bromomethyl solution (0.2cc of bromine and 100% of methyl alcohol).
cc), an inverted mesa-shaped etched surface is formed as shown in FIG. 2(b).

次に第2図(c) K示すようにエツチングした部分に
MO−CVD装置を用いてp−InP埋め込み層4を形
成する。結晶成長は窒化シリコン膜11上に半導体層が
殆ど成長せず、かつ埋め込まれたp−InP埋め込み層
40表面は平坦になるように成長条件を選択した。この
時窒化シリコン膜ll上に僅かに成長した多結晶半導体
は2次工程である・クツファードフッ酸処理の際に容易
に取除くことが出来る。
Next, as shown in FIG. 2(c) K, a p-InP buried layer 4 is formed in the etched portion using an MO-CVD apparatus. The growth conditions for crystal growth were selected so that almost no semiconductor layer would grow on the silicon nitride film 11 and the surface of the buried p-InP layer 40 would be flat. At this time, the polycrystalline semiconductor slightly grown on the silicon nitride film 11 can be easily removed during the secondary step of Kutufurd hydrofluoric acid treatment.

次に第2図(d)に示すように窒化シリコン膜11をバ
ッフアートフッ酸を用いて一度除去した後。
Next, as shown in FIG. 2(d), the silicon nitride film 11 is once removed using buffered hydrofluoric acid.

半導体多層膜の約右半分がエツチングされるように再度
窒化シリコン膜を形成する。この時多層膜半導体基板の
ほぼ中央に形成される逆メサ状の突起において、 In
GaAsP活性層2の幅は約1.2μmになるように窒
化シリコン膜を形成した。
A silicon nitride film is formed again so that about the right half of the semiconductor multilayer film is etched. At this time, in the inverted mesa-shaped protrusion formed almost at the center of the multilayer semiconductor substrate, In
A silicon nitride film was formed so that the width of the GaAsP active layer 2 was approximately 1.2 μm.

次に第2図(、)に示すようにエツチングされた右半分
をMO−CVD装置を用いてn−InP埋め込み層を形
成する。この場合、p−InP埋め込み層を形成した時
と同様に、エツチング部分のみに平坦な成長層を得るこ
とが出来た。
Next, as shown in FIG. 2(a), an n-InP buried layer is formed on the etched right half using a MO-CVD apparatus. In this case, as in the case of forming the p-InP buried layer, a flat growth layer could be obtained only in the etched portion.

次にバッフアートフッ酸を用いて窒化シリコン膜12を
除去した後、レジスト膜を用いたリフトオフ法により第
2図(f)に示すようにInGaAsP活性層2を含む
逆メサ状の突起の上以外の領域にp側電極6とn側電極
7を同時に形成した。電極金属としてはチタニウム、白
金、金をE−gun蒸着装置を用いて順次形成した。こ
の場合p側電極6とn側電極7の分離間隔は20〜30
μm程度であれば良く、リフトオフ法で十分再現性良く
電極を形成することが出来た。
Next, after removing the silicon nitride film 12 using buffered hydrofluoric acid, a lift-off method using a resist film is performed to remove the parts other than those on the inverted mesa-shaped protrusion including the InGaAsP active layer 2, as shown in FIG. 2(f). A p-side electrode 6 and an n-side electrode 7 were simultaneously formed in the region. As electrode metals, titanium, platinum, and gold were sequentially formed using an E-gun vapor deposition apparatus. In this case, the separation interval between the p-side electrode 6 and the n-side electrode 7 is 20 to 30
It was sufficient to have a thickness of approximately μm, and the electrode could be formed with sufficient reproducibility using the lift-off method.

p、n両電極の熱処理をした後、半絶縁性基板1側を鏡
面研摩して素子厚を約150μmにした後。
After heat-treating both the p and n electrodes, the semi-insulating substrate 1 side was mirror polished to a device thickness of about 150 μm.

研摩面側に融着用金属9であるチタニウムと金を順次形
成してプロセスを終了する。
Titanium and gold, which are fusion metals 9, are sequentially formed on the polished surface side, and the process is completed.

本実施例の半導体レーデはg InGaAsP活性層2
の周囲は高抵抗層で覆われている。従ってp−n接合等
による余分な接合容量が殆ど存在しないために、電極金
属から供給された電気信号は、直流から高周波領域に渡
ってその殆どがI nGaAsP活性層2に供給される
。このため高周波応答特性に優れる半導体レーザ装置が
供給される。
The semiconductor radar of this example is g InGaAsP active layer 2
is surrounded by a high resistance layer. Therefore, since there is almost no extra junction capacitance due to a p-n junction or the like, most of the electrical signals supplied from the electrode metal are supplied to the InGaAsP active layer 2 in the range from direct current to high frequency. Therefore, a semiconductor laser device with excellent high frequency response characteristics is provided.

この半導体レーザウェファを、共振器長が300μmと
なるようにへき開を行い、ストリップライン上に直接融
着を行い半導体レーザを組立て、小信号周波数特性を測
定した。その結果2発振閾値の2倍のバイアス電流値に
於て3dB帯域として10GHz以上の値が得られた。
This semiconductor laser wafer was cleaved so that the cavity length was 300 μm, and the semiconductor laser was assembled by directly fusion bonding onto the strip line, and its small signal frequency characteristics were measured. As a result, a value of 10 GHz or more was obtained as a 3 dB band at a bias current value twice the two-oscillation threshold.

この3dB帯域は短共振器化による光子密度の増加、フ
ォトンライフタイムの減少、冷却等を施すことによシ更
に高い値になると期待できる。
This 3 dB band can be expected to become even higher by increasing the photon density by shortening the resonator, decreasing the photon lifetime, cooling, etc.

ここで第1図、第2図に示す実施例においてはInGa
AsP系半導体レーザを用いたが、その他の材料2例え
ばGaAlAs系等の半導体レーデにも適用可能である
。又本構造は9分布帰還反射型構造(DFB−LD) 
、分布ブラッグ反射型構造(DBR−LD )にも容易
に適用可能である。この場合には超高速変調が可能で、
且つ単一軸モードで発振する半導体レーザ装置が容易に
得られる。
In the embodiment shown in FIGS. 1 and 2, InGa
Although an AsP-based semiconductor laser is used, it is also applicable to semiconductor lasers made of other materials such as GaAlAs. Also, this structure is a 9 distributed feedback reflection type structure (DFB-LD).
, it can also be easily applied to distributed Bragg reflection type structures (DBR-LD). In this case, ultra-high-speed modulation is possible,
Moreover, a semiconductor laser device that oscillates in a single-axis mode can be easily obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は2発光領域近傍以外の部分
を高抵抗半導体層で覆うことによシ、半導体レーザ内部
の寄生容量を極力除去することが可能になる。更にSt
O□等の誘電体膜を使用していないため、信頼性につい
ても大幅に向上する。
As explained above, the present invention makes it possible to eliminate the parasitic capacitance inside the semiconductor laser as much as possible by covering the portion other than the vicinity of the two light-emitting regions with a high-resistance semiconductor layer. Moreover, St.
Since a dielectric film such as O□ is not used, reliability is also greatly improved.

以上の点から本発明によ’) −10GHz以上の変調
帯域を有し、かつ信頼性にも優れる超高速半導体レーデ
装置を容易に得ることができる。
In view of the above points, the present invention can easily provide an ultra-high speed semiconductor radar device which has a modulation band of -10 GHz or more and is also excellent in reliability.

InGaAsP活性層、3は高抵抗InP層、8はIn
GaAsPキ+yゾ層、4はp−InP埋め込み層、5
はn−InP埋め込み層、6はp−側電極、7Fin−
側電極である。
InGaAsP active layer, 3 high resistance InP layer, 8 In
GaAsP quad layer, 4 is p-InP buried layer, 5
is an n-InP buried layer, 6 is a p-side electrode, 7Fin-
This is the side electrode.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の構造を示す断面図。 第2図(、)〜(f)は第1図に示す実施例の製作工程
を順に示す断面図である。 図において1は半絶縁性InP基板、2は第2図
FIG. 1 is a sectional view showing the structure of an embodiment of the present invention. 2(a) to 2(f) are cross-sectional views sequentially showing the manufacturing process of the embodiment shown in FIG. 1. In the figure, 1 is a semi-insulating InP substrate, and 2 is a semi-insulating InP substrate.

Claims (1)

【特許請求の範囲】[Claims] 1、半絶縁性基板上に活性層、高抵抗半導体層、及びキ
ャップ層が順次積層されて予め定められた方向に延びる
メサ状の突起部と、該突起部の一方側で前記半絶縁性基
板上に形成された第1の導電型半導体層と、前記突起部
の他方側で前記半絶縁性基板上に形成された第2の導電
型半導体層とを有することを特徴とする半導体レーザ装
置。
1. A mesa-shaped protrusion in which an active layer, a high-resistance semiconductor layer, and a cap layer are sequentially laminated on a semi-insulating substrate and extending in a predetermined direction, and the semi-insulating substrate on one side of the protrusion. A semiconductor laser device comprising: a first conductive type semiconductor layer formed on the semi-insulating substrate; and a second conductive type semiconductor layer formed on the semi-insulating substrate on the other side of the protrusion.
JP28396788A 1988-11-11 1988-11-11 Semiconductor laser device Pending JPH02130984A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28396788A JPH02130984A (en) 1988-11-11 1988-11-11 Semiconductor laser device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28396788A JPH02130984A (en) 1988-11-11 1988-11-11 Semiconductor laser device

Publications (1)

Publication Number Publication Date
JPH02130984A true JPH02130984A (en) 1990-05-18

Family

ID=17672549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28396788A Pending JPH02130984A (en) 1988-11-11 1988-11-11 Semiconductor laser device

Country Status (1)

Country Link
JP (1) JPH02130984A (en)

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