JPH04144297A - Semiconductor laser device - Google Patents

Semiconductor laser device

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Publication number
JPH04144297A
JPH04144297A JP26898690A JP26898690A JPH04144297A JP H04144297 A JPH04144297 A JP H04144297A JP 26898690 A JP26898690 A JP 26898690A JP 26898690 A JP26898690 A JP 26898690A JP H04144297 A JPH04144297 A JP H04144297A
Authority
JP
Japan
Prior art keywords
layer
inp
ingaasp
semiconductor laser
activated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26898690A
Other languages
Japanese (ja)
Inventor
Hiroyuki Nishimoto
浩之 西本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP26898690A priority Critical patent/JPH04144297A/en
Publication of JPH04144297A publication Critical patent/JPH04144297A/en
Pending legal-status Critical Current

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  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To obtain a highly reliable semiconductor laser device capable of an ultra high-speed modulation, by reducing junction capacitances inside the semiconductor laser, and by making the resistance values of the regions other than the current paths leading to an activated layer high, and further, by concentrating effectively high-frequency currents on the activated layer. CONSTITUTION:On an inverse mesa protruding part 20 formed on a substrate 1 of n-InP, laminated are in succession a buffer layer 2 of n-InP, an activated layer 3 of InGaAsP, and a clad layer 4 of p-InP. Further, a first high resistance layer 5 of InP, a stop layer 6 of InGaAsP, and a second high resistance layer 7 of InP are so formed in succession as to cover the inverse mesa protruding part 20. At this time, the stop layer 6 of InGaAsP is so formed as to be at the higher position than the activated layer 3 of InGaAsP, when using the substrate 1 of n-InP as a reference. Therefore, since the surroundings of the activated layer 3 of InGaAsP are the semiconductor layers of high resistance values, most of the currents implanted from a p-side electrode 10 flow into the activated layer 3 of InGaAsP, and an excellent structure in a high-frequency response speed is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体レーザ装置に関する 〔従来の技術〕 従来、この種の半導体レーザ装置は、発光領域である活
性層以外に存在する寄生容量を低減させ高周波信号の漏
れを抑制するために、活性層の直上の半導体表面層以外
に比較的誘電率の小さなSiO2等の絶縁膜形成し、2
 G b / s程度の高速変調を可能にしていた。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a semiconductor laser device [Prior Art] Conventionally, this type of semiconductor laser device has been designed to reduce parasitic capacitance existing in areas other than the active layer, which is the light emitting region. In order to suppress the leakage of high-frequency signals, an insulating film such as SiO2 with a relatively low dielectric constant is formed on the semiconductor surface layer directly above the active layer.
It enabled high-speed modulation on the order of Gb/s.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来光通信用の光源として使用されている高性
能な埋込み型半導体レーザ装置は、電流狭窄構造として
p−n逆バイアス接合を用いているなめ、p−n接合容
量が大きく高周波の信号電流はこのp−n接合と半導体
層の抵抗を介して活性層以外の領域に洩れてしまう。そ
のため半導体層表面にSiO2等の絶縁膜を形成するだ
けでは超高速半導体レーザ装置を得ることが困難であっ
た。
The high-performance embedded semiconductor laser device conventionally used as a light source for optical communications mentioned above uses a p-n reverse bias junction as a current confinement structure, so it has a large p-n junction capacitance and cannot handle high-frequency signal currents. leaks to regions other than the active layer via this pn junction and the resistance of the semiconductor layer. Therefore, it has been difficult to obtain an ultrahigh-speed semiconductor laser device simply by forming an insulating film such as SiO2 on the surface of the semiconductor layer.

またSiO2自体も容量を持っており、例えば通常の半
導体レーザ素子程度の面積(300X250μm2)に
、厚さ3000A程度のSiO2膜を形成した場合、S
 i 02自身の持つ容量は10pF程度となり、5G
Hz以上の高周波変調に対しては無視できる大きさでは
なかった。更に5i02と半導体との熱膨張率は一桁程
度違うため、5i02形成後に半導体内部に歪みが残り
、半導体レーザの信頼性に影響を与えていた。
In addition, SiO2 itself has a capacitance. For example, if a SiO2 film with a thickness of about 3000 A is formed on an area about the size of a normal semiconductor laser element (300 x 250 μm2), the S
The capacitance of i02 itself is about 10pF, and 5G
The magnitude was not negligible for high frequency modulation of Hz or higher. Furthermore, since the thermal expansion coefficients of 5i02 and the semiconductor differ by about one order of magnitude, distortion remains inside the semiconductor after 5i02 is formed, which affects the reliability of the semiconductor laser.

本発明の目的は、半導体レーザ内部の接合容量を低減し
且つ、活性層に通じる電流経路以外の領域を高抵抗化す
ることにより、高周波電流を効果的に活性層に集中し、
超高速変調が可能で信頼性の高い半導体レーザ装置を提
供することにある。
The purpose of the present invention is to reduce the junction capacitance inside the semiconductor laser and increase the resistance of areas other than the current path leading to the active layer, thereby effectively concentrating high frequency current in the active layer.
The object of the present invention is to provide a highly reliable semiconductor laser device capable of ultra-high-speed modulation.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体レーザ装置は、導電型半導体基板上に形
成された導電型バッファ層、活性層、および導電型クラ
ッド層を含むメサ状の突起が、前記導電型半導体基板を
基準とした時、前記活性層より高い位置に形成された拡
散ストップ層を挟んだ高抵抗層で埋め込まれ且つ、前記
導電型クラッド層に達するまで不純物拡散層が形成され
ている。
In the semiconductor laser device of the present invention, when a mesa-shaped protrusion including a conductive buffer layer, an active layer, and a conductive cladding layer formed on a conductive semiconductor substrate is based on the conductive semiconductor substrate, An impurity diffusion layer is buried with high resistance layers sandwiching a diffusion stop layer formed at a higher position than the active layer, and is formed up to the conductive type cladding layer.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の構造を示+断面図、第2図
は本発明の一実施例の製造工程のm造を示す断面図であ
る。
FIG. 1 is a cross-sectional view showing the structure of an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

第1図において、n−1nP基板1に形成された逆メサ
の突起部20には、n−InPバッファ層2.InGa
AsP活性層3.p−InPクラッド層4が順次積層さ
れているにの逆メサの突起20を覆うように第1のIn
P高抵抗層5゜I nGaAsPストップ層6.第2の
InP高抵抗層7が順次形成されている。この時I n
GaAsPストップ層6は、InGaAsP活性層3よ
りも、n−1nP基板1を基準にした時に高い位置にく
るように形成されている。
In FIG. 1, an n-InP buffer layer 2. InGa
AsP active layer 3. The first InP cladding layer 4 is sequentially laminated so as to cover the protrusion 20 of the inverted mesa.
P high resistance layer 5°I nGaAsP stop layer 6. A second InP high resistance layer 7 is sequentially formed. At this time I n
The GaAsP stop layer 6 is formed at a higher position than the InGaAsP active layer 3 with respect to the n-1nP substrate 1.

不純物拡散の拡散の深さは、一般に拡散時間で制御する
が、拡散炉の温度プロファイル、拡散雰囲気の蒸気圧の
制御が困難なため制御性が良くない。従って拡散の深さ
のバラツキにより拡散フロントがn−InPバッファ層
2もしくはI nGaAsP活性As上到達することを
防ぐためInGaAsPスト71層6を設けている。I
nPとInGaAsPとの拡散速度の差、すなわちIn
GaAsPの方がInPよりも拡散速度が遅いことを利
用している6 InGaAsP活性層3の周囲は、高抵抗半導体層であ
るためp側電g!10から注入された信号電流はほとん
どInGaAsP活性層3に流れ、高周波応答速度の優
れた構造となる。
The depth of impurity diffusion is generally controlled by the diffusion time, but controllability is not good because it is difficult to control the temperature profile of the diffusion furnace and the vapor pressure of the diffusion atmosphere. Therefore, the InGaAsP layer 71 is provided to prevent the diffusion front from reaching the n-InP buffer layer 2 or the InGaAsP active As due to variations in the diffusion depth. I
The difference in diffusion rate between nP and InGaAsP, that is, In
This takes advantage of the fact that GaAsP has a slower diffusion rate than InP.6 Since the InGaAsP active layer 3 is surrounded by a high-resistance semiconductor layer, the p-side electric potential g! Most of the signal current injected from 10 flows into the InGaAsP active layer 3, resulting in a structure with excellent high frequency response speed.

次に第2図を参照して製造工程について説明する。n−
InP基板1上には半導体層を積層するためのMO−C
VD装置を用いて、第2図(A)に示すようにn−In
Pバッファ層2を3μm。
Next, the manufacturing process will be explained with reference to FIG. n-
MO-C for stacking semiconductor layers on the InP substrate 1
Using a VD device, as shown in FIG. 2(A), n-In
P buffer layer 2 has a thickness of 3 μm.

InGaAsP活性層3をO,llzm、 P−InP
クラッド層4を1μm順次成長させ多層膜半導体20を
形成する。
InGaAsP active layer 3 is O,llzm, P-InP
A multilayer semiconductor 20 is formed by sequentially growing the cladding layer 4 to a thickness of 1 μm.

次に第2図(B)に示すように、幅2.5μmの窒化シ
リコン膜20をマスクとして逆メサ上の突起をエツチン
グ工法を用いて多層膜半導体層20のほぼ中央に形成す
る。エツチングの深さはn−InPバッファ層2に達す
るまでの例えば約2μmである。この時マスクストライ
プの方向は<100>方向であり、エツチング液とし、
てブロムメチル溶液(ブロム0.2ccとメチルアルコ
ール100ccの混合溶液〉を用いて第2図(B)に示
すように逆メサ状の突起が形成される。
Next, as shown in FIG. 2(B), using the silicon nitride film 20 having a width of 2.5 μm as a mask, a protrusion on the inverted mesa is formed approximately at the center of the multilayer semiconductor layer 20 using an etching method. The etching depth is, for example, approximately 2 μm until reaching the n-InP buffer layer 2. At this time, the direction of the mask stripe is the <100> direction, and the etching solution is
Using a bromine methyl solution (a mixed solution of 0.2 cc of bromine and 100 cc of methyl alcohol), an inverted mesa-shaped protrusion is formed as shown in FIG. 2(B).

次に第2図(C)に示すようにMO−CVD装置を用い
て第1のInP高抵抗層5を1,51tm、InGaA
sPスト71層6を0.471m形成する。この時逆メ
サ状の突起上には窒化シリコンン膜20が形成されたま
まであるため、半導体層は成長しない。窒化シリコン1
IK20をバッフアートフッ酸を用いて除去した後、再
びMO−CVD装置を用いて第2のInP高抵抗層7を
1、’1μm、p−I nGaAsPキャップ層9を0
.5μmに順次形成する。
Next, as shown in FIG. 2(C), a first InP high resistance layer 5 of 1,51 tm and InGaA
An sP strike 71 layer 6 is formed to a thickness of 0.471 m. At this time, since the silicon nitride film 20 remains formed on the inverted mesa-shaped protrusion, the semiconductor layer does not grow. silicon nitride 1
After removing the IK20 using buffered hydrofluoric acid, the second InP high resistance layer 7 is formed to have a thickness of 1 μm, and the p-I nGaAsP cap layer 9 is formed to a thickness of 0 μm using the MO-CVD apparatus again.
.. Sequentially formed to have a thickness of 5 μm.

次に第2図(D>において全面的に不純物拡散を行うが
、p−InPクラッド層4に拡散フロントが到達するよ
うに、その拡散時間は長く設定する。この時InGaA
sPストップ層6によりp−InPクラッド層4層外以
外では拡散の進行は遅いため、拡散フロントがn−In
Pバッファ層2もしくはInGaAsP活性層3に到達
しないため、InGaAsP活性N3の周囲に低抵抗層
の電流経路が形成されない。
Next, impurity diffusion is performed over the entire surface in FIG.
Due to the sP stop layer 6, diffusion progresses slowly except outside the four p-InP cladding layers, so the diffusion front is
Since the current does not reach the P buffer layer 2 or the InGaAsP active layer 3, a current path in the low resistance layer is not formed around the InGaAsP active layer N3.

この後p −1n G a A s Pキャブ1層9側
には、蒸着金属としてCrとAuを抵抗加熱真空蒸着法
により順次蒸着し、電極を形成する。更に380℃の水
素雰囲気中で5分間熱処理を行った後、n−InP基板
1側を厚さ150μmに鏡面研磨を行う。続いてn−側
電極として、Au・Qe7”Niをn−InP基板1側
に順次蒸着した後380℃の水素雰囲気中で5分間熱処
理を行う。
Thereafter, Cr and Au are sequentially vapor-deposited as vapor-deposited metals on the p-1n GaAsP cab 1 layer 9 side by a resistance heating vacuum vapor deposition method to form an electrode. After further heat treatment for 5 minutes in a hydrogen atmosphere at 380° C., the n-InP substrate 1 side is mirror-polished to a thickness of 150 μm. Subsequently, Au.Qe7''Ni was sequentially deposited on the n-InP substrate 1 side as an n-side electrode, and then heat-treated for 5 minutes in a hydrogen atmosphere at 380°C.

最後に保護電極としてp側電極]0側にTi/Pt/’
Au、n側電極11側にT i 7’ A uをスパッ
タリング装置で蒸着して製造工程を終了する。
Finally, the p-side electrode as a protective electrode] Ti/Pt/' on the 0 side
Au and T i 7' Au are deposited on the n-side electrode 11 side using a sputtering device to complete the manufacturing process.

なおこの半導体レーザウユファを共振器長が300μm
となるようにへき開を行い、ストリップライン上に直接
融着を行って半導体し−ザを組立て、小信号周波数特性
を測定した結果、発振しきい値の2倍のバイアス電流値
において、3db帯域として10GHz以上の値が得ら
れた。この3db帯域は、短共振器化による光子密度の
増加、フォトンライフタイムの減少、冷却等を施すこと
により、更に改善されることが期待できる。
The cavity length of this semiconductor laser is 300 μm.
The semiconductor was cleaved so that A value of 10 GHz or more was obtained. This 3 db band can be expected to be further improved by increasing the photon density by shortening the cavity, decreasing the photon lifetime, cooling, etc.

以上I nGaAsP系半導体レーザについて説明した
が、その他の材料例えばGaAlAs系の半導体レーザ
にも適用可能である。また本構造は、分布帰還型構造(
DFB−LD)や分布ブラッグ反射型構造(DBR−L
D)にも容易に適用可能で、超高速変調が可能で且つ、
単一軸モードで発振する半導体レーザ装置が容易に得ら
れる。
Although the InGaAsP semiconductor laser has been described above, it is also applicable to semiconductor lasers made of other materials, such as GaAlAs. This structure also has a distributed feedback structure (
DFB-LD) and distributed Bragg reflection structure (DBR-L)
D) can be easily applied, ultra-high-speed modulation is possible, and
A semiconductor laser device that oscillates in a single-axis mode can be easily obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、発光領域近傍以外の部分
を高抵抗半導体層で覆い、半導体レーザ内部の寄生容量
を除去すること可能な構造を容易に且つ、再現性がよく
得ることができる。更に5i02等の誘電体膜を使用し
ていないなめ、信頼性が向上するという効果がある。
As explained above, according to the present invention, a structure in which a portion other than the vicinity of the light emitting region is covered with a high-resistance semiconductor layer and parasitic capacitance inside a semiconductor laser can be removed can be easily obtained with good reproducibility. Furthermore, since a dielectric film such as 5i02 is not used, reliability is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構造と示す断面図、第2図
は本発明の一実施例の製造工程の構造を示す断面図であ
る。 1 ・−n−1n P基板、2− n −I r+ P
バフフッ層、3−InGaAsP活性層、4−p−In
Pクラッド層、5・・・第1のI n F’高抵抗層、
6・・・InGaAsPストップ層、7・・第2のIn
P高抵抗層、8・・・拡散層、9−p −T nGaA
sPキャップ層、10・・・p側電極、11・・n@電
極、20・・・逆メサ突起部。
FIG. 1 is a sectional view showing a structure of an embodiment of the present invention, and FIG. 2 is a sectional view showing a structure of a manufacturing process of an embodiment of the invention. 1 ・-n-1n P substrate, 2- n -I r+ P
Buff layer, 3-InGaAsP active layer, 4-p-In
P cladding layer, 5... first I n F' high resistance layer,
6... InGaAsP stop layer, 7... Second In
P high resistance layer, 8...diffusion layer, 9-p-T nGaA
sP cap layer, 10...p-side electrode, 11...n@electrode, 20...inverted mesa protrusion.

Claims (1)

【特許請求の範囲】[Claims] 導電型半導体基板上に形成された導電型バッファ層、活
性層、および導電型クラッド層を含むメサ状の突起が、
前記導電型半導体基板を基準とした時、前記活性層より
高い位置に形成された拡散ストップ層を挟んだ高抵抗層
で埋め込まれ且つ、前記導電型クラッド層に達するまで
不純物拡散層が形成されていることを特徴とする半導体
レーザ装置。
A mesa-shaped protrusion including a conductive buffer layer, an active layer, and a conductive cladding layer formed on a conductive semiconductor substrate is
When the conductive type semiconductor substrate is used as a reference, an impurity diffusion layer is buried with a high resistance layer sandwiching a diffusion stop layer formed at a higher position than the active layer, and is formed until reaching the conductive type cladding layer. A semiconductor laser device characterized by:
JP26898690A 1990-10-05 1990-10-05 Semiconductor laser device Pending JPH04144297A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26898690A JPH04144297A (en) 1990-10-05 1990-10-05 Semiconductor laser device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26898690A JPH04144297A (en) 1990-10-05 1990-10-05 Semiconductor laser device

Publications (1)

Publication Number Publication Date
JPH04144297A true JPH04144297A (en) 1992-05-18

Family

ID=17466072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26898690A Pending JPH04144297A (en) 1990-10-05 1990-10-05 Semiconductor laser device

Country Status (1)

Country Link
JP (1) JPH04144297A (en)

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