JPH02130953A - Inverse-blocking transistor module - Google Patents

Inverse-blocking transistor module

Info

Publication number
JPH02130953A
JPH02130953A JP63285267A JP28526788A JPH02130953A JP H02130953 A JPH02130953 A JP H02130953A JP 63285267 A JP63285267 A JP 63285267A JP 28526788 A JP28526788 A JP 28526788A JP H02130953 A JPH02130953 A JP H02130953A
Authority
JP
Japan
Prior art keywords
transistor
diode
current
units
symmetrically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63285267A
Other languages
Japanese (ja)
Other versions
JP2592116B2 (en
Inventor
Yoshio Sakai
吉男 坂井
Kiyoshi Nakamura
清 中村
Takeyoshi Ando
武喜 安藤
Susumu Kobayashi
進 小林
Hiroto Suyama
巣山 廣登
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Hitachi Ltd
Original Assignee
Fuji Electric Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Hitachi Ltd filed Critical Fuji Electric Co Ltd
Priority to JP63285267A priority Critical patent/JP2592116B2/en
Publication of JPH02130953A publication Critical patent/JPH02130953A/en
Application granted granted Critical
Publication of JP2592116B2 publication Critical patent/JP2592116B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

Landscapes

  • Power Conversion In General (AREA)

Abstract

PURPOSE:To make internal chip units share current uniformly by arranging a plurality of transistor and diode chips constituting a module symmetrically and arranging pairs of positive and negative main terminals symmetrically on the plane of a module container. CONSTITUTION:Diodes FRD1 and FRD2 are connected in series to transistor units Tr1 and Tr2, respectively, to bear inverse dielectric strength. A pair of positive main terminals A1 and A2 as well as a pair of negative main terminals E1 and E2 are arranged symmetrically so that main current can be extracted under the same conditions from the two internal transistor-diode units. By providing two pairs of positive and negative main terminals symmetrically for the transistor units in this manner, current can be balanced uniformly between the transistor and diode units.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は逆阻止形トランジスタモジニールの構造に係り
、特に大電力変換器の構築に好適な逆阻止形トランジス
タモジニールを提供する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the structure of a reverse blocking transistor modinyl, and particularly provides a reverse blocking transistor modinyl suitable for constructing a high power converter.

〔従来の技術〕[Conventional technology]

従来、トランジスタを用いた大電力変換器として、電流
容量数百アンペア以上のものが望まれる場合は多数のト
ランジスタ及びダイオードの集合体として、並列接続に
より電流容量を満足させることが多い。例えば、100
 Aの電流容量のトランジスタチップ及びダイオードチ
ップを各4個並列配置すれば、400Aの電流容量を得
ることができる。
Conventionally, when a current capacity of several hundred amperes or more is desired as a high power converter using transistors, the current capacity is often satisfied by connecting a large number of transistors and diodes in parallel as an aggregate. For example, 100
If four transistor chips and four diode chips each having a current capacity of A are arranged in parallel, a current capacity of 400A can be obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、トランジスタのチップ並列数を増すと、外部
回路と接続するための端子の位置からチップ面上の電極
までの距離が遠いチップは近いチップよりインダクタン
スが増えるという問題が次第に顕著になってくる。その
結果、インダクタンスの低い位置にあるチップは、イン
ダクタンスの高い位置にあるチップより電流が流れ易く
、電流集中を起こして過電流破壊に至るおそれも大きく
なるという問題があった。
However, as the number of transistor chips in parallel increases, the problem gradually becomes more apparent that chips whose distance from the position of the terminal for connection to an external circuit to the electrode on the chip surface is far are greater than those which are closer. As a result, there is a problem in that current flows more easily in a chip located at a low inductance position than in a chip located at a high inductance position, increasing the risk of current concentration leading to overcurrent damage.

本発明は以上のことを鑑みて、複数のトランジスタチッ
プを並列接続させて大きな電流容量とする場合に、電流
の不均一に基づく過電流破壊が生。
In view of the above, the present invention has been developed to reduce the risk of overcurrent damage due to non-uniformity of current when a plurality of transistor chips are connected in parallel to achieve a large current capacity.

しにくく高信頼性の逆阻止形トランジスタモジュールを
提供することを目的とする。
The purpose of the present invention is to provide a reverse blocking transistor module that is difficult to prevent and has high reliability.

〔課題を解決するための手段〕[Means to solve the problem]

そのような目的を達成するために本発明の逆阻止形トラ
ンジスタモジコールは複数のトランジスタチップとそれ
らのトランジスタのコレクタに直列接続された複数のダ
イオードチップとが共通金属基板上に絶縁板を介して固
着され、前記ダイオードチップからは2本にまとめられ
たアノード主端子、前記トランジスタチップからは2本
にまとめられたエミッタ主端子とベース端子が垂直方向
に立ち上げられて絶縁容器に封入されるものにおいて、
前記各アノード主端子、各エミッタ主端子が互いに対称
的な形状にされると共に絶縁容器の外表面において互い
に対称に配置される構成とする。
In order to achieve such a purpose, the reverse blocking transistor module of the present invention has a plurality of transistor chips and a plurality of diode chips connected in series to the collectors of these transistors on a common metal substrate through an insulating plate. The main anode terminal is fixed to the diode chip, and the main emitter terminal and the base terminal are fixed to the diode chip. In,
Each of the anode main terminals and each emitter main terminal has a symmetrical shape and is arranged symmetrically on the outer surface of the insulating container.

〔作用〕[Effect]

大容量の逆阻止形トランジスタモジュールを構成するに
際し、複数のトランジスタ及びダイオード単位への電流
を均等にするため、まず同数のトランジスタ及びダイオ
ードの並列設置からなる二つのトランジスタ・ダイオー
ド単位を互いに対称に配置する。先の例で説明すれば、
各トランジスタ・ダイオード単位が電流400Aの容量
を持ち、二つのトランジスタ・ダイオード単位の集合と
して合わせて800Aの電流容量が得られる。ここで、
両トランジスタ単位に電流を等しく流すための条件を正
確に一致させるため、各トランジスタ及びダイオードか
ら取り出す主電流端子を両トランジスタ・ダイオード単
位毎に対称に2組(正・負)備える。この結果、トラン
ジスタモジュールとしての正・負主端子及び補助コレク
タ端子はそれぞれ対をなし対称形に配置される。
When constructing a large-capacity reverse-blocking transistor module, in order to equalize the current to multiple transistors and diode units, first arrange two transistor/diode units symmetrically with each other, each consisting of the same number of transistors and diodes installed in parallel. do. To explain with the previous example,
Each transistor/diode unit has a current capacity of 400A, and the two transistor/diode units collectively have a current capacity of 800A. here,
In order to accurately match the conditions for allowing current to flow equally through both transistor units, two sets (positive and negative) of main current terminals taken out from each transistor and diode are symmetrically provided for each transistor/diode unit. As a result, the positive and negative main terminals and auxiliary collector terminals of the transistor module are arranged in pairs and symmetrically.

このように主電流端子をトランジスタ・ダイオード単位
毎に取り出すことにより、トランジスタ・ダイオード単
位毎の電流バランスが平衡し、逆阻止形トランジスタモ
ジュールとして安定した性能が得られる。
By taking out the main current terminal for each transistor/diode unit in this way, the current balance for each transistor/diode unit is balanced, and stable performance as a reverse blocking transistor module can be obtained.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図ないし第4図を用いて
詳細に説明する。各図面に共通して付けられた同符号は
互いに同機能の相当する個所を示す。
Hereinafter, one embodiment of the present invention will be described in detail using FIGS. 1 to 4. The same reference numerals assigned in common to each drawing indicate parts having the same function.

第1図は本発明の外部接続用端子の配置を示す外形図を
示し、第2図(a)は第1図の樹脂ケースの蓋を除去し
た内部構造を示す上面図であり、第2図(b)は側断面
図を示す。第3図は第1図、第2図で示される本発明の
逆阻止形トランジスタモジュールの内部配線を示す等価
回路図である。
FIG. 1 shows an outline view showing the arrangement of external connection terminals of the present invention, FIG. 2(a) is a top view showing the internal structure of the resin case in FIG. 1 with the lid removed, and FIG. (b) shows a side sectional view. FIG. 3 is an equivalent circuit diagram showing the internal wiring of the reverse blocking transistor module of the present invention shown in FIGS. 1 and 2. FIG.

この逆阻止形トランジスタモジュールは、第3図に示さ
れているようにトランジスタTr、、ダイオードFRD
IとトランジスタTr2.ダイオードFRD2との二つ
のトランジスタ・ダイオード単位の並列接続から成り、
第2図に示されるように各トランジスタTrI、Tr2
とダイオードFRDI。
This reverse blocking transistor module includes a transistor Tr, a diode FRD, and a diode FRD as shown in FIG.
I and transistor Tr2. Consists of parallel connection of two transistor/diode units with diode FRD2,
As shown in FIG. 2, each transistor TrI, Tr2
and diode FRDI.

FRD2はそれぞれ異なる半導体チップにより形成され
ている。
The FRDs 2 are formed by different semiconductor chips.

さらに各トランジスタTr、、Tr2は第3図に示すよ
うにそれぞれ3段増幅のダーリントン結合から成ってい
る。Tr1+ないしTr、、、が第1のトランジスタ単
位Tr、を構成し、Tr2+ないしTr2.が第2のト
ランジスタ単位Tr!を構成している。各トランジスタ
単位Tr、 、 Tr2には、それぞれダイオードFR
DI及びFRD2が直列接続されて逆耐電圧を負担して
いる。これらのトランジスタTr。
Furthermore, each of the transistors Tr, Tr2 consists of a three-stage amplification Darlington coupling as shown in FIG. Tr1+ to Tr,... constitute a first transistor unit Tr, and Tr2+ to Tr2. is the second transistor unit Tr! It consists of Each transistor unit Tr, Tr2 has a diode FR.
DI and FRD2 are connected in series and bear the reverse withstand voltage. These transistors Tr.

Tr、及びダイオードFRDI、FRD2は第2図に示
すように例えばそれぞれ4個のトランジスタチップ及び
ダイオードチップの集合(並列接続)から成り立ってい
る。
As shown in FIG. 2, the Tr and the diodes FRDI and FRD2 each consist of, for example, a set of four transistor chips and four diode chips (connected in parallel).

第1図ないし第3図においてAI及びA2は1対の正の
主端子、El及びE2は負の主端子である。これらの1
対の主端子は、内部の二つのトランジスタ・ダイオード
単位から同一条件で主電流を引き出すように対称的な形
状に構成されている。
In FIGS. 1 to 3, AI and A2 are a pair of positive main terminals, and El and E2 are a pair of negative main terminals. 1 of these
The main terminals of the pair are configured in a symmetrical shape so as to draw main current from the two internal transistor/diode units under the same conditions.

bはベース端子、eは信号入出力用の補助エミッタ端子
、bl、b2はこのトランジスタモジュールの並列接続
時の接続用の端子である。
b is a base terminal, e is an auxiliary emitter terminal for signal input/output, and bl and b2 are connection terminals when the transistor modules are connected in parallel.

第1図ないし第3図に示す本発明の逆阻止形トランジス
タモジュールを用いて電力変換器を構成する場合、一般
にはその等価回路は第4図になる。
When a power converter is constructed using the reverse blocking transistor module of the present invention shown in FIGS. 1 to 3, the equivalent circuit thereof is generally shown in FIG. 4.

ACは電源、Lは負荷を示す。さらに第1図(a)で示
されるトランジスタモジネールの上面図を使って第4図
に担当する配線接続を示したものを第5図に表す。トラ
ンジスタチップ及びダイオードチップを複数個並列配置
にして大容量のトランジスタモジニールを構成する場合
、各トランジスタ及びダイオードの電流分担が均一にな
ることが重要である。本実施例では、トランジスタ単位
毎に対称に正・負主端子を2組出すことによって、トラ
ンジスタ及びダイオード単位の電流バランスが均一とす
ることが可能になり高信頼性の電力変換器が構成できる
AC indicates a power supply, and L indicates a load. Furthermore, using the top view of the transistor module shown in FIG. 1(a), the wiring connections in charge of FIG. 4 are shown in FIG. 5. When constructing a large-capacity transistor module by arranging a plurality of transistor chips and diode chips in parallel, it is important that the current sharing among the transistors and diodes is uniform. In this embodiment, by symmetrically providing two sets of positive and negative main terminals for each transistor unit, it is possible to make the current balance of each transistor and diode unit uniform, and a highly reliable power converter can be constructed.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、大電流容量の逆阻止形トランジスタモ
ジュールにおいて、このモジュールを構成する複数のト
ランジスタ及びダイオードチップあるいは、トランジス
タ及びダイオード単位の配置条件を対称にし、かつ正負
主端子をモジ、 −Jし容器平面上に2本対称に配置し
たことにより、内部のチップ及びトランジスタ及びダイ
オード単位の電流分担が均一にできる効果が得られる。
According to the present invention, in a reverse blocking transistor module having a large current capacity, the arrangement conditions of a plurality of transistors and diode chips or transistors and diodes constituting this module are made symmetrical, and the positive and negative main terminals are connected to By arranging the two symmetrically on the plane of the container, an effect can be obtained in which the current sharing among the internal chips, transistors, and diodes can be made uniform.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、一実施例の外形図で、(a)は上面図、(ハ
)は側面図、M2図は本発明の内部配置図、第3図は本
発明の内部等価回路図、第4図は本発明のトランジスタ
モジニールを用いた電力変換器の結線図、第5図は第4
図の実装図である。 A1.A2・・・・・アノード(正)端子、El、 E
、  エミッタ(負)端子、Tr、 、 Tr2− )
ランジスタ単位、FRDl、FRD2  ダイオード単
位。 第1図 第2図 第 図 第 図
1 is an external view of one embodiment, (a) is a top view, (c) is a side view, M2 is an internal layout diagram of the present invention, and FIG. 3 is an internal equivalent circuit diagram of the present invention. Figure 4 is a wiring diagram of a power converter using the transistor Modineal of the present invention, and Figure 5 is a wiring diagram of a power converter using the transistor Modineal of the present invention.
FIG. A1. A2...Anode (positive) terminal, El, E
, emitter (negative) terminal, Tr, , Tr2-)
Transistor unit, FRD1, FRD2 diode unit. Figure 1 Figure 2 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1)複数のトランジスタチップとそれらのトランジスタ
のコレクタに直列接続された複数のダイオードチップと
が共通金属基板上に絶縁板を介して固着され、前記ダイ
オードチップから2本にまとめられたアノード主端子と
、前記トランジスタチップからは2本にまとめられたエ
ミッタ主端子とベース端子とがそれぞれ垂直に立ち上げ
られて絶縁容器に封入されるものにおいて、前記各アノ
ード主端子、各エミッタ主端子が互いに対称的な形状に
されると共に絶縁容器の外表面において互いに対称に配
置されていることを特徴とする逆阻止形トランジスタモ
ジュール。
1) A plurality of transistor chips and a plurality of diode chips connected in series to the collectors of these transistors are fixed on a common metal substrate via an insulating plate, and an anode main terminal which is combined into two from the diode chips and , in which two main emitter terminals and two base terminals are vertically raised from the transistor chip and sealed in an insulating container, and each anode main terminal and each emitter main terminal are symmetrical to each other. What is claimed is: 1. A reverse blocking transistor module, characterized in that the module is shaped like this and is arranged symmetrically to each other on the outer surface of an insulating container.
JP63285267A 1988-11-11 1988-11-11 Transistor module Expired - Lifetime JP2592116B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63285267A JP2592116B2 (en) 1988-11-11 1988-11-11 Transistor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63285267A JP2592116B2 (en) 1988-11-11 1988-11-11 Transistor module

Publications (2)

Publication Number Publication Date
JPH02130953A true JPH02130953A (en) 1990-05-18
JP2592116B2 JP2592116B2 (en) 1997-03-19

Family

ID=17689289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63285267A Expired - Lifetime JP2592116B2 (en) 1988-11-11 1988-11-11 Transistor module

Country Status (1)

Country Link
JP (1) JP2592116B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657874B2 (en) 2001-11-27 2003-12-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor converter circuit and circuit module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59152750U (en) * 1983-03-31 1984-10-13 富士電機株式会社 semiconductor equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59152750U (en) * 1983-03-31 1984-10-13 富士電機株式会社 semiconductor equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657874B2 (en) 2001-11-27 2003-12-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor converter circuit and circuit module

Also Published As

Publication number Publication date
JP2592116B2 (en) 1997-03-19

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