CN217159670U - Half-bridge circuit and switch layout structure thereof - Google Patents

Abstract

The embodiment of the application relates to the technical field of semiconductor devices, and discloses a half-bridge circuit and a switch layout structure thereof, wherein the half-bridge circuit comprises a substrate and at least one switch group, and the switch group comprises a first switch MOS (metal oxide semiconductor) transistor, a second switch MOS transistor and an input capacitor; the anode of the input capacitor is connected with the drain electrode of the first switch MOS tube, and the cathode of the input capacitor is connected with the source electrode of the second switch MOS tube; the source electrode of the first switch MOS tube is connected with the drain electrode of the second switch MOS tube; a first power path formed by connecting the source electrode of the first switch MOS tube, the drain electrode of the second switch MOS tube and the source electrode of the second switch MOS tube is a straight line; the drain electrode of the second switch MOS tube is positioned between the source electrode of the first switch MOS tube and the source electrode of the second switch MOS tube, and the input capacitor is positioned on one side of the drain electrode of the first switch MOS tube, which is far away from the source electrode of the first switch MOS tube. The switch layout structure of the half-bridge circuit in the embodiment of the application can shorten the path of the power circuit, reduce the parasitic inductance of the circuit and enable the half-bridge circuit to be safer and more reliable.

Description

Half-bridge circuit and switch layout structure thereof

Technical Field

The embodiment of the application relates to the field of semiconductor devices, in particular to a half-bridge circuit and a switch layout structure thereof.

Background

In power electronics applications, as silicon-based technologies approach their limits of development, design engineers have in recent years sought wide-bandgap technologies such as Gallium Nitride (GaN) devices to provide solutions for higher energy efficiency and higher switching frequencies. As a wide bandgap semiconductor device, GaN devices have many advantages such as low gate charge, capability of operating at frequencies up to 1MHz, and extremely low switching loss.

The GaN device is different from a traditional Metal oxide semiconductor field effect transistor (MOS) tube, because the GaN device has no PN junction, the GaN device has no body diode, Two-Dimensional Electron Gas (Two-Dimensional Electron Gas, 2 DEG) on the boundary surface of AlGaN/GaN can conduct current in the reverse direction, but has no reverse recovery charge, so that the GaN device is not problematic in reverse recovery, and is very suitable for hard switch application. However, GaN devices are generally more susceptible to over-voltage than silicon devices due to their limited avalanche capability.

Therefore, the switch layout structure of the half-bridge circuit appears to be especially critical for discrete GaN devices.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a half-bridge circuit and a switch layout structure thereof, which are used to shorten a path of a power loop, reduce a loop parasitic inductance, and make the half-bridge circuit safer and more reliable.

In order to solve the above technical problem, an embodiment of the present application provides a half-bridge circuit and a switch layout structure thereof, including: the switch group comprises a substrate and at least one switch group arranged on the substrate; the switch group comprises a first switch MOS tube, a second switch MOS tube and an input capacitor; the anode of the input capacitor is connected with the drain electrode of the first switch MOS tube, and the cathode of the input capacitor is connected with the source electrode of the second switch MOS tube; the source electrode of the first switch MOS tube is connected with the drain electrode of the second switch MOS tube; a first power path formed by connecting the source electrode of the first switch MOS tube, the drain electrode of the second switch MOS tube and the source electrode of the second switch MOS tube is a straight line; the drain electrode of the second switch MOS tube is positioned between the source electrode of the first switch MOS tube and the source electrode of the second switch MOS tube, and the input capacitor is positioned on one side of the drain electrode of the first switch MOS tube, which is far away from the source electrode of the first switch MOS tube.

In addition, the first power path is perpendicular to the second power path; the second power path is formed by connecting the anode of the input capacitor, the drain electrode of the first switch MOS tube and the source electrode of the first switch MOS tube.

In addition, a source electrode of the second switch MOS tube and a negative electrode of the input capacitor form a third power path; the first power path, the second power path and the third power path enclose a power loop; the power loop is rectangular or square in shape.

In addition, the switch layout structure of the half-bridge circuit further comprises a first isolation driver and a second isolation driver; the grid electrode of the first isolation driver is connected with the grid electrode of the first switch MOS tube; and the grid electrode of the second isolation driver is connected with the grid electrode of the second switching MOS tube.

In addition, the first switch MOS tube, the second switch MOS tube, the input capacitor, the first isolation driver and the second isolation driver are arranged on the same layer.

In addition, the switch layout structure of the half-bridge circuit further includes: the conducting layer is arranged on one side of the substrate, which is far away from the switch group; the substrate is provided with a plurality of through holes, and the conducting layer is connected with the first switch MOS tube, the second switch MOS tube and the input capacitor through the through holes.

In addition, the conductive layer includes a first conductive layer, a second conductive layer, and a third conductive layer; the first conducting layer is connected with the anode of the input capacitor and the drain electrode of the first switch MOS tube through the via hole; the second conducting layer is connected with the cathode of the input capacitor and the source electrode of the second switch MOS transistor through the through hole; the third conducting layer is connected with the source electrode of the first switch MOS tube and the drain electrode of the second switch MOS tube through the through hole.

In addition, the first switching MOS tube and the second switching MOS tube are gallium nitride devices or silicon carbide devices.

In addition, the substrate is one of a PCB (printed circuit board), an alumina substrate or an aluminum nitride substrate.

The embodiment of the application also provides a half-bridge circuit, which comprises the switch layout structure.

Compared with the prior art, the embodiment of the application mainly aims at the defect that the path of a power circuit in the switch layout structure of the half-bridge circuit in the prior art is long, the embodiment of the application provides the half-bridge circuit and the switch layout structure thereof, and the power path formed by connecting the source electrode of the first switch MOS tube, the drain electrode of the second switch MOS tube and the source electrode of the second switch MOS tube is a straight line by reasonably arranging the first switch MOS tube, the second switch MOS tube and the input capacitor on the substrate, so that the path of the power circuit is shortened, the parasitic inductance of the power circuit is reduced, the voltage stress applied to the switch MOS tube in the switching process is finally reduced, the voltage spike introduced by the parasitic inductance in the current conversion process is effectively reduced, and the safety and reliability performance of the switch MOS tube and the half-bridge circuit is ensured.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a circuit diagram of a half-bridge circuit;

FIG. 2 is a schematic diagram of a switch layout of a half-bridge circuit in the related art;

fig. 3 is a schematic diagram of a switch layout structure of a half-bridge circuit provided in the present application;

fig. 4 is a schematic cross-sectional view of a switch layout structure of a half-bridge circuit provided in the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following describes each embodiment of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in various embodiments of the present application in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

As known from the background art, the layout structure of the switches of the discrete GaN devices on the circuit board is particularly critical to ensure the safety performance of the half-bridge circuit.

At present, two GaN devices of a half-bridge topology are integrated on one chip in the related technology, so that the integration of the GaN devices is realized, and the parasitic inductance of packaging and layout can be effectively reduced; however, this integration scheme is only suitable for low voltage low current GaN devices. For high voltage and large current GaN devices, discrete devices are also usually used to build circuits.

The half-bridge circuit is built by adopting the discrete GaN devices, and the GaN devices are arranged on the circuit board side by side or in parallel, and are in a vertically symmetrical or horizontally symmetrical state. The fast switching speed of GaN devices results in high di/dt. Parasitic inductance inevitably exists in a power loop, when current changes rapidly, high peak overvoltage can be generated at two ends of a GaN device, circuit misoperation and electromagnetic interference (EMI) exceeding standards are caused at light, and breakdown and damage of the GaN device are caused at heavy. However, the above-mentioned structure of the GaN device with symmetrical arrangement does not consider the problem of shortening the power loop path, so that a high voltage spike is generated to act on the GaN device under the action of the parasitic inductance of the power loop, which may cause the GaN device to be damaged.

Fig. 1 is a circuit diagram of a half-bridge circuit. The switching MOS transistor Q1 and Q2 can be GaN devices, C _IN Is an input capacitance, V _sw Is a switching node. The power loop indicated by the arrow in fig. 1 is a strong magnetic field interference source, and because the GaN device has a fast switching speed and thus a high di/dt, a high voltage spike may be generated on the GaN device due to the parasitic inductance of the loop, which may cause damage to the GaN device. Therefore, the parasitic inductance of the power loop must be reduced as much as possible, and an effective way to reduce the parasitic inductance of the power loop is to shorten the path of the power loop.

The input capacitor C _IN Usually formed by several capacitors connected in parallel.

Fig. 2 is a schematic diagram showing a switch layout structure of a half-bridge circuit in the related art. FIG. 2 is a half-bridge circuitComprises two switch MOS tubes and three capacitors connected in parallel to form an input capacitor C _IN The case (1). In the related art, the switching MOS transistors are laid out by using a conventional printed circuit board layout (PCB layout) method, as shown in fig. 2, the switching MOS transistor Q1 and the switching MOS transistor Q2 are symmetrically arranged in an up-down manner, and the directions of the source S and drain D terminals of the switching MOS transistor Q1 and the switching MOS transistor Q2 are also the same. The power loop is the loop indicated by the arrow in fig. 2. As can be seen from fig. 2, the layout method of the switching MOS transistor Q1 and the switching MOS transistor Q2 that are vertically symmetrical has a longer path of the power loop.

It can be understood that when the switching MOS transistor Q1 and the switching MOS transistor Q2 adopt a left-right symmetrical layout structure, the problem of long power loop path still exists.

The input capacitor C _IN May be formed by three capacitors connected in parallel. The number of capacitors connected in parallel may also be other numbers, such as six, eight or ten.

To solve the technical problem of long power loop path, referring to fig. 3, an embodiment of the present application provides a switch layout structure of a half-bridge circuit, including: a substrate 1 and at least one switch set disposed on the substrate 1; the switch group comprises a first switch MOS tube Q1, a second switch MOS tube Q2 and an input capacitor C _IN Input capacitance C _IN The capacitor is formed by connecting three capacitors in parallel, and the capacitor can be a capacitor with the capacity of 22 muF as an example; input capacitance C _IN Is connected with the drain D of a first switch MOS tube Q1, and an input capacitor C _IN The negative electrode of the first switching MOS tube Q2 is connected with the source electrode S of the second switching MOS tube Q2; the source S of the first switching MOS transistor Q1 is connected with the drain D of the second switching MOS transistor Q2; a first power path formed by connecting the source S of the first switching MOS transistor Q1, the drain D of the second switching MOS transistor Q2 and the source S of the second switching MOS transistor Q2 is a straight line; the drain D of the second switching MOS transistor Q2 is positioned between the source S of the first switching MOS transistor Q1 and the source S of the second switching MOS transistor Q2, and the input capacitor C _IN The drain D of the first switch MOS transistor Q1 is located on a side far away from the source S of the first switch MOS transistor Q1.

It should be noted that, the embodiments of the present application provide a switching layout junction of a half-bridge circuitThe structure can include a plurality of switch groups, each switch group includes a first switch MOS tube Q1, a second switch MOS tube Q2 and an input capacitor C _IN . When the switch layout structure comprises a plurality of switch groups, the switch groups can be connected with the input capacitor C in parallel _IN And (4) connecting.

The following embodiments of the present application are described in detail with the switching layout structure of a half-bridge circuit including a switch group.

By comparing fig. 2 and fig. 3, it can be found that: in the switch layout structure of the half-bridge circuit provided in the embodiment of the present application, compared with fig. 2, the layout of the first switch MOS transistor Q1 and the second switch MOS transistor Q2 in fig. 3 is that the first switch MOS transistor Q1 and the second switch MOS transistor Q2 in the embodiment of the present application are both rotated by 180 degrees, and the final layout structure of the first switch MOS transistor Q1 and the second switch MOS transistor Q2 is not an up-down symmetrical structure in fig. 2. Referring to fig. 3 in particular, the direction of the source terminal of the source S of the second switching MOS transistor Q2 towards the drain terminal of the drain D of the second switching MOS transistor Q2 is rotated by 90 degrees compared to fig. 2 with respect to the first switching MOS transistor Q1, and it can be considered that the direction of the drain terminal of the drain D of the second switching MOS transistor Q2 towards the source terminal of the source S is rotated by 90 degrees compared to fig. 2.

As an example, as shown in fig. 2, the direction of the source terminal of the source S of the second switching MOS transistor Q2 toward the drain terminal is a first direction, and the first direction is parallel to the direction of the source terminal of the source S of the first switching MOS transistor Q1 toward the drain terminal of the drain D, and as can be seen from fig. 2, the first direction is a horizontal direction; alternatively, the direction of the drain terminal of the drain D of the second switching MOS transistor Q2 toward the source terminal of the source S may be the first direction, and the first direction is parallel to the direction of the drain terminal of the drain D of the first switching MOS transistor Q1 toward the source terminal of the source S. In the switch layout structure of the half-bridge circuit provided in the embodiment of the present application, as shown in fig. 3, a direction of the source terminal of the source S of the second switch MOS transistor Q2 toward the drain terminal of the drain D is a second direction, and is perpendicular to a direction of the source terminal of the source S of the first switch MOS transistor Q1 toward the drain terminal of the drain D, and the second direction is a vertical direction; alternatively, the direction of the drain terminal of the drain D of the second switching MOS transistor Q2 toward the source terminal of the source S is a second direction, and the second direction is perpendicular to the direction of the drain terminal of the drain D of the first switching MOS transistor Q1 toward the source terminal of the source S.

The first switching MOS transistor Q1, the second switching MOS transistor Q2, and the input capacitor C _IN The substrate 1 may be fixed by mounting or may be fixed on the substrate 1 by soldering.

In some embodiments, the substrate 1 is one of a Printed Circuit Board (PCB), an alumina substrate, or an aluminum nitride substrate. The substrate 1 is an alumina substrate or an aluminum nitride substrate, and can keep smaller power loop inductance and realize better electrical property and thermal property at the same time.

In some embodiments, the first power path is perpendicular to the second power path; the second power path is formed by input capacitor C _IN The positive electrode of the first switching MOS transistor Q1, the drain D of the first switching MOS transistor Q1, and the source S of the first switching MOS transistor Q2 are connected.

As shown in fig. 3, the first power path is line a, and the second power path is line B; the first power path line a is formed by connecting the source S of the first switch MOS transistor Q1, the drain D of the second switch MOS transistor Q2 and the source S of the second switch MOS transistor Q2, and the first power path line a is a straight line; the second power path is formed by input capacitor C _IN The positive electrode of the first switch MOS transistor Q1, the drain electrode D of the first switch MOS transistor Q1 and the source electrode S of the first switch MOS transistor Q2 are connected to form a first power path a line perpendicular to a second power path B line.

In some embodiments, the source S of the second switching MOS transistor Q2 and the input capacitor C _IN Forming a third power path; the first power path, the second power path and the third power path enclose a power loop; the power loop is rectangular or square in shape.

Referring to fig. 3, the third power path is a line C, and the line C of the third power path is formed by the source S of the second switching MOS transistor Q2 and the input capacitor C _IN Forming a negative electrode of (1); the third power path C is L-shaped, and the third power path C, the first power path a and the second power path B enclose a power loop, which is rectangular (the area of the arrow in fig. 3 connecting the lines). From FIG. 3It can be seen that, in the switch layout structure of the half-bridge circuit provided in the embodiment of the present application, compared with the switch layout structure of the conventional half-bridge circuit in fig. 2, the power loop path is shortened a lot, and the switch layout structure is more compact as a whole. The switch layout structure of the half-bridge circuit provided by the embodiment of the application effectively reduces the voltage spike introduced by the parasitic inductance in the current conversion process by shortening the power loop path, thereby ensuring the safety and reliability of the switch MOS tube.

In some embodiments, the switching topology of the half-bridge circuit further includes a first isolated driver and a second isolated driver; the grid electrode of the first isolation driver is connected with the grid electrode of the first switch MOS tube; and the grid electrode of the second isolation driver is connected with the grid electrode of the second switching MOS tube. Specifically, the gate of the first isolation driver is connected to the gate of the first switching MOS transistor Q1 by Kelvin (Kelvin) connection, and similarly, the gate of the second isolation driver is connected to the gate of the second switching MOS transistor Q2 by Kelvin (Kelvin) connection, and the gates of the first switching MOS transistor Q1 and the second switching MOS transistor Q2 are driven to perform gate driving, and the current of the output terminal drain D is controlled by the voltage applied to the gate of the input terminal of the switching MOS transistor.

In some embodiments, the first switching MOS transistor Q1, the second switching MOS transistor Q2, and the input capacitor C _IN The first isolation driver and the second isolation driver may be disposed in the same layer.

As shown in fig. 4, a first switching MOS transistor Q1, a second switching MOS transistor Q2, and an input capacitor C _IN The first isolation driver and the second isolation driver can be arranged on the same layer of the substrate 1, so that the switch layout structure is more compact, and heat conduction and heat dissipation are facilitated.

It can be understood that the first switching MOS transistor Q1, the second switching MOS transistor Q2, and the input capacitor C _IN The first isolation driver and the second isolation driver may be disposed in different layers, and on the substrate 1, the first switching MOS transistor Q1, the second switching MOS transistor Q2, and the input capacitor C may be disposed in different layers _IN Can be arranged on the substrate 1, the first isolation driver and the second isolation driver are arranged on other layers, and the first isolation driver and the second isolation driver are arranged on the other layersThe isolation driver is respectively connected with the first switch MOS tube Q1 and the second switch MOS tube Q2 through via holes.

In some embodiments, the first switching MOS transistor Q1, the second switching MOS transistor Q2 and the input capacitor C _IN Can set up the apron 4 that is used for encapsulating the device in the one side of keeping away from base plate 1, be equipped with a plurality of through-holes on the apron 4, pour into sealed glue 5 through the through-hole and in order to fill up the space between device and the apron 4 in order to carry out the embedment to the device, guarantee the stability of embedment back device.

In some embodiments, the switching layout structure of the half-bridge circuit further includes: the conducting layer 2 is arranged on one side of the substrate 1 far away from the switch group; a plurality of through holes 3 are arranged on the substrate 1, and the conducting layer 2 passes through the through holes 3 and is connected with the first switch MOS tube Q1, the second switch MOS tube Q2 and the input capacitor C _IN And (4) connecting.

Referring to fig. 4, the conductive layer 2 is disposed on a side of the substrate 1 away from the first switching MOS, the conductive layer 2 connects the source of the first switching MOS Q1 in the switch group with the drain of the first switching MOS Q1, and the source of the second switching MOS Q2 with the input capacitor C _IN And the negative pole of the input capacitor C _IN Is connected to the drain of the first switching MOS transistor Q1.

In some embodiments, the material of the conductive layer 2 is a conductive metal material such as copper, gold, silver, platinum, or the like. Preferably, the conductive layer 2 is usually made of copper foil material to form a copper clad laminate, and is formed by arranging a first switching MOS transistor Q1, a second switching MOS transistor Q2 and an input capacitor C _IN Copper-clad plates are respectively arranged in the regions to realize the first switch MOS tube Q1, the second switch MOS tube Q2 and the input capacitor C _IN And (4) connecting.

Referring to fig. 3, a plurality of via holes 3 are formed on the substrate 1, and the conductive layer 2 passes through the via holes and the first switching MOS transistor Q1, the second switching MOS transistor Q2 and the input capacitor C _IN And (4) connecting.

In some embodiments, the conductive layer 2 includes a first conductive layer 21, a second conductive layer 22, and a third conductive layer 23; the first conductive layer 21 passes through the via hole 3 and the input capacitor C _IN The positive electrode of the first switch MOS tube Q1 is connected with the drain electrode D of the first switch MOS tube Q1; the second conductive layer 22 passes through the via 3 and the input capacitor C _IN The negative electrode of the second switching MOS tube Q2 is connected with the source electrode S of the second switching MOS tube Q2; the third conductive layer 23 is connected to the source S of the first switching MOS transistor Q1 and the drain D of the second switching MOS transistor Q2 through the via 3.

As shown in fig. 3, conducting layer 2 can be the copper-clad plate, can cover copper by a large scale according to the area size of base plate 1, simultaneously offering a large amount of via holes 3, be favorable to the heat dissipation of the device that generates heat, like first switch MOS pipe Q1 and second switch MOS pipe Q2 for the great device of heat dissipation, so set up the heat that gives off first switch MOS pipe Q1 and second switch MOS pipe Q2 and conduct so that the heat in time gives off through via holes 3.

In some embodiments, the first switching MOS transistor Q1 and the second switching MOS transistor Q2 are gallium nitride (GaN) devices or silicon carbide devices.

In some embodiments, when the first switching MOS transistor Q1 and the second switching MOS transistor Q2 are both gallium nitride (GaN) devices, the first switching MOS transistor Q1, the second switching MOS transistor Q2 and the input capacitor C _IN The connections form a half bridge circuit as shown in fig. 1.

The embodiment of the application also provides a half-bridge circuit, which comprises the switch layout structure.

By the technical scheme, the embodiment of the application provides a switch layout structure of a half-bridge circuit, which mainly aims at the defect that a power loop path is longer in the switch layout structure of the half-bridge circuit in the prior art, and reduces parasitic inductance of the power loop by shortening the power loop path. The first switch MOS tube Q1, the second switch MOS tube Q2 and the input capacitor C are reasonably arranged in the embodiment of the application _IN The power path formed by connecting the source electrode of the first switch MOS tube Q1, the drain electrode of the second switch MOS tube Q2 and the source electrode of the second switch MOS tube Q2 is a straight line, so that the path of the power loop is shortened, the parasitic inductance of the power loop is reduced, and the voltage stress applied to the switch MOS tube in the switching process is finally reduced, thereby effectively reducing the voltage spike introduced by the parasitic inductance in the commutation process, and ensuring the safety and reliability of the switch MOS tube and the half-bridge circuit.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.

Claims (10)

1. A switching topology for a half-bridge circuit, comprising:

a substrate;

at least one switch set disposed on the substrate; the switch group comprises a first switch MOS tube, a second switch MOS tube and an input capacitor; the anode of the input capacitor is connected with the drain electrode of the first switch MOS tube, and the cathode of the input capacitor is connected with the source electrode of the second switch MOS tube; the source electrode of the first switch MOS tube is connected with the drain electrode of the second switch MOS tube;

a first power path formed by connecting the source electrode of the first switch MOS tube, the drain electrode of the second switch MOS tube and the source electrode of the second switch MOS tube is a straight line; the drain electrode of the second switch MOS tube is positioned between the source electrode of the first switch MOS tube and the source electrode of the second switch MOS tube, and the input capacitor is positioned on one side, far away from the source electrode of the first switch MOS tube, of the drain electrode of the first switch MOS tube.

2. The switching topology of a half-bridge circuit of claim 1, wherein the first power path is perpendicular to the second power path;

the second power path is formed by connecting the anode of the input capacitor, the drain electrode of the first switch MOS tube and the source electrode of the first switch MOS tube.

3. The switching topology of the half-bridge circuit of claim 2, wherein the source of the second switching MOS transistor and the negative terminal of the input capacitor form a third power path;

the first power path, the second power path, and the third power path enclose a power loop;

the power loop is rectangular or square in shape.

4. The switching topology of a half-bridge circuit of claim 1, further comprising a first isolated driver and a second isolated driver;

the grid electrode of the first isolation driver is connected with the grid electrode of the first switch MOS tube; and the grid electrode of the second isolation driver is connected with the grid electrode of the second switch MOS tube.

5. The switching topology of a half-bridge circuit of claim 4, wherein the first switching MOS transistor, the second switching MOS transistor, the input capacitor, the first isolation driver and the second isolation driver are disposed in a same layer.

6. The switching topology of a half-bridge circuit of claim 1, further comprising: the conducting layer is arranged on one side, far away from the switch group, of the substrate;

the substrate is provided with a plurality of through holes, and the conducting layer is connected with the first switch MOS tube, the second switch MOS tube and the input capacitor through the through holes.

7. The switch layout structure of the half-bridge circuit of claim 6, wherein the conductive layers comprise a first conductive layer, a second conductive layer, and a third conductive layer;

the first conducting layer is connected with the anode of the input capacitor and the drain electrode of the first switch MOS tube through a via hole; the second conducting layer is connected with the negative electrode of the input capacitor and the source electrode of the second switch MOS tube through a through hole; the third conducting layer is connected with the source electrode of the first switch MOS tube and the drain electrode of the second switch MOS tube through via holes.

8. The switching topology of a half-bridge circuit of any one of claims 1 to 7, wherein the first and second switching MOS transistors are gallium nitride devices or silicon carbide devices.

9. The switch layout structure of a half-bridge circuit of any one of claims 1 to 7, wherein the substrate is one of a PCB board, an alumina substrate or an aluminum nitride substrate.

10. A half bridge circuit comprising a switch arrangement according to any one of claims 1 to 9.

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