JPH02130949A - Manufacture of lead frame and semiconductor device - Google Patents
Manufacture of lead frame and semiconductor deviceInfo
- Publication number
- JPH02130949A JPH02130949A JP63285244A JP28524488A JPH02130949A JP H02130949 A JPH02130949 A JP H02130949A JP 63285244 A JP63285244 A JP 63285244A JP 28524488 A JP28524488 A JP 28524488A JP H02130949 A JPH02130949 A JP H02130949A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- lead frame
- purity
- tip
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010949 copper Substances 0.000 claims abstract description 43
- 229910052802 copper Inorganic materials 0.000 claims abstract description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000004544 sputter deposition Methods 0.000 claims abstract description 10
- 238000007740 vapor deposition Methods 0.000 claims abstract description 7
- 238000007789 sealing Methods 0.000 claims abstract description 4
- 239000011347 resin Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 238000007747 plating Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 229910000510 noble metal Inorganic materials 0.000 description 4
- 239000010970 precious metal Substances 0.000 description 4
- 150000001879 copper Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Physical Vapour Deposition (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、リードフレームおよびこれを用いた半導体装
置の製造方法に係り、特にその製造コストの低減に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a lead frame and a method for manufacturing a semiconductor device using the lead frame, and particularly relates to reducing the manufacturing cost thereof.
（従来の技術）
例えば通常のＩＣは、第２図に示すように、リードフレ
ーム１のダイパッド２に、半導体素子３を固着し、この
半導体素子３のポンディングパッドとリードフレームの
インナーリード４とを金線あるいはアルミ線のボンディ
ングワイヤ５によって結線し、更にこれらを樹脂６で封
止することにより製造されている。(Prior Art) For example, in a normal IC, as shown in FIG. 2, a semiconductor element 3 is fixed to a die pad 2 of a lead frame 1, and a bonding pad of this semiconductor element 3 and an inner lead 4 of the lead frame are connected. are connected by bonding wires 5 made of gold or aluminum wires, and further sealed with resin 6.
ここで用いられるリードフレームは、第３図に１例を示
す如く、半導体素子を搭載するためのダイパッド２と、
先端が該ダイパッドをとり囲むように延在せしめられた
インナーリード４と、該インナーリードとほぼ直交する
方向に延びこれらインナーリードを一体的に支持するタ
イバー７と、該タイバーの外側に前記各インナーリード
に接続するように配設せしめられたアウターリード８と
ダイパッド２を支持するサポートパー９とから構成され
ている。The lead frame used here includes a die pad 2 for mounting a semiconductor element, as shown in an example in FIG.
An inner lead 4 whose tip extends so as to surround the die pad, a tie bar 7 extending in a direction substantially perpendicular to the inner lead and integrally supporting these inner leads, and each inner lead on the outside of the tie bar. It is composed of an outer lead 8 arranged to be connected to the leads and a support par 9 that supports the die pad 2.
そして、グイボンドやワイヤボンドの密着性をより確実
にすべく、このインナーリードの先端およびダイパッド
には、貴金属メツキが施されている。In order to further ensure the adhesion of the wire bond and the wire bond, the tips of the inner leads and the die pad are plated with a precious metal.
しかしながら、貴金属の使用によりリードフレームの製
造コストが上昇し、特に大容量メモリに用いられるリー
ドフレームでは、チップサイズに合わせ、極めて広い面
積のダイパッドを有するため貴金属の使用量が増大し、
コストの高騰が深刻な問題となっていた。However, the use of precious metals increases the manufacturing cost of lead frames, and lead frames used for large-capacity memories in particular have extremely wide die pads to match the chip size, which increases the amount of precious metals used.
Rising costs were becoming a serious problem.
また、ボンディングワイヤについても一部アルミニウム
線が使用されてはいるものの、はとんどが金線を使用し
ており、これも価格高騰の大きな原因となっていた。Furthermore, although some aluminum wires are used for the bonding wires, most of them are gold wires, which was also a major cause of the price hike.
（発明が解決しようとする課題）
このように、貴金属の使用によるリードフレームの！％
Ｉ造コストの高騰が深刻な問題となっている。(Problem to be solved by the invention) In this way, lead frames made of precious metals! %
The soaring cost of I-manufacturing has become a serious problem.
本発明は、前記実情に鑑みてなされたもので、低コスト
で信頼性の高いリードフレームを提供することを目的と
する。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a lead frame that is low in cost and highly reliable.
（課題を解決するための手段）
そこで本発明では、インナーリード先端のワイヤボンデ
ィング領域に、スパッタリング法あるいは蒸着法により
純度９９．９９９％以上の銅（Ｃｕ）層を形成するよう
にしている。(Means for Solving the Problems) Therefore, in the present invention, a copper (Cu) layer with a purity of 99.999% or more is formed in the wire bonding region at the tip of the inner lead by sputtering or vapor deposition.
また、本発明では、インナーリード先端のワイヤボンデ
ィング領域に、スパッタリング法あるいは蒸着法により
純度９９．９９９％以上の銅（Ｃｕ）層を形成すると共
に、チップ搭載後、純度９９゜９９９％以上の銅ワイヤ
でワイヤボンディングを行うようにしている。Furthermore, in the present invention, a copper (Cu) layer with a purity of 99.999% or more is formed in the wire bonding area at the tip of the inner lead by sputtering or vapor deposition, and after mounting the chip, a copper (Cu) layer with a purity of 99.999% or more is formed on the wire bonding area at the tip of the inner lead. I try to do wire bonding with wire.
（作用）
本発明は、最近実用化が可能となり、注目されている純
度９９．９９９％以上の銅に着目してなされたもので、
これをターゲットとして用いて、スパッタリング法ある
いは蒸着法等を採用゛すれば純度９９．９９９％以上の
銅層の形成が可能となることを発見した。(Function) The present invention was made with a focus on copper with a purity of 99.999% or more, which has recently become practical and is attracting attention.
It has been discovered that by using this as a target and employing a sputtering method, a vapor deposition method, etc., it is possible to form a copper layer with a purity of 99.999% or more.
この銅層をリードフレームで従来行われていた貴金属メ
ツキ層に替えて用いることによって、極めて低コストで
、ワイヤボンディング性の高いリードフレームを得るこ
とが可能となる。By using this copper layer in place of the noble metal plating layer conventionally used in lead frames, it becomes possible to obtain lead frames with high wire bondability at extremely low cost.
また、この銅層を貴金属メツキ層に替えて用いることに
よって、ボンディングワイヤをも銅とすることができ低
コストで信頼性の高い半導体装置を得ることが可能とな
る。Furthermore, by using this copper layer in place of the noble metal plating layer, the bonding wire can also be made of copper, making it possible to obtain a highly reliable semiconductor device at low cost.
（実施例）
以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。(Example) Hereinafter, examples of the present invention will be described in detail with reference to the drawings.
第１図（ａ）乃至第１図（ｅ）は、本発明実施例のリー
ドフレームの製造工程を示す図である。FIG. 1(a) to FIG. 1(e) are diagrams showing the manufacturing process of a lead frame according to an embodiment of the present invention.
まず、第１図（ａ）に示すように、スタンピング法によ
り、銅からなる帯状材料を加工し、第３図に示したよう
なリードフレーム１を形成する。First, as shown in FIG. 1(a), a strip-shaped material made of copper is processed by a stamping method to form a lead frame 1 as shown in FIG. 3.
次いで、第１図（ｂ）に示すように、コイニング処理を
行い、インナーリード４先端部の平坦幅を確保したのち
、スパッタリング法により、ダイパッド２および、各イ
ンナ−リード４先端部のボンディングエリアに純度９９
．９９９％以上の銅（Ｃｕ）層１０を形成する。このと
き、ソースとして、純度９９．９９９％以上の銅（Ｃｕ
）を用いる。Next, as shown in FIG. 1(b), a coining process is performed to ensure a flat width at the tips of the inner leads 4, and then the die pad 2 and the bonding area at the tips of each inner lead 4 are coated by sputtering. Purity 99
．． A copper (Cu) layer 10 of 999% or more is formed. At this time, copper (Cu) with a purity of 99.999% or more is used as a source.
) is used.
この後、第１図（Ｃ）に示すように、グイパッド２上に
半導体素子チップ３を固着し、各インナ−リード４先端
部のボンディングエリアと半導体素子チップ３のポンデ
ィングパッドとをワイヤボンディング法により純度９９
．９９９％以上の銅からなるワイヤ５を介して結線する
。After this, as shown in FIG. 1(C), the semiconductor element chip 3 is fixed on the guide pad 2, and the bonding area at the tip of each inner lead 4 and the bonding pad of the semiconductor element chip 3 are bonded using wire bonding. Purity 99
．． Connection is made via a wire 5 made of 999% or more copper.
そして、第１図（ｄ）に示すように、樹脂封止を行い、
アウターリード先端部を残して該リードフレーム槽体を
封止する。Then, as shown in FIG. 1(d), resin sealing is performed,
The lead frame tank is sealed leaving the outer lead tips intact.
最後に、タイバー７を切除し、アウターリード８の先端
を分離すると共に、所望の方向に折り曲げ成型し、第１
図（ｅ）に示すように、半導体装置が完成する。Finally, the tie bar 7 is cut out, the tip of the outer lead 8 is separated, and the tip is bent in a desired direction to form the first
As shown in Figure (e), the semiconductor device is completed.
このようにして形成されたリードフレームによれば、金
メツキなどの貴金属メツキが不要となり、極めて低コス
トとなる。そしてこのようにして形成される銅層は、電
気抵抗が少なくビッカース硬度４２以下、伸び３０％以
上とＡｕに近い性質を持っているため、ボンディングワ
イヤとの密着性が良好であり、極めて信頼性の高いもの
となる。According to the lead frame formed in this manner, noble metal plating such as gold plating is not required, resulting in extremely low cost. The copper layer formed in this way has properties similar to Au, such as low electrical resistance, Vickers hardness of 42 or less, and elongation of 30% or more, so it has good adhesion to the bonding wire and is extremely reliable. The value will be high.
さらに、ボンディングワイヤをも銅で構成することがで
きるため、ボンディングワイヤのコストが大幅に低減さ
れ、製造コストが節減される。Furthermore, since the bonding wire can also be made of copper, the cost of the bonding wire is significantly reduced and manufacturing costs are saved.
なお、前記実施例では、ダイパッド上にも銅層を形成す
るようにしたが、半導体チップを固着するに際し、ポリ
イミド樹脂などによって固着するようにすれば、銅層を
形成する必要はなく、さらに経費の節減をはかることが
できる。In the above embodiment, a copper layer is also formed on the die pad, but if the semiconductor chip is fixed using polyimide resin or the like, there is no need to form a copper layer, and the cost can be further reduced. It is possible to save money.
また、インナーリード先端への銅層の形成をスパッタリ
ング法によって行うようにしたが、真空蒸着法や電子ビ
ーム蒸着法など他の方法でも有効である。Further, although the copper layer is formed on the tips of the inner leads by sputtering, other methods such as vacuum evaporation or electron beam evaporation may also be effective.
しかし、メツキ法では不純物の混入を避けるこができず
銅を高純度に保つことが不可能である。However, the Metsuki method cannot avoid contamination with impurities, making it impossible to maintain high purity copper.
以上説明してきたように、本発明の方法によれば、イン
ナーリード先端のワイヤボンディング領域に、純度９９
．９９９％以上の銅をターゲツトとして用いて、スパッ
タリング法あるいは蒸着法等により、純度９９．９９９
％以上の銅層を形成するようにしているため、低コスト
で信頼性の高いリードフレームを得ることが可能となる
。As explained above, according to the method of the present invention, the wire bonding area at the tip of the inner lead has a purity of 99%.
．． Using 999% or more copper as a target, the purity is 99.999 by sputtering method or vapor deposition method.
% or more of the copper layer, it is possible to obtain a highly reliable lead frame at low cost.
また、この銅層を貴金属メツキ層に替えて用いることに
よって、ボンディングワイヤをも銅とすることができ、
さらに低コストで信頼性の高い半導体装置を得ることが
可能となる。Furthermore, by using this copper layer instead of the noble metal plating layer, the bonding wire can also be made of copper.
Furthermore, it becomes possible to obtain a highly reliable semiconductor device at low cost.
第１図（ａ）乃至第１図（ｅ）は、本発明実施例のリー
ドフレームの製造工程を示す図、第２図は、従来の半導
体装置のリードフレームを示す図、第３図は、半導体装
！の実装例を示す図である。
１・・・リードフレーム、２・・・ダイパッド、３・・
・半導体素子、４・・・インナーリード、５・・・ボン
ディングワイヤ、６・・・樹脂、７・・・タイバー、８
・・・アウターリード、９・・・サポートパー −１０
・・・銅層。
第１図（ｂン
第
図 （Ｃン
第
図（ｄ）
第
図（ｅ）
第２図
第３図1(a) to 1(e) are diagrams showing the manufacturing process of a lead frame according to an embodiment of the present invention, FIG. 2 is a diagram showing a lead frame of a conventional semiconductor device, and FIG. Semiconductor equipment! It is a figure showing an example of implementation. 1...Lead frame, 2...Die pad, 3...
- Semiconductor element, 4... Inner lead, 5... Bonding wire, 6... Resin, 7... Tie bar, 8
...Outer lead, 9...Support par -10
...Copper layer. Figure 1 (Figure B (Figure C) (D) Figure (e) Figure 2 Figure 3
Claims (2)
のインナーリードを有するリードフレームの製造方法に
おいて、 リードフレームの形状をなすように、実質 的に銅からなる板状体を形状加工する工程と、インナー
リード先端付近のワイヤボンディ ング領域に、純度９９．９９９％以上の銅（Ｃｕ）をソ
ースとして、スパッタリング法あるいは蒸着法により純
度９９．９９９％以上の銅（Ｃｕ）層を形成する工程を
含むことを特徴とするリードフレームの製造方法。(1) A method for manufacturing a lead frame having a plurality of inner leads extending radially from the vicinity of a semiconductor element mounting portion, including the step of processing a plate-like body substantially made of copper into the shape of a lead frame; Includes a step of forming a copper (Cu) layer with a purity of 99.999% or more in the wire bonding region near the tip of the inner lead by sputtering or vapor deposition using copper (Cu) with a purity of 99.999% or more as a source. A method for manufacturing a lead frame characterized by:
のインナーリードを有するリードフレーム上に半導体素
子を実装してなる半導体装置の製造方法において、 リードフレームの形状をなすように、実質 的に銅からなる板状体を形状加工する工程と、インナー
リード先端付近のワイヤボンディ ング領域に純度９９．９９９％以上の銅（Ｃｕ）をソー
スとして、スパッタリング法あるいは蒸着法；より純度
９９．９９９％以上の銅（Ｃｕ）層を形成する工程と、 半導体素子搭載部分上に半導体素子を固着 する工程と、 前記半導体素子とインナーリードとの間を 純度９９．９９９％以上の銅（Ｃｕ）からなるボンディ
ングワイヤを介して電気的に接続するワイヤボンディン
グ工程と、 前記半導体素子とインナーリード先端部を 覆うように封止する封止工程とを含むことを特徴とする
半導体装置の製造方法。(2) In a method for manufacturing a semiconductor device in which a semiconductor element is mounted on a lead frame having a plurality of inner leads extending radially from the vicinity of the semiconductor element mounting part, the semiconductor device is made of substantially copper so as to form the shape of the lead frame. The process of processing the shape of a plate-shaped body, and sputtering or vapor deposition using copper (Cu) with a purity of 99.999% or more as a source in the wire bonding area near the tip of the inner lead; copper with a purity of 99.999% or more A process of forming a (Cu) layer, a process of fixing a semiconductor element on the semiconductor element mounting part, and a process of connecting a bonding wire made of copper (Cu) with a purity of 99.999% or more between the semiconductor element and the inner lead. A method for manufacturing a semiconductor device, the method comprising: a wire bonding step for electrically connecting the semiconductor element and the tip end portion of the inner lead; and a sealing step for covering and sealing the semiconductor element and the tip of the inner lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63285244A JPH02130949A (en) | 1988-11-11 | 1988-11-11 | Manufacture of lead frame and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63285244A JPH02130949A (en) | 1988-11-11 | 1988-11-11 | Manufacture of lead frame and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02130949A true JPH02130949A (en) | 1990-05-18 |
Family
ID=17688979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63285244A Pending JPH02130949A (en) | 1988-11-11 | 1988-11-11 | Manufacture of lead frame and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02130949A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1060632A (en) * | 1996-08-16 | 1998-03-03 | Dowa Mining Co Ltd | Sputtering target, its production, and semiconductor device |
-
1988
- 1988-11-11 JP JP63285244A patent/JPH02130949A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1060632A (en) * | 1996-08-16 | 1998-03-03 | Dowa Mining Co Ltd | Sputtering target, its production, and semiconductor device |
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