JPH02129915A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent development of peeling and spikes of metal silicide of high melting point as a contact section by applying a process to eliminate metal silicide of high melding point at a contact section and a process to introduce impurity ions from an opened contact hole. CONSTITUTION:When a contact is opened, excessive etching is performed to also eliminate metal silicide 5b of high melting point at a contact hole. At this time, etching proceeds also at a silicon substrate 1 and diffusion layer junction becomes shallow. Therefore, if a wiring metal 8 is applied to enable alloying reaction, spike develops. Impurity is introduced from a contact hole and a diffusion layer 3d of the contact section is selectively made rather deep to avoid spike. Peeling and spikes of metal silicide of high melting point which develop during contact hole glass flow can be thereby prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a high-speed fine MO3 semiconductor device.

[Summary of the invention]

In the present invention, in order to prevent peeling of the high melting point metal silicide at the contact portion, not only the insulating film but also the high melting point metal silicide is removed at the same time by performing excessive etching when opening the contact. be. At this time, the silicon substrate is also etched, so if the diffusion layer is of the same conductivity type as the silicon substrate, there will be no problem, but if the diffusion layer is of the opposite conductivity type to the silicon substrate, the depth of the diffusion layer will be shallow. However, when aluminum is used as the wiring metal, a so-called spike problem occurs.

Further, in the present invention, in order to prevent spikes, an impurity having the same conductivity type as that of the diffusion layer is introduced through the contact hole, and a slightly deeper diffusion layer is provided only in the contact hole.

[Conventional technology]

FIGS. 2(a) and 2(b) show a method of manufacturing an MO8 semiconductor device using conventional polycide as a gate electrode material. - As an example, a case using a CMO3 semiconductor will be explained.

FIG. 2(a) shows a diagram in which a contact hole 7 is opened in an interlayer insulating film to obtain an electrical connection between a wiring metal and a polycide or silicon substrate 1 made of high melting point metal silicide 5b and polycrystalline silicon 5a. There is. At this time, as the high melting point metal silicide, for example, tungsten silicide,
Or molybdenum silicide can be mentioned. The shape of the contact is very vertical because the hole is formed by dry etching immediately after etching. Therefore, if left as is, the step coverage of the wiring metal to be deposited later will be extremely poor, which will cause a decrease in yield, so it is necessary to improve the shape of the contact. Currently, a method commonly used is CVD (Chemica, 17 Vapor D
PSG film, which is an oxide film, or BPS, which is a CVD oxide film containing a high concentration of phosphorus and boron.
After opening a contact hole using a G film, the temperature is 850℃~9
There is a so-called glass flow process in which contact holes are rounded by heat treatment at a temperature of about 50° C. for 15 to 60 minutes. Rather than performing this heat treatment in a non-oxidizing atmosphere,
It is well known that the flow effect is better when carried out in an oxidizing atmosphere. When polycide is used as the gate electrode, a silicide peeling problem occurs in which the high melting point metal silicide 5b is peeled off from the polycrystalline silicon 5a in this glass flow process. FIG. 2(b) shows this situation. A characteristic of silicide is that it is resistant to high-temperature, long-term heat treatment in a non-oxidizing atmosphere, but is extremely vulnerable to high-temperature heat treatment in an oxidizing atmosphere, which exposes the silicide. The problem of silicide peeling occurs during the hole glass flow process.

[Problem to be solved by the invention]

If the problem of high melting point metal silicide peeling occurs in the contact hole, the electrical bond between the wiring metal and the polycide becomes unstable, increasing the contact resistance and eventually causing the MO
3. This causes a decrease in the yield of semiconductor devices. Of course, this is also a big problem from the viewpoint of reliability.

[Means to solve the problem]

In order to solve the above problems, the present invention removes high melting point metal silicide in the contact hole by excessively etching the contact hole. At this time, the silicon substrate is also etched, and the diffusion layer junction becomes shallow, so that when a wiring metal is later covered and an alloying reaction is performed, a so-called spike problem occurs. In order to solve this spike problem, the present invention introduces impurities through the contact hole and selectively deepens the diffusion layer in the contact portion.

[Effect]

The problem of silicide peeling does not occur even in the glass flow process in which the shape of the contact hole is improved by removing the high melting point metal silicide in the contact hole when forming the contact hole. The problem of spikes after wiring metal deposition caused by a shallower diffusion layer can be solved by introducing impurities through the contact hole and selectively deepening the diffusion bond at the contact portion.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. 1st
Figure (a) shows a state in which a contact hole necessary for establishing an electrical connection between the wiring metal and the polycide or diffusion layer 3 is opened in the interlayer insulating film 6 by dry etching. At this time, by performing excessive dry etching, the high melting point metal silicide 5b in the contact portion is removed. In practice, for example, if a BPSG film, which is a CVD oxide film containing boron and phosphorus at a high concentration, is used as an interlayer insulating film, and tungsten silicide is used as a high-melting point metal silicide, dry etching is performed using C2F6 and C2F6 as reactive gases.
By performing etching in plasma using a mixed gas of HF and continuing to perform excessive etching even after the end point has been detected, the shape shown in FIG. 1(a) can be obtained. At this time, when etching is performed using the above reaction gas, the etch rate ratio between the silicon substrate and the silicide is about 1:2, so for example, the tungsten silicide film thickness is reduced to 1500 Å.
If it is ~2,500 people, the diffusion layer 3 in the silicon substrate 1 will be about 750A~1,250 people shallow. When the junction becomes shallow and aluminum is used as the wiring metal, a so-called spike phenomenon occurs as shown in Figure 3 after the heat treatment that promotes the alloying reaction to ensure electrical bonding between the wiring metal and the diffusion layer occurs. . That is, aluminum diffuses and penetrates the diffusion layer, causing an electrical short circuit with the silicon substrate, resulting in a defect. Therefore, the problem of spikes can be solved by introducing impurities of the same conductivity type as the diffusion layer into the silicon substrate or well through the contact hole to make the junction at the contact portion a little deeper. In actuality, a photolithography process is used to open the contact area between the substrate and the conductive type diffusion layer 3b, and other contact areas are patterned so as to be covered with photoresist.
will be introduced. At this time, for example, the conductivity type of the silicon substrate 1 is P.
When it is a mold, it is sufficient to introduce donor phosphorus or arsenic as an impurity. This situation is shown in FIG. 1(b). Next, in the opposite direction, the contact part of the diffusion layer 3a of the same conductivity type as the substrate is opened using a photolithography process, the other contact parts are patterned so as to be covered with photoresist, and the impurity 3d is added using ion implantation technology. Introduce it through the contact hole. At this time, for example, the conductivity type of the silicon substrate 1 is P.
If it is a type, boron or BF2, which is an acceptor impurity, may be ion-implanted as the impurity. This situation is shown in FIG. 1(c). Next, a heat treatment was performed in an oxidizing atmosphere at 850 DEG C. to 950 DEG C., which also served as a contact hole glass flow of the BPSG film and activation of impurities introduced through the contact hole, as shown in FIG. 1(d). At this time, since the refractory metal silicide in the contact area has already been removed, no peeling occurs at all. Next, as shown in FIG. 1(e), a wiring metal 8 is deposited after undergoing hydrofluoric acid treatment.

〔Effect of the invention〕

As explained above, the present invention solves the problem of peeling off of high melting point metal silicide that occurs during contact hole glass flow by simultaneously removing not only the interlayer insulating film but also the high melting point metal silicide in the contact area during contact etching. I was able to resolve the issue. Electrical coupling with the wiring metal will be made with the polycrystalline silicon under the polycide layer, but the polycrystalline silicon will have a thickness of 1019 to 102 degrees/cm3.
Good contact characteristics can be obtained by mixing phosphorus. Since the refractory metal silicide is removed only from the contact area, the advantage of low resistance, which is one of the reasons for using a polycide gate, remains intact. The problem of spikes caused by this method can be overcome by introducing impurities through the contact hole and providing a slightly deeper junction in the contact lower diffusion layer. In the embodiment, an impurity of a conductivity type opposite to that of the silicon substrate is introduced first, and then an impurity of the same conductivity type as that of the silicon substrate is introduced, but this order may be reversed.

FIG.

１　・　・・ 2・・・・ a13 4・1 5a・・ 5b・・ 61・ 7・・・・ 8・・・・ ・Silicon substrate jar well b, 3c, 3d ・Diffusion layer ・Field oxide film ・Polycrystalline silicon ・High melting point metal silicide ・Interlayer insulation film ·contact ・Wiring metal that's all

[Brief explanation of drawings]

1(a) to (e) are step-by-step cross-sectional views of a method for manufacturing a MOS semiconductor device according to the present invention, and FIGS. 2(a) and (b) are step-by-step cross-sectional views of a conventional method for manufacturing a MOS semiconductor device. , 3rd
The figure shows the conventional MOS of semiconductor device spa applicant Seiko Electronic Industries Co., Ltd. Patent attorney Keinosuke Hayashi!
l - 1 bottle @ I / 1 Manufacturing method 5 Odor presentation 2゛ Prisoner 1゛ side view Fig. 2 - 1 - Guide book Table 1 Spy 78 1 cross-sectional view Fig. 3

Claims (1)

[Claims] In a method for manufacturing a MOS semiconductor device having a two-layer structure gate electrode using refractory metal silicide for the upper layer and polycrystalline silicon for the lower layer, a contact hole is formed in an insulating film to obtain an electrical connection. A method for manufacturing a MOS semiconductor device, comprising the steps of simultaneously removing the high-melting point metal silicide in the portion, introducing impurity ions through an opened contact hole, and heat treatment.