JPH02128488A - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JPH02128488A JPH02128488A JP63281793A JP28179388A JPH02128488A JP H02128488 A JPH02128488 A JP H02128488A JP 63281793 A JP63281793 A JP 63281793A JP 28179388 A JP28179388 A JP 28179388A JP H02128488 A JPH02128488 A JP H02128488A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- submount
- compound semiconductor
- block
- carbon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 150000001875 compounds Chemical class 0.000 title claims abstract description 22
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 18
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 16
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 230000007774 longterm Effects 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- -1 GaP shown in Table 1 Chemical compound 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001721 carbon Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ＧａＡｓ＋ ＧａＰ等化合物半導体材料
を使用する半導体レーザ、ＦＥＴ等化合物半導体装置に
関し、特にそのマウント材に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to compound semiconductor devices such as semiconductor lasers and FETs using compound semiconductor materials such as GaAs+GaP, and particularly relates to mounting materials thereof.
第３図は従来のＧａＡｓ系半導体レーザの組立構造図で
あり、図中、１はレーザダイオード（ＬＤ）チップ、２
はＳｉサブマウント、３及び４はそれぞれチップ側及び
サブマウント側の金（Ａｕ）系メタライズ、５は放熱用
銀（Ａｇ）ブロック、６はリード線である。Fig. 3 is an assembly structure diagram of a conventional GaAs-based semiconductor laser, in which 1 is a laser diode (LD) chip, 2 is a laser diode (LD) chip;
3 and 4 are gold (Au)-based metallization on the chip side and submount side, respectively, 5 is a silver (Ag) block for heat dissipation, and 6 is a lead wire.
組立て方法は、まず、Ａｇブロック５＋Ｓｉサブマウン
ト２．及びＬＤチップ１を３段積みにし、マウンティン
グ用ヒータ上に設置し、Ｎ２ガス雰囲気中で約４３０℃
に昇温する。Ｓｉサブマウント２の金メタライズ４はＳ
ｉサブマウント２と反応溶融し、ＡｕＳｉ共品合金品合
金、ＬＤチップ１及びＡｇブロック５と融着する。この
様な３段積み融着後にＡｇブロック５をパッケージに取
り付け、リード線６をリードボンドすることに依りＬＤ
素子が形成される。The assembly method is as follows: First, Ag block 5 + Si submount 2. LD chips 1 were stacked in three layers, placed on a mounting heater, and heated to approximately 430°C in an N2 gas atmosphere.
The temperature rises to Gold metallization 4 of Si submount 2 is S
It reacts and melts with the i-submount 2, and is fused with the AuSi alloy, the LD chip 1, and the Ag block 5. After stacking and fusing three layers like this, the Ag block 5 is attached to the package, and the lead wire 6 is lead-bonded to form the LD.
An element is formed.
従来の化合物半導体装置は以上の様に構成されており、
Ｓｉサブマウントを使用しているため、サブマウント（
Ｓｉ）とチップ（ＧａＡｓ等）との熱膨張係数の差異が
大きく、そのためチップにストレスを発生し、素子寿命
を低下させるという問題点があった。Conventional compound semiconductor devices are configured as described above.
Since a Si submount is used, the submount (
There is a large difference in thermal expansion coefficient between Si) and the chip (GaAs, etc.), which causes stress on the chip and shortens the life of the device.
この発明は上記の様な問題点を解消するためになされた
ものであり、信頼性の高い化合物半導体装置を安価に提
供することを目的としている。This invention was made to solve the above-mentioned problems, and aims to provide a highly reliable compound semiconductor device at a low cost.
この発明に係る化合物半導体装置は、化合物半導体チッ
プのマウント材にカーボン（Ｃ）を使用したものである
。A compound semiconductor device according to the present invention uses carbon (C) as a mounting material for a compound semiconductor chip.
本発明においては、マウント材に化合物半導体チップと
非常に熱膨張係数の近いカーボンを使用することに依り
、チップに引張応力及び圧縮応力がかからず、そのため
通電寿命試験やヒートサイクルテスト等、環境試験に依
る特性劣化のないデバイスの製作が可能となる。In the present invention, by using carbon, which has a coefficient of thermal expansion very similar to that of the compound semiconductor chip, as the mounting material, no tensile stress or compressive stress is applied to the chip, and therefore environmental It becomes possible to manufacture devices without deterioration of characteristics due to testing.
以下、この発明の一実施例を第１図について説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図において、１はＬＤチップ、３及び４はそれぞれ
チップ側及びサブマウント側の金糸メタライズ、５は放
熱用Ａｇブロック、６はリード線、７はカーボン（Ｃ）
からなるサブマウントである。In Figure 1, 1 is an LD chip, 3 and 4 are gold thread metallization on the chip side and submount side, respectively, 5 is an Ag block for heat dissipation, 6 is a lead wire, and 7 is carbon (C).
It is a submount consisting of.
組立ては、まず、Ａｇブロック５．カーボン（Ｃ）サブ
マウント７１ 及びＬＤチップ１を３段積みにし、マウ
ンティング用ヒータ上に設置し、Ｎ２ガス雰囲気中で約
４３０℃に昇温する。チップ１及びサブマウント７のメ
タライズ３，４には、ＡｕＳｉ、ＡｕＳｎ等Ａｕ系のも
のやＰ ｂ Ｓ ｎｌＩｎＳｎ等低温用メタライズなど
を使用し、上記チップ１とサブマウント７、及びサブマ
ウント７とＡｇブロック５を融着する。この様な３段積
み融着後にＡｇブロック５をパッケージに取り付け、リ
ード線６をリードボンドすることに依りＬＤ素子を形成
する。First, assemble the Ag block 5. The carbon (C) submount 71 and the LD chip 1 are stacked in three stages, placed on a mounting heater, and heated to about 430° C. in an N2 gas atmosphere. The metallization 3 and 4 of the chip 1 and the submount 7 are made of Au-based materials such as AuSi and AuSn, or low-temperature metallization such as PbSnlInSn. Fuse block 5. After stacking and fusing the three layers in this manner, the Ag block 5 is attached to the package, and the lead wires 6 are lead-bonded to form an LD element.
ここで、化合物半導体装置に使用する材料物性の一覧表
を表１に示す。Here, Table 1 shows a list of physical properties of materials used in compound semiconductor devices.
表１
例えば上記チップ１の化合物半導体にＧａＡｓを使用し
た場合、ＧａＡｓの熱膨張係数はθ、６３Ｘ １０−６
ｄ ｅ ｇ−’である。本実施例の様にサブマウントと
してＣを使用した場合、Ｃの熱膨張係数は８．５Ｘ１０
−６ｄｅｇ−’であり、ＧａＡｓの熱膨張係数との差は
非常にわずかである。一方、従来のＳｔサブマウントを
使用した場合にはその差は非常に大きい。従って、この
実施例に依れば、Ｃサブマウント７を使用しているので
、上記の様にチップ１とサブマウント７との熱膨張係数
が非常に近いため、チップへの引張応力や圧縮応力がか
からず、通電寿命試験やヒートサイクルテスト等の環境
試験で応力に起因するデバイスの特性劣化が生じない。Table 1 For example, when GaAs is used as the compound semiconductor of chip 1, the thermal expansion coefficient of GaAs is θ, 63X 10-6
d e g-'. When C is used as a submount as in this example, the thermal expansion coefficient of C is 8.5X10
-6 deg-', and the difference from the thermal expansion coefficient of GaAs is very small. On the other hand, when the conventional St submount is used, the difference is very large. Therefore, according to this embodiment, since the C submount 7 is used, the coefficients of thermal expansion of the chip 1 and the submount 7 are very similar as described above, so that tensile stress and compressive stress on the chip are reduced. There is no deterioration of device characteristics due to stress in environmental tests such as current life tests and heat cycle tests.
また、上記Ｃ材はサブマウント７の下地となるブロック
材、ステム材等の材料、例えばＡｇ、Ｆｅ＋Ｃｕなど、
熱膨張係数の非常に大きな材料とチップとの緩衝材とし
ても作用する。In addition, the above-mentioned C material is a material such as a block material, a stem material, etc., which is the base of the submount 7, such as Ag, Fe+Cu, etc.
It also acts as a buffer between the chip and a material with a very large coefficient of thermal expansion.
また、この実施例の様にチップ１が半導体レーザである
場合、サブマウント７のカーボンが黒色のため、サブマ
ウント７での光の反射がなくなるなどの効果もある。Further, when the chip 1 is a semiconductor laser as in this embodiment, since the carbon of the submount 7 is black, there is an effect that light reflection on the submount 7 is eliminated.
さらに、サブマウント７のメタライズ４を、チップ１と
の界面側とＡｇブロック５との界面側とが繋がる様、例
えばサブマウント７の側面にも形成する様にすれば、電
気抵抗率を下げることができるので素子のシリーズ抵抗
を下げることができ、ひいてはチップ１の温度上昇も少
なくなり、より安定な動作が可能となる。Furthermore, if the metallization 4 of the submount 7 is formed on the side surface of the submount 7, for example, so that the interface side with the chip 1 and the interface side with the Ag block 5 are connected, the electrical resistivity can be lowered. As a result, the series resistance of the element can be lowered, which in turn reduces the temperature rise of the chip 1, allowing more stable operation.
第２図は本発明の他の実施例に依る化合物半導体装置を
示す図であり、８はブロック材としてカーボンを用いた
カーボンブロック、９はこのカーボンブロック８側のメ
タライズであり、この例では電気抵抗率を下げるために
ブロック８の側面にも形成している。この様に、ＬＤチ
ップ１をカーボンブロック８上に直接メタライズに依り
融着する様にしても良い。また、同様にＬＤチップ１を
、ステム祠としてカーボンを用いたカーボンステム上に
直接融着する様にしても良い。FIG. 2 is a diagram showing a compound semiconductor device according to another embodiment of the present invention, where 8 is a carbon block using carbon as a block material, 9 is metallization on the side of this carbon block 8, and in this example, electrical It is also formed on the side surface of the block 8 in order to lower the resistivity. In this way, the LD chip 1 may be directly fused onto the carbon block 8 by metallization. Further, similarly, the LD chip 1 may be directly fused onto a carbon stem using carbon as a stem hole.
なお、上記実施例ではいず、れもチップ１にＧａＡｓ（
熱膨張係数： ６．６３Ｘ１０−６ｄｅｇ−’）を使用
した場合について述べたが、本発明はチップ１に例えば
表１に示したＧａＰ等、熱膨張係数がカーボンに近い他
の化合物半導体材料を使用した場合においても適用でき
、上記実施例と同様の効果がある。Note that, although not in the above embodiment, the chip 1 is made of GaAs (
Although the case has been described in which a thermal expansion coefficient of 6.63 x 10-6 deg-') is used, the present invention also uses other compound semiconductor materials having a thermal expansion coefficient close to that of carbon, such as GaP shown in Table 1, for the chip 1. The present invention can also be applied in such a case, and the same effects as in the above embodiment can be obtained.
以上の様に、この発明に依れば、化合物半導体チップの
マウント材に化合物半導体と熱膨張係数が近いカーボン
を使用する様にしたので、チップとマウント材との熱膨
張係数の差異に依るチップへの歪がなくなり、環境試験
に依る特性劣化がなく長期にわたって信頼性の良い化合
物半導体装置が安価に得られる効果がある。As described above, according to the present invention, carbon having a coefficient of thermal expansion close to that of the compound semiconductor is used as the mounting material for the compound semiconductor chip. This has the effect that a compound semiconductor device that is reliable over a long period of time without deterioration of characteristics due to environmental tests can be obtained at a low cost.
第１図は本発明の一実施例に依る化合物半導体装置を示
す図、第２図は本発明の他の実施例に依る化合物半導体
装置を示す図、第３図は従来の化合物半導体装置を示す
図である。
１はＬＤチップ、７はカーボンサブマウント、８はカー
ボンブロック。
なお、図中、同一符号は同−又は相当部分を示す。FIG. 1 shows a compound semiconductor device according to an embodiment of the present invention, FIG. 2 shows a compound semiconductor device according to another embodiment of the invention, and FIG. 3 shows a conventional compound semiconductor device. It is a diagram. 1 is the LD chip, 7 is the carbon submount, and 8 is the carbon block. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
化合物半導体装置において、 上記マウント材はカーボンからなることを特徴とする化
合物半導体装置。[Claims] 1) A compound semiconductor device comprising a compound semiconductor element mounted on a mount material, wherein the mount material is made of carbon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63281793A JPH02128488A (en) | 1988-11-07 | 1988-11-07 | Compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63281793A JPH02128488A (en) | 1988-11-07 | 1988-11-07 | Compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02128488A true JPH02128488A (en) | 1990-05-16 |
Family
ID=17644057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63281793A Pending JPH02128488A (en) | 1988-11-07 | 1988-11-07 | Compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02128488A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636321U (en) * | 1992-10-12 | 1994-05-13 | 住友電設株式会社 | Floor outlet equipment |
| JP2002100826A (en) * | 2000-09-21 | 2002-04-05 | Toshiba Corp | Submount material |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6365259B2 (en) * | 1982-03-16 | 1988-12-15 |
-
1988
- 1988-11-07 JP JP63281793A patent/JPH02128488A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6365259B2 (en) * | 1982-03-16 | 1988-12-15 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636321U (en) * | 1992-10-12 | 1994-05-13 | 住友電設株式会社 | Floor outlet equipment |
| JP2002100826A (en) * | 2000-09-21 | 2002-04-05 | Toshiba Corp | Submount material |
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