JPH02125647A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPH02125647A JPH02125647A JP63279735A JP27973588A JPH02125647A JP H02125647 A JPH02125647 A JP H02125647A JP 63279735 A JP63279735 A JP 63279735A JP 27973588 A JP27973588 A JP 27973588A JP H02125647 A JPH02125647 A JP H02125647A
- Authority
- JP
- Japan
- Prior art keywords
- flip chip
- board
- gap
- solder
- flux
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910000679 solder Inorganic materials 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 30
- 230000004907 flux Effects 0.000 claims abstract description 16
- 239000003960 organic solvent Substances 0.000 claims abstract description 7
- 238000005476 soldering Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 abstract description 4
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 abstract description 2
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 abstract description 2
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 description 8
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004093 laser heating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、混成集積回路の製造方法に関し、特にフリッ
プチップを搭載した基板とクリップ端子とをレーザー照
射により半田付けする混成集積回路の製造方法に関する
。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a hybrid integrated circuit, and in particular, a method for manufacturing a hybrid integrated circuit in which a substrate on which a flip chip is mounted and a clip terminal are soldered by laser irradiation. Regarding.
従来、混成集積回路基板にリード端子を接続する場合、
以下の様に行っていた。先ず、基板上に各種部品を搭載
し、配線接続を行なう、また、ペアペレットは樹脂によ
り保護する。次にクリップ端子で基板を挟み、溶融した
半田槽に浸す（半田デイツプ法）か又は半田ペーストを
端子に塗布加熱して溶融する（リフロー法）方法で端子
接続を行っている。リフロー法には、赤外線リフロー炉
、気相法等の素子全体を加熱する一括加熱法と、レーザ
ー法、光ビーム法、ホットラム法、熱風等の素子の一部
を加熱する部分加熱法がある。Conventionally, when connecting lead terminals to a hybrid integrated circuit board,
It was done as follows. First, various parts are mounted on the board, wiring connections are made, and the paired pellets are protected with resin. Next, terminal connections are made by sandwiching the board between clip terminals and dipping it into a bath of molten solder (solder dip method), or by applying solder paste to the terminals and heating and melting them (reflow method). Reflow methods include batch heating methods such as infrared reflow ovens and vapor phase methods in which the entire element is heated, and partial heating methods in which a portion of the element is heated such as laser methods, light beam methods, hot ram methods, and hot air.
半田デイツプ法、リフロー法（−括加熱法１部分加熱法
）の各方法のうち半田デイツプ法は、基板や部品への熱
ストレスが大きいのでリフロ一方法への置き換えが進ん
でいる。またリフロー法の中でも高密度実装型の製品で
は、必要部分のみを加熱する部分加熱法が注目を集めて
いる。レーザー加熱法はこの中で加熱面積が小さいこと
、及び加熱時間が短いことが特徴であり、ペアペレット
を搭載した高密度実装型基板への適用が進められている
。特に、半田バンプを有するフリップチップを搭載した
基板に端子を接続する場合、端子部分のみを局所的に加
熱する必要がある。Of the solder dip method and the reflow method (-bulk heating method, one-part heating method), the solder dip method is increasingly being replaced by the reflow method because it imposes a large amount of thermal stress on the board and components. Among the reflow methods, the partial heating method, which heats only the necessary parts, is attracting attention for high-density packaging products. Among these methods, the laser heating method is characterized by its small heating area and short heating time, and its application to high-density mounting type substrates mounted with paired pellets is progressing. In particular, when connecting a terminal to a board on which a flip chip having solder bumps is mounted, it is necessary to locally heat only the terminal portion.
ところで、上述した従来のレーザ半田付法は、以下の様
な欠点を有する。半田ペーストに照射されたレーザー光
は半田を溶融するとともにフラックスを突沸させるので
半田ボール及びフラックスを飛散させる。このために基
板上に飛散したフラックスや半田ボールを有機溶剤に浸
漬し、超音波を印加する等して除去する必要がある。と
ころでフリップチップを搭載した基板は、フリップチッ
プとの間に半田バンプの高さとほぼ同じ数１０ ／ｌ
ｍ〜１００μｍ前後の間隙を有する。レーザー照射によ
り飛散して半田ボールは、この間隙に突入し、隣接する
半田バンプを短絡させることがあった。レーザー半田付
は前に、フリップチップ自身を樹脂により被覆する方法
があるが、フリップチップとクリップ端子の間隔が狭い
場合、クリップ端子を露出させたままフリップチップの
みを被覆することは困難となる。従って、フリップチッ
プの特徴を生かした高密度実装素子を製造する場合、被
覆されないフリップチップの搭載された基板の端子ず田
付けを行った後、素子全体の被覆を行なう必要がある。By the way, the conventional laser soldering method described above has the following drawbacks. The laser beam irradiated onto the solder paste melts the solder and causes the flux to bump, causing the solder balls and flux to scatter. For this purpose, it is necessary to remove the flux and solder balls scattered on the substrate by immersing them in an organic solvent and applying ultrasonic waves. By the way, the board on which the flip chip is mounted has a distance of 10/l, which is approximately the same as the height of the solder bumps, between the flip chip and the board.
It has a gap of about m to 100 μm. The solder balls scattered by the laser irradiation sometimes entered this gap and short-circuited adjacent solder bumps. Laser soldering has previously been done by coating the flip chip itself with resin, but if the distance between the flip chip and the clip terminal is narrow, it is difficult to coat only the flip chip while leaving the clip terminal exposed. Therefore, when manufacturing a high-density mounting device that takes advantage of the characteristics of flip chips, it is necessary to solder the terminals of the substrate on which the uncovered flip chip is mounted, and then cover the entire device.
本発明は、フリップチップを搭載した基板１−に、クリ
ップ端子を装着し半田ペーストを塗布してレーザー光に
より半田付けする混成集積回路の製造方法において、前
記半田ペーストをクリップ端子に塗布する工程と、前記
フリップチップと前記基板との間隙を有機溶剤で溶解す
る物質で遮へいする工程と、前記半田ペーストのフラッ
クス及び前記基板とフリップチップとの間隙を遮へいす
る物質を一括して除去する工程とを含むことを特６７と
する。The present invention provides a method for manufacturing a hybrid integrated circuit in which a clip terminal is attached to a substrate 1- on which a flip chip is mounted, a solder paste is applied, and the soldering is performed using a laser beam, including the step of applying the solder paste to the clip terminal. , a step of shielding the gap between the flip chip and the substrate with a substance that can be dissolved with an organic solvent, and a step of removing all at once the flux of the solder paste and the substance shielding the gap between the substrate and the flip chip. It shall be included in Special Clause 67.
次に、本発明について図面を参照して説明する。第１図
は、本発明の第１の実施例の製造工程を示す断面図であ
る。第１図（ａ）に示すように、回路基板１上にフリッ
プチップ２を搭載する。次に第１図（ｂ）のようにクリ
ップ端子５を挿入して、高粘度に調整したロジン系フラ
ックス４を広がりを考慮して基板上に数点塗布した。フ
ラックス４は基板上に広がり表面張力で基板とフリップ
チップ２の間隙を遮へいした。これを】００°Ｃで予備
乾燥して、第１図（Ｃ）のようにクリップ端子５上にデ
イスペンサーで半田ペースト６を塗布した。そして、半
田ペースト６にＹＡＧレーザー光を照射する。半田ペー
ストは溶解して各クリップ端子に引き寄せられるととも
に、大量のフラックスと半田ボールを飛散させるが、あ
らかじめ塗布されたフラックスによってフリップチップ
２の間隙は遮へいされており、フリップチップ２に半田
ボールが衝突したり、間隙に突入することが無い。これ
を基板ごと有機溶剤に浸漬してフラックスや半田ボール
を除去する。そして第１図（ｄ ）のようにフリップチ
ップ２を被覆用樹脂８で被覆した後、外装樹脂９で全体
を被覆すると混成集積回路が得られる。Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view showing the manufacturing process of the first embodiment of the present invention. As shown in FIG. 1(a), a flip chip 2 is mounted on a circuit board 1. Next, as shown in FIG. 1(b), a clip terminal 5 was inserted, and a rosin-based flux 4 adjusted to have a high viscosity was applied at several points on the substrate, taking into consideration its spread. The flux 4 spread over the substrate and blocked the gap between the substrate and the flip chip 2 due to surface tension. This was pre-dried at 00°C, and solder paste 6 was applied onto the clip terminal 5 using a dispenser as shown in FIG. 1(C). Then, the solder paste 6 is irradiated with YAG laser light. The solder paste melts and is attracted to each clip terminal, scattering a large amount of flux and solder balls, but the gap between the flip chips 2 is shielded by the pre-applied flux, and the solder balls collide with the flip chips 2. There is no chance of the product falling or entering the gap. The entire board is immersed in an organic solvent to remove flux and solder balls. Then, as shown in FIG. 1(d), after the flip chip 2 is covered with a coating resin 8, the whole is covered with an exterior resin 9 to obtain a hybrid integrated circuit.
第２図（ａ）、（ｂ）は本発明の第２の実施例の製造工
程の一部を示す断面図である。本実施例では、間隙の遮
へい用物質としてクリップ端−看に塗布する半田ペース
トを使用した。第２［４（ａ）、（ｂ）に示すように基
板１にクリップ端子５を挿入して、クリップ端子５及び
基板１と一２リップチップ２との間隙部に半田ペースト
６を＜・ノτ布した。それから、ＹＡＧレーザー光でク
リップ端子５の半田付けを行ない、有機溶剤でフラック
スと半田ペーストの除去を行った。そして第１の実施例
と同様に樹脂被覆を行ってフリップチップを搭載した混
成集積回路を得た。FIGS. 2(a) and 2(b) are cross-sectional views showing a part of the manufacturing process of the second embodiment of the present invention. In this example, a solder paste applied to the end of the clip was used as the material for shielding the gap. 2. Insert the clip terminal 5 into the board 1 as shown in FIG. τ clothed. Then, the clip terminals 5 were soldered using a YAG laser beam, and the flux and solder paste were removed using an organic solvent. Then, resin coating was performed in the same manner as in the first embodiment to obtain a hybrid integrated circuit equipped with a flip chip.
この実施例では、半田付は用に半田ペーストをそのまま
用いたが、遮へい用に塗布する量が多くなる場合や塗布
時間が長くなる場合は、コスト的に不利となるので、こ
の方法は部分的な遮へいに使用する場合に適している。In this example, solder paste was used as is for soldering, but if the amount to be applied for shielding is large or if the application time is long, it will be disadvantageous in terms of cost, so this method is partially applicable. Suitable for use as shielding.
本発明によれば、半田ボールがフリップチップと基板と
の間隙に突入することが無く、更に間隙に半田ボールが
突入しない用に遮へいする物質を半田ベーストのフラッ
クスと同時に除去できるので、製造歩留りが上がり、安
価なフリップチップを搭載した混成集積回路を実現でき
る効果がある。According to the present invention, the solder ball does not enter the gap between the flip chip and the substrate, and the material that shields the solder ball from entering the gap can be removed at the same time as the flux of the solder base, which improves the manufacturing yield. This has the effect of making it possible to realize a hybrid integrated circuit equipped with a low-cost flip chip.
第１図（ａ）〜（ｄ）は、本発明の第１の実施例の製造
工程を示す断面図、第２図（ａ）（ｂ）は本発明の第２
の実施例の製造工程の一部を示す断面図である。
１・・・基板、２・・フリップチップ、３・・・半田バ
ンプ、４・・・フラックス、５・・・クリップ端子、６
・・・半田ペースト、７・・・半田、８・・・フリップ
チップ被覆あ
山FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process of the first embodiment of the present invention, and FIGS. 2(a) and (b) are cross-sectional views showing the manufacturing process of the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a part of the manufacturing process of the example. 1... Board, 2... Flip chip, 3... Solder bump, 4... Flux, 5... Clip terminal, 6
...Solder paste, 7...Solder, 8...Flip chip coating pile
Claims (1)
装着し半田ペーストを塗布してレーザー光により半田付
けする混成集積回路の製造方法において、前記半田ペー
ストをクリップ端子に塗布する工程と、前記フリップチ
ップと前記基板との間隙を有機溶剤で溶解する物質で遮
へいする工程と、前記半田ペーストのフラックス及び前
記基板とフリップチップとの間隙を遮へいする物質を一
括して除去する工程とを含むことを特徴とする混成集積
回路の製造方法。A method for manufacturing a hybrid integrated circuit in which a clip terminal is mounted on a board on which a flip chip is mounted, a solder paste is applied, and the soldering is performed using a laser beam. The method includes the steps of: shielding the gap between the substrate and the flip chip with a substance that can be dissolved with an organic solvent; and removing at once the flux of the solder paste and the substance that shields the gap between the substrate and the flip chip. A method for manufacturing a hybrid integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63279735A JPH02125647A (en) | 1988-11-04 | 1988-11-04 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63279735A JPH02125647A (en) | 1988-11-04 | 1988-11-04 | Manufacture of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02125647A true JPH02125647A (en) | 1990-05-14 |
Family
ID=17615161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63279735A Pending JPH02125647A (en) | 1988-11-04 | 1988-11-04 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02125647A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04122097A (en) * | 1990-09-13 | 1992-04-22 | Kokusai Electric Co Ltd | Production of electronic apparatus |
| JPH10256713A (en) * | 1997-03-13 | 1998-09-25 | Samsung Electron Co Ltd | Method of mounting ic package |
| JP2018163998A (en) * | 2017-03-27 | 2018-10-18 | 横河電機株式会社 | Explosion proof component mounting board |
-
1988
- 1988-11-04 JP JP63279735A patent/JPH02125647A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04122097A (en) * | 1990-09-13 | 1992-04-22 | Kokusai Electric Co Ltd | Production of electronic apparatus |
| JPH10256713A (en) * | 1997-03-13 | 1998-09-25 | Samsung Electron Co Ltd | Method of mounting ic package |
| JP2018163998A (en) * | 2017-03-27 | 2018-10-18 | 横河電機株式会社 | Explosion proof component mounting board |
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