JPH07302808A - Method for coating electronic element - Google Patents
Method for coating electronic elementInfo
- Publication number
- JPH07302808A JPH07302808A JP6114360A JP11436094A JPH07302808A JP H07302808 A JPH07302808 A JP H07302808A JP 6114360 A JP6114360 A JP 6114360A JP 11436094 A JP11436094 A JP 11436094A JP H07302808 A JPH07302808 A JP H07302808A
- Authority
- JP
- Japan
- Prior art keywords
- sealing material
- sealing
- electronic member
- coating
- unnecessary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、所定のマウント基材上
に実装する電子部材の外面を保護用の封止材料にてコー
ティングする方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of coating an outer surface of an electronic member mounted on a predetermined mount substrate with a protective sealing material.
【０００２】[0002]
【従来の技術】図７は、従来の電子部材のコーティング
方法を説明する概略断面図であり、電子部材として半導
体素子１を用いた場合を例として示している。すなわ
ち、この半導体素子１を所定の封止材料２にてコーティ
ングするには、先ず、チップ状の半導体素子１をマウン
ト基材３上に実装した後、半導体素子１に設けられた電
極パッド１１とマウント基材３上に設けられた配線パタ
ーン３１とをボンディングワイヤー４にて接続する。こ
の状態で半導体素子１の上方からディスペンサ７を用い
て保護用の樹脂から成る封止材料２を滴下し、その流動
性を利用して半導体素子１の外周を覆うようにする。そ
して、この封止材料２を硬化させることにより、湿気や
外光から半導体素子１を保護するためのコーティングを
行っている。2. Description of the Related Art FIG. 7 is a schematic cross-sectional view for explaining a conventional method for coating an electronic member, and shows an example in which a semiconductor element 1 is used as the electronic member. That is, in order to coat the semiconductor element 1 with the predetermined sealing material 2, first, the chip-shaped semiconductor element 1 is mounted on the mount base material 3, and then the electrode pads 11 provided on the semiconductor element 1 are formed. The wiring pattern 31 provided on the mount substrate 3 is connected by the bonding wire 4. In this state, the sealing material 2 made of a protective resin is dropped from above the semiconductor element 1 by using the dispenser 7, and the fluidity thereof is used to cover the outer periphery of the semiconductor element 1. Then, by curing the sealing material 2, coating for protecting the semiconductor element 1 from moisture and external light is performed.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな電子部材のコーティング方法には次のような問題が
ある。すなわち、封止を必要とする電子部材と封止を必
要としない部品とが接近してマウント基材上に実装され
ている場合、ディスペンサにて封止材料を滴下する際に
その封止材料が封止を必要としない部品に付着しないよ
う十分な注意が必要となる。However, such a coating method for electronic members has the following problems. That is, when the electronic member that requires sealing and the component that does not require sealing are mounted close to each other on the mount base material, when the sealing material is dropped by the dispenser, the sealing material is Great care must be taken not to adhere to parts that do not require sealing.
【０００４】ディスペンサは、封止材料となる樹脂を充
填するためのシリンジと、シリンジの先端部に取り付け
られたニードルとから構成されており、シリンジ内の樹
脂を例えば押し棒で押圧したり空気圧によって加圧する
ことでニードル先端の細穴から樹脂を射出する用具であ
る。近年では、実装部品の高密度化が進んでおり、この
ようなディスペンサを用いて所定領域にのみ封止材料と
なる樹脂を塗布するのは非常に困難である。The dispenser is composed of a syringe for filling a resin as a sealing material and a needle attached to the tip of the syringe. The resin in the syringe is pressed with a push rod or by air pressure, for example. It is a tool that injects resin from a small hole at the tip of the needle by applying pressure. In recent years, the density of mounted components has been increasing, and it is very difficult to apply a resin as a sealing material only to a predetermined region using such a dispenser.
【０００５】例えば、赤外線受光モジュールにおいて
は、赤外線光を受けるため封止の不要なＰＩＮフォトダ
イオードと、外光による誤動作を防止するため封止の必
要となる増幅用ＩＣとが１ｍｍ程度の間隔で実装されて
いる。このような増幅用ＩＣの外面にのみ誤動作防止用
の樹脂をディスペンサにて塗布するのは非常に困難であ
り、誤ってＰＩＮフォトダイオードにこの樹脂が付着し
てしまった場合には赤外線受光モジュールの受光特性に
多大な悪影響を与えることになる。For example, in an infrared light receiving module, a PIN photodiode that does not need to be sealed because it receives infrared light and an amplifying IC that needs to be sealed to prevent malfunction due to outside light are spaced by about 1 mm. It is implemented. It is very difficult to apply a malfunction preventing resin only to the outer surface of such an amplifying IC with a dispenser, and if this resin accidentally adheres to the PIN photodiode, the infrared receiving module This will have a great adverse effect on the light receiving characteristics.
【０００６】この問題を解消するために、ディスペンサ
のニードル先端の細穴の径を更に細くし、微細で精密な
樹脂塗布を行うことが考えられるが、これでは樹脂の出
方の低下を招き、作業効率を悪化させることになる。ま
た、ディスペンサによる樹脂塗布では、シリンジの中の
樹脂量や作業時の温度等により塗布される量が変化して
しまい、均一な塗布量を実現するのは困難である。In order to solve this problem, it is considered that the diameter of the fine hole at the tip of the needle of the dispenser is further reduced and fine and precise resin coating is carried out, but this causes a decrease in the appearance of resin, Work efficiency will be deteriorated. In addition, in the resin application by the dispenser, the applied amount changes depending on the amount of resin in the syringe, the temperature during work, and the like, and it is difficult to realize a uniform applied amount.
【０００７】[0007]
【課題を解決するための手段】本発明は、このような課
題を解決するために成された電子部材のコーティング方
法である。すなわち、本発明は、所定の封止不要領域を
有する電子部材をマウント基材上に実装した状態でこの
電子部材を保護用の封止材料にてコーティングする方法
であり、第１の工程として電子部材の外面で少なくとも
封止不要領域を除く部分に封止材料を被着する処理を行
い、第２の工程として電子部材をマウント基材上に実装
して封止不要領域に対する所定の処理を行い、第３の工
程として封止材料を溶融することで電子部材の外面でマ
ウント基材との実装面および封止不要領域以外の全ての
部分を封止材料にて覆う処理を行っている。The present invention is a method for coating an electronic member, which has been made to solve the above problems. That is, the present invention is a method of coating an electronic member having a predetermined unnecessary sealing region on a mount base material with a protective sealing material, and the electronic member is used as a first step. A process of applying a sealing material to at least a portion of the outer surface of the member excluding the non-sealing region is performed, and as a second step, an electronic member is mounted on a mount base material and a predetermined process is performed on the non-sealing region. In the third step, the sealing material is melted to cover the entire surface of the electronic member except the mounting surface with the mount base material and the sealing unnecessary area on the outer surface of the electronic member.
【０００８】また、封止材料として感光性材料を用いた
場合には、第１の工程として電子部材の外面全体にこの
封止材料を一様に塗布した後、所定の光を該封止材料に
照射することで少なくとも封止不要領域に塗布された該
封止材料を除去する。また、封止材料として熱可塑性樹
脂を用いた場合には、第１の工程として電子部材の外面
全体にこの封止材料を一様に塗布した後、少なくとも封
止不要領域を部分加熱して塗布された封止材料を蒸発さ
せる方法でもある。さらに、第３の工程において、封止
材料を溶融する際、封止材料に対して超音波を与えるよ
うにした電子部材のコーティング方法でもある。When a photosensitive material is used as the sealing material, the first step is to uniformly apply the sealing material to the entire outer surface of the electronic member, and then apply predetermined light to the sealing material. To remove the sealing material applied to at least the sealing unnecessary area. When a thermoplastic resin is used as the sealing material, the first step is to uniformly apply the sealing material to the entire outer surface of the electronic member, and then at least partially heat the non-sealing area to apply the sealing material. It is also a method of evaporating the encapsulating material thus formed. Furthermore, in the third step, when the sealing material is melted, ultrasonic waves are applied to the sealing material, which is also a coating method for the electronic member.
【０００９】[0009]
【作用】本発明では、第１の工程により電子部材の外面
で少なくとも封止不要領域を除く部分に封止材料を被着
しているため、第２の工程で電子部材をマウント基材上
に実装した後の封止不要領域に対する所定の処理を封止
材料の影響を受けることなく行えるようになる。また、
第３の工程において封止材料を溶融することで、電子部
材の外面のマウント基材との実装面および封止不要領域
以外の全ての部分に封止材料が回り込む状態となり、封
止が必要な部分を全て封止材料にて覆うことができる。In the present invention, since the sealing material is applied to the outer surface of the electronic member in the first step except at least the unnecessary sealing region, the electronic member is mounted on the mount substrate in the second step. Predetermined processing can be performed on the sealing-unnecessary region after mounting without being affected by the sealing material. Also,
By melting the encapsulating material in the third step, the encapsulating material comes into a state where the encapsulating material wraps around the mounting surface of the electronic member on the mount base material and all the areas other than the sealing-unnecessary area, and thus the sealing is required. The entire portion can be covered with the sealing material.
【００１０】また、封止材料として感光性材料を用いる
ことで、封止材料を電子部材の全面に一様に塗布した後
に光の照射によって封止不要領域に塗布された封止材料
を一括除去できるようになる。さらに、封止材料として
熱可塑性樹脂を用いる場合には、封止材料を電子部材の
全面に一様に塗布した後、封止不要領域に塗布された封
止材料を部分加熱することでその位置の封止材料が蒸発
して除去できるようになる。しかも、感光性材料や熱可
塑性樹脂から成る封止材料を電子部材の全面に一様に塗
布することから、封止不要領域以外の部分の封止材料が
均一な量となる。また、第３の工程において封止材料を
溶融する際、封止材料に超音波を与えることで封止材料
の粘性が低下して電子部材外面への回り込みが容易とな
る。Further, by using the photosensitive material as the sealing material, the sealing material is uniformly applied to the entire surface of the electronic member and then the sealing material applied to the unnecessary sealing area is collectively removed by irradiation of light. become able to. Further, when a thermoplastic resin is used as the sealing material, the sealing material is evenly applied to the entire surface of the electronic member, and then the sealing material applied to the unnecessary sealing area is partially heated to move its position. The encapsulating material in the above can be evaporated and removed. Moreover, since the sealing material composed of the photosensitive material or the thermoplastic resin is uniformly applied to the entire surface of the electronic member, the sealing material in the portion other than the sealing unnecessary area becomes uniform. Further, when the sealing material is melted in the third step, by applying ultrasonic waves to the sealing material, the viscosity of the sealing material is reduced and it becomes easy for the sealing material to go around to the outer surface of the electronic member.
【００１１】[0011]
【実施例】以下に、本発明の電子部材のコーティング方
法の実施例を図に基づいて説明する。図１は、本発明の
電子部材のコーティング方法を第１工程から第３工程の
順に説明する概略断面図であり、電子部材の例として半
導体素子１を用いた場合を示している。先ず、図１
（ａ）に示す第１工程として、半導体素子１の外面で少
なくとも封止不要領域Ｓ以外の部分に封止材料２を被着
する処理を行う。Embodiments of the method for coating an electronic member according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view for explaining the coating method for an electronic member of the present invention in the order of the first step to the third step, and shows a case where a semiconductor element 1 is used as an example of the electronic member. First, Fig. 1
As a first step shown in (a), a process of depositing the sealing material 2 on the outer surface of the semiconductor element 1 at least in a portion other than the unnecessary sealing region S is performed.
【００１２】封止不要領域Ｓとは、封止材料２が塗布さ
れると不都合のある場所であり、例えば後の工程で電気
的な配線を行うための電極パッド１１の一部であった
り、光学的な入出力が必要となる部分である。図１
（ａ）に示す例では、半導体素子１の上面に設けられた
電極パッド１１の一部が封止不要領域Ｓとなっており、
この封止不要領域Ｓよりもわずかに広く封止材料２を塗
布しない部分を設けている。これは、後述する第２工程
でのボンディングワイヤーの接続位置誤差を考慮してボ
ンディングワイヤーの接触領域である封止不要領域Ｓよ
りもわずかに大きく開口させ、ボンディングワイヤーの
確実な接続を得るためである。The unneeded region S is a place where the encapsulation material 2 is inconvenient, for example, a part of the electrode pad 11 for electrical wiring in a later step, This is the part that requires optical input / output. Figure 1
In the example shown in (a), a part of the electrode pad 11 provided on the upper surface of the semiconductor element 1 is the sealing unnecessary region S,
A portion where the sealing material 2 is not applied is provided slightly wider than the sealing unnecessary region S. This is because in order to obtain a reliable connection of the bonding wire, the opening is made slightly larger than the sealing unnecessary area S which is the contact area of the bonding wire in consideration of the bonding wire connection position error in the second step described later. is there.
【００１３】次に、図１（ｂ）に示す第２工程として、
半導体素子１をリードフレームやプリント配線板等のマ
ウント基材３上に実装した後に第１工程で封止材料２を
塗布しなかった電極パッド１１とマウント基材３上に設
けられた配線パターン３１とをボンディングワイヤー４
にて接続する処理を行う。第２工程でワイヤーボンディ
ングを行うにあたり、予め第１工程で電極パッド１１上
のボンディングワイヤー４の接続位置（封止不要領域
Ｓ）よりも大きめに封止材料２を塗布しない領域を設け
ているため、多少位置合わせ誤差が生じた場合であって
もボンディングワイヤー４と電極パッド１１との確実な
圧着を行うことができる。Next, as a second step shown in FIG.
After mounting the semiconductor element 1 on the mount base material 3 such as a lead frame or a printed wiring board, the electrode pad 11 on which the sealing material 2 was not applied in the first step and the wiring pattern 31 provided on the mount base material 3 And bonding wire 4
Perform the process to connect. In performing the wire bonding in the second step, a region where the sealing material 2 is not applied is provided in advance in the first step in a size larger than the connection position of the bonding wire 4 on the electrode pad 11 (sealing unnecessary region S). Even if there is some alignment error, the bonding wire 4 and the electrode pad 11 can be reliably pressure bonded.
【００１４】次いで、図１（ｃ）に示す第３工程とし
て、封止材料２の溶融処理を行う。つまり、半導体素子
１の外周に塗布された封止材料２を加熱等によって溶融
することで封止材料２が溶け出して、半導体素子１の外
周でマウント基材３との実装面および封止不要領域Ｓ以
外の全ての部分、特に半導体素子１の側面１ａまでも封
止材料２が回り込み、半導体素子１を覆う状態となる。
なお、封止不要領域Ｓにはボンディングワイヤー４が接
触しているため、このような封止材料２の回り込みによ
ってボンディングワイヤー４の接続部分周囲もコートさ
れ、接続補強の効果が生じることになる。Next, as a third step shown in FIG. 1C, the sealing material 2 is melted. That is, the sealing material 2 applied to the outer periphery of the semiconductor element 1 is melted by heating or the like, whereby the sealing material 2 is melted out, and the mounting surface with the mount base material 3 on the outer periphery of the semiconductor element 1 and sealing are unnecessary. The sealing material 2 also wraps around all the parts other than the region S, especially the side surface 1a of the semiconductor element 1 to cover the semiconductor element 1.
Since the bonding wire 4 is in contact with the sealing unnecessary area S, such a wraparound of the sealing material 2 also coats the periphery of the connection portion of the bonding wire 4 and an effect of reinforcing the connection is produced.
【００１５】次に、本発明の具体的な一例を図２〜図４
に基づいて説明する。以下の例では、複数の半導体素子
１が所定の回路形成工程によって設けられたウエハ１０
の状態からの説明を行う。先ず、図２（ａ）に示すスピ
ンコーティングとして、ウエハ１０の表面に封止材料２
を塗布した状態でウエハ１０を回転させ、表面に一様な
厚さで封止材料２を被着させる処理を行う。封止材料２
としては、例えば熱可塑性樹脂から成るものや感光性樹
脂から成るものを用る。このような封止材料２をスピン
コーティングによってウエハ１０の表面に０．１ｍｍ程
度の厚さに塗布する。Next, a concrete example of the present invention will be described with reference to FIGS.
It will be described based on. In the following example, the wafer 10 in which the plurality of semiconductor elements 1 are provided by a predetermined circuit forming process
It will be explained from the state of. First, as the spin coating shown in FIG. 2A, the sealing material 2 is formed on the surface of the wafer 10.
Then, the wafer 10 is rotated in a state of being coated with, and a process for applying the sealing material 2 to the surface with a uniform thickness is performed. Sealing material 2
For example, one made of a thermoplastic resin or one made of a photosensitive resin is used. Such a sealing material 2 is applied to the surface of the wafer 10 by spin coating to a thickness of about 0.1 mm.
【００１６】次に、図２（ｂ）に示す硬化として、ウエ
ハ１０の表面にスピンコーティングで被着した封止材料
２を硬化させる処理を行う。この処理では、先のスピン
コーティングの際、加熱により粘度調整を行う封止材料
２を用いた場合にはこれを冷却することで硬化を行う。
また、所定の溶剤を混ぜることで粘度調整を行う封止材
料２を用いた場合には乾燥によりその溶剤を蒸発させる
ことで硬化を行う。Next, as the curing shown in FIG. 2B, a process of curing the sealing material 2 deposited on the surface of the wafer 10 by spin coating is performed. In this treatment, when the sealing material 2 whose viscosity is adjusted by heating is used in the previous spin coating, it is cured by cooling it.
Further, when the sealing material 2 whose viscosity is adjusted by mixing a predetermined solvent is used, it is cured by evaporating the solvent by drying.
【００１７】次いで、図２（ｃ）に示す不要部分の除去
として、各半導体素子１の表面で封止不要領域Ｓ（図１
（ａ）参照）である例えば電極パッド１１の部分に塗布
された封止材料２の除去処理を行う。例えば、封止材料
２として熱可塑性樹脂を用いた場合には、レーザ光５を
除去位置（例えば各電極パッド１１上）に照射し、これ
によってその位置の封止材料２を加熱蒸発させることで
除去を行う。また、封止材料２として感光性樹脂を用い
た場合には、所定のマスク（図示せず）を介して封止材
料２上に光を照射した後、所定の溶剤を用いて現像する
ことによって除去位置（例えば各電極パッド１１上）の
封止材料２を除去する。Next, as a removal of the unnecessary portion shown in FIG. 2C, a sealing unnecessary region S (FIG. 1) is formed on the surface of each semiconductor element 1.
(See (a)), for example, a process of removing the sealing material 2 applied to the portion of the electrode pad 11 is performed. For example, when a thermoplastic resin is used as the sealing material 2, by irradiating the removal position (for example, on each electrode pad 11) with the laser beam 5, the sealing material 2 at that position is heated and evaporated. Remove. When a photosensitive resin is used as the sealing material 2, by irradiating the sealing material 2 with light through a predetermined mask (not shown) and then developing it with a predetermined solvent. The sealing material 2 at the removal position (for example, on each electrode pad 11) is removed.
【００１８】レーザ光５を用いる場合には、その波長と
して封止材料２には吸収されやすく、電極パッド１１の
材質（一般的にはアルミニウム）に吸収されにくい例え
ばＹＡＧレーザを用いる。なお、この場合のレーザ光５
のスポットサイズは１μｍ以下にするのが望ましい。When the laser beam 5 is used, for example, a YAG laser is used as its wavelength, which is easily absorbed by the sealing material 2 and is hardly absorbed by the material of the electrode pad 11 (generally aluminum). In this case, the laser light 5
The spot size is preferably 1 μm or less.
【００１９】このようなレーザ光５を用いて封止材料２
の部分除去を行う場合には、熱可塑性樹脂であればどの
ような種類でも良いため半導体素子１の保護目的に応じ
た樹脂を選択できるようになる。また、感光性樹脂を用
いて部分除去を行う場合には一括した除去作業が行える
ことになり、作業時間の短縮化を図ることが可能とな
る。A sealing material 2 is produced by using such a laser beam 5.
When the partial removal is performed, any type of thermoplastic resin may be used, so that it is possible to select a resin suitable for the purpose of protecting the semiconductor element 1. Further, when the photosensitive resin is used for partial removal, it is possible to carry out collective removal work, and it is possible to shorten the work time.
【００２０】次に、図３（ａ）に示すダイシングとし
て、ウエハ１０を所定位置で切断して個々の半導体素子
１に分割する処理を行う。これにより、それぞれの半導
体素子１において、少なくとも封止不要領域Ｓ（図１
（ａ）参照）を除く部分に封止材料２が被着した状態と
なる。続いて、図３（ｂ）に示すダイボンディングとし
て、半導体素子１をマウント基材３上に実装する処理を
行い、その後、図３（ｃ）に示すワイヤーボンディング
として、半導体素子１上の電極パッド１１とマウント基
材３上の配線パターン３１とのボンディングワイヤー４
による接続処理を行う。Next, as the dicing shown in FIG. 3A, a process of cutting the wafer 10 at a predetermined position and dividing it into individual semiconductor elements 1 is performed. Thereby, in each semiconductor element 1, at least the sealing unnecessary region S (see FIG.
The sealing material 2 is attached to the portion excluding (a). Subsequently, as the die bonding shown in FIG. 3B, a process of mounting the semiconductor element 1 on the mount base material 3 is performed, and then, as the wire bonding shown in FIG. 3C, the electrode pad on the semiconductor element 1 is performed. Bonding wire 4 between 11 and the wiring pattern 31 on the mount substrate 3
Performs connection processing by.
【００２１】半導体素子１のダイボンドでは、ダイボン
ド剤（図示せず）の硬化（キュア）の際に封止材料２が
溶融しないような材質のものを用いる。また、図４
（ａ）はボンディング部の部分拡大図である。すなわ
ち、先に説明した不要部分の除去処理（図２（ｃ）参
照）により、少なくとも封止不要領域Ｓの部分に塗布さ
れた封止材料２が除去されており、これによって例えば
電極パッド１１が露出した状態となっている。この露出
部分は、ボンディングワイヤー４の位置決め誤差を考慮
して封止不要領域Ｓよりもわずかに大きくなっており、
多少の誤差でもボンディングワイヤー４の先端が電極パ
ッド１１と確実に接触できるようになっている。In the die bonding of the semiconductor element 1, a material that does not melt the sealing material 2 when the die bonding agent (not shown) is cured is used. Also, FIG.
(A) is a partially enlarged view of a bonding portion. That is, the sealing material 2 applied to at least the portion of the sealing unnecessary region S is removed by the above-described unnecessary portion removal processing (see FIG. 2C). It is exposed. This exposed portion is slightly larger than the sealing unnecessary area S in consideration of the positioning error of the bonding wire 4,
The tip of the bonding wire 4 can be surely brought into contact with the electrode pad 11 even if there is some error.
【００２２】次に、図４（ｂ）に示すように、封止材料
２を加熱等によって溶融することで半導体素子１の外面
を封止材料２で覆うようにする。つまり、封止材料２の
溶融によって半導体素子１の上面に塗布された封止材料
２が半導体素子１の側面１ａまで回り込むようになる。
また、電極パッド１１上においては、封止材料２が溶融
することでボンディングワイヤー４の接続部分を囲む状
態となり、封止不要領域Ｓ以外の部分を完全に覆うよう
になる。例えば、図２（ａ）に示すスピンコーティング
の際に封止材料２を０．１ｍｍ程度の厚さで塗布した場
合には、封止材料２の溶融で半導体素子１の側面１ａに
は厚さ０．０７ｍｍ程度の封止材料２が回り込む状態と
なる。また、封止材料２をスピンコーティングによって
一様に塗布しているため、溶融後の封止材料２の厚さが
ほぼ均一となる。Next, as shown in FIG. 4B, the outer surface of the semiconductor element 1 is covered with the sealing material 2 by melting the sealing material 2 by heating or the like. That is, the melting of the sealing material 2 causes the sealing material 2 applied to the upper surface of the semiconductor element 1 to wrap around to the side surface 1 a of the semiconductor element 1.
Further, on the electrode pad 11, the sealing material 2 melts to surround the connection portion of the bonding wire 4 and completely covers the portion other than the sealing unnecessary region S. For example, when the encapsulating material 2 is applied to a thickness of about 0.1 mm during the spin coating shown in FIG. 2A, the encapsulating material 2 is melted and the side surface 1 a of the semiconductor element 1 is thickened. The sealing material 2 having a thickness of about 0.07 mm is in a state of wrapping around. Moreover, since the sealing material 2 is applied uniformly by spin coating, the thickness of the sealing material 2 after melting becomes substantially uniform.
【００２３】これによって、半導体素子１の外面でマウ
ント基材３との実装面および封止不要領域Ｓ以外の部分
を完全に封止材料２にて覆うことができ、半導体素子１
を湿気や外光から保護することができるようになる。な
お、封止材料２の溶融を行う際、封止材料２に所定の超
音波を与えることでその粘度を低下させ、半導体素子１
の外面への回り込みを容易にしかも確実に行うことがで
きるようになる。As a result, the outer surface of the semiconductor element 1 can be completely covered with the sealing material 2 except for the mounting surface with the mount base material 3 and the sealing unnecessary area S.
You will be able to protect it from moisture and outside light. When the sealing material 2 is melted, a predetermined ultrasonic wave is applied to the sealing material 2 to reduce its viscosity, and the semiconductor element 1
It becomes possible to easily and reliably wrap around the outer surface.
【００２４】次に、本発明の他の例を図５に基づいて説
明する。この実施例では、電極パッド１１に対応する部
分以外にも例えば光学的な入出力を行う光学素子領域１
２を封止不要領域Ｓとした半導体素子１を用いた例を示
している。Next, another example of the present invention will be described with reference to FIG. In this embodiment, in addition to the portion corresponding to the electrode pad 11, for example, the optical element region 1 for performing optical input / output is provided.
An example using the semiconductor element 1 in which 2 is the sealing unnecessary region S is shown.
【００２５】先ず、図５（ａ）に示す第１工程として、
少なくともこの封止不要領域Ｓを除く部分に封止材料２
を被着する処理を行う。このような封止材料２の被着状
態を構成するには、図２（ｃ）に示すようなレーザ光５
を用いた部分的な加熱蒸発でも、フォトリソグラフィー
法を用いて一括除去を行ってもいずれでもよい。First, as the first step shown in FIG.
At least the portion excluding the sealing unnecessary region S has the sealing material 2
Is applied. In order to form such an adhered state of the sealing material 2, a laser beam 5 as shown in FIG.
Either partial heating and evaporation using a method or batch removal using a photolithography method may be performed.
【００２６】次に、図５（ｂ）に示す第２工程として、
半導体素子１をマウント基材３上に実装した状態で各封
止不要領域（図５（ａ）参照）に対する所定処理を行
う。例えば、電極パッド１１に対応する封止不要領域Ｓ
にはボンディングワイヤー４の接続処理を行い、また光
学素子領域１２に対応する封止不要領域Ｓにはレンズ８
等の取り付け作業を行う。Next, as a second step shown in FIG.
Predetermined processing is performed on each sealing unnecessary region (see FIG. 5A) with the semiconductor element 1 mounted on the mount substrate 3. For example, the sealing unnecessary region S corresponding to the electrode pad 11
The bonding wire 4 is connected to the optical element region 12, and the lens 8 is formed in the sealing unnecessary region S corresponding to the optical element region 12.
And so on.
【００２７】その後、図５（ｃ）に示す第３工程として
封止材料２の溶融処理を行い、封止材料２が半導体素子
１の側面１ａまで回り込むようにする。すなわち、封止
材料２は例えば加熱溶融によって半導体素子１の外面を
広がっていき、封止不要領域Ｓであるボンディングワイ
ヤー４の接続位置とレンズ８およびマウント基材３との
実装面を除く全ての部分を覆う状態となる。このよう
に、電極パッド１１の部分以外にも光学素子領域１２等
の封止不要領域Ｓがあっても半導体素子１を保護するた
めのコーティングを行うことができる。After that, as a third step shown in FIG. 5C, the sealing material 2 is melted so that the sealing material 2 reaches the side surface 1a of the semiconductor element 1. That is, the sealing material 2 spreads on the outer surface of the semiconductor element 1 by, for example, heating and melting, and all of the sealing material 2 except for the bonding position of the bonding wire 4, which is the sealing unnecessary area S, and the mounting surface of the lens 8 and the mount substrate 3. The part is covered. In this way, coating for protecting the semiconductor element 1 can be performed even if there is a sealing unnecessary area S such as the optical element area 12 other than the electrode pad 11.
【００２８】図６は、本発明の適応例を説明する概略断
面図である。この例では、マウント基材３上に接近して
半導体素子１と受光素子６とが実装された例えば赤外線
受光モジュールにおいて本発明のコーティング方法を適
応した例を示している。赤外線受光モジュールでは、受
光素子６にて赤外線光を受け、半導体素子１にてその受
光信号を増幅する処理を行っている。受光素子６は、光
を受ける必要があるため封止材料２によるコーティング
が不要であるが、半導体素子１は赤外線等の外光によっ
て誤動作を起こす恐れがあるため外光遮断用の封止材料
２によるコーティングが必要となる。FIG. 6 is a schematic sectional view for explaining an application example of the present invention. In this example, an example in which the coating method of the present invention is applied to, for example, an infrared light receiving module in which the semiconductor element 1 and the light receiving element 6 are mounted close to each other on the mount substrate 3 is shown. In the infrared light receiving module, the light receiving element 6 receives infrared light, and the semiconductor element 1 amplifies the received light signal. Since the light receiving element 6 needs to receive light, the coating with the sealing material 2 is unnecessary. However, the semiconductor element 1 may malfunction due to external light such as infrared rays, and thus the sealing material 2 for blocking external light. Coating is required.
【００２９】このような場合において本発明のコーティ
ング方法を用いれば、半導体素子１の外面でマウント基
材３との実装面およびボンディングワイヤー４の接続位
置を除く全ての部分を封止材料２にて覆うことができ、
しかも近接して実装された受光素子６には一切封止材料
２が付着しないことになる。つまり、封止が必要な電子
部材と封止が不要な部品とが接近している場合であって
も確実に封止の必要な電子部材のみを封止材料２にて覆
うことができ、封止の不要な部品に影響を与えないよう
にすることができるようになる。In such a case, if the coating method of the present invention is used, the sealing material 2 covers all the outer surface of the semiconductor element 1 except the mounting surface with the mount substrate 3 and the connection position of the bonding wire 4. Can be covered,
Moreover, the sealing material 2 does not adhere to the light receiving elements 6 mounted close to each other. That is, even when the electronic member that needs to be sealed and the component that does not need to be sealed are close to each other, only the electronic member that needs to be sealed can be surely covered with the sealing material 2. It becomes possible to prevent the parts that do not need to be stopped from being affected.
【００３０】なお、本実施例においては半導体素子１か
ら成る電子部材を例としてコーティング方法の説明を行
ったが、本発明はこれに限定されない。例えば、集積回
路を備えていない抵抗器やコンデンサ等のチップ部品か
ら成る電子部材であっても同様な方法にてコーティング
を行うことが可能である。In the present embodiment, the coating method has been described by taking the electronic member formed of the semiconductor element 1 as an example, but the present invention is not limited to this. For example, it is possible to perform coating in the same manner even on an electronic member including a chip component such as a resistor or a capacitor which does not include an integrated circuit.
【００３１】[0031]
【発明の効果】以上説明したように、本発明の電子部材
のコーティング方法によれば次のような効果がある。す
なわち、本発明では、予め電子部材の外面で少なくとも
封止不要領域以外の部分に封止材料を被着しておき、こ
の電子部材をマウント基材上に実装した状態で所定の処
理を行った後に封止材料を溶融しているため、必要な部
分にのみ確実なコーティングを行うことが可能となる。As described above, the electronic member coating method of the present invention has the following effects. That is, in the present invention, a sealing material is applied in advance to at least a portion other than the sealing unnecessary area on the outer surface of the electronic member, and a predetermined process is performed with the electronic member mounted on the mount substrate. Since the sealing material is melted later, reliable coating can be performed only on a necessary portion.
【００３２】また、封止材料を電子部材の外面に一様に
塗布した後、所定の光を照射したり部分加熱することで
封止不要領域に塗布された封止材料を除去し、先と同様
に所定の処理を行って封止材料を溶融することで必要な
部分へのコーティング作業が容易となる。特に、マウン
ト基材上にコーティングの必要な電子部材とコーティン
グの不要な部品とが接近して実装されている場合には本
発明のコーティング方法が有効な手段となる。Further, after uniformly applying the sealing material to the outer surface of the electronic member, the sealing material applied to the unnecessary sealing area is removed by irradiating a predetermined light or partially heating. Similarly, a predetermined process is performed to melt the sealing material, which facilitates coating work on a necessary portion. In particular, the coating method of the present invention is an effective means when an electronic member that requires coating and a component that does not require coating are mounted close to each other on the mount substrate.
【図１】本発明を（ａ）〜（ｃ）の工程順に説明する概
略断面図である。FIG. 1 is a schematic cross-sectional view illustrating the present invention in the order of steps (a) to (c).
【図２】具体例を説明する図（その１）で、（ａ）がス
ピンコーティング、（ｂ）が硬化、（ｃ）が不要部分の
除去を示している。FIG. 2 is a diagram (part 1) illustrating a specific example, in which (a) shows spin coating, (b) shows curing, and (c) shows removal of unnecessary portions.
【図３】具体例を説明する図（その２）で、（ａ）がダ
イシング、（ｂ）がダイボンディング、（ｃ）がワイヤ
ーボンディングを示している。FIG. 3 is a diagram (part 2) explaining a specific example, in which (a) shows dicing, (b) shows die bonding, and (c) shows wire bonding.
【図４】部分拡大図であり、（ａ）がボンディング部、
（ｂ）が半導体素子端部を示している。FIG. 4 is a partially enlarged view of FIG.
(B) shows the end of the semiconductor element.
【図５】本発明の他の例を（ａ）〜（ｃ）の工程順に説
明する概略断面図である。FIG. 5 is a schematic cross-sectional view illustrating another example of the present invention in the order of steps (a) to (c).
【図６】本発明の適応例を説明する概略断面図である。FIG. 6 is a schematic cross-sectional view illustrating an application example of the present invention.
【図７】従来例を説明する概略断面図である。FIG. 7 is a schematic cross-sectional view illustrating a conventional example.
１ 半導体素子 １ａ 側面 ２ 封止材料 ３ マウント基材 ４ ボンディングワイヤー ５ レーザ光 １０ ウエハ １１ 電極パッド Ｓ 封止不要領域 DESCRIPTION OF SYMBOLS 1 Semiconductor element 1a Side surface 2 Sealing material 3 Mount base material 4 Bonding wire 5 Laser light 10 Wafer 11 Electrode pad S Sealing unnecessary area
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/31 Ｈ０５Ｋ 3/28 Ｇ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 23/31 H05K 3/28 G
Claims (4)
マウント基材上に実装した状態で該電子部材を保護用の
封止材料にてコーティングする方法であって、 前記電子部材の外面で少なくとも前記封止不要領域を除
く部分に前記封止材料を被着する第１の工程と、 前記電子部材を前記マウント基材上に実装して前記封止
不要領域に対する所定の処理を行う第２の工程と、 前記封止材料を溶融することにより前記電子部材の外面
で前記マウント基材との実装面および前記封止不要領域
以外の全ての部分を該封止材料にて覆う第３の工程とか
ら成ることを特徴とする電子部材のコーティング方法。1. A method of coating an electronic member having a predetermined unnecessary sealing region on a mount base material with a protective sealing material, the method comprising coating the electronic member with an outer surface of the electronic member. A first step of depositing the sealing material on at least a portion excluding the sealing unnecessary area, and a second step of mounting the electronic member on the mount base material and performing a predetermined process on the sealing unnecessary area And a third step of melting the encapsulating material to cover all parts of the outer surface of the electronic member other than the mounting surface of the mount base material and the unneeded sealing area with the encapsulating material. A method for coating an electronic member, comprising:
場合において、 前記第１の工程は、前記電子部材の外面に前記封止材料
を一様に塗布した後、所定の光を該封止材料に照射する
ことで少なくとも前記封止不要領域に塗布された該封止
材料を除去することを特徴とする請求項１記載の電子部
材のコーティング方法。2. When a photosensitive material is used as the sealing material, in the first step, the sealing material is uniformly applied to the outer surface of the electronic member, and then a predetermined light is sealed. The method for coating an electronic member according to claim 1, wherein at least the sealing material applied to the sealing unnecessary region is removed by irradiating the sealing material.
た場合において、 前記第１の工程は、前記電子部材の外面に前記封止材料
を一様に塗布した後、少なくとも前記封止不要領域を部
分加熱して塗布された該封止材料を蒸発させることを特
徴とする請求項１記載の電子部材のコーティング方法。3. In the case of using a thermoplastic resin as the sealing material, in the first step, at least the sealing unnecessary area is formed after the sealing material is uniformly applied to the outer surface of the electronic member. 2. The method for coating an electronic member according to claim 1, wherein the coating material is partially heated to evaporate the applied sealing material.
溶融する際、該封止材料に対して超音波を与えることを
特徴とする請求項１から請求項３のうちいずれか一つに
記載の電子部材のコーティング方法。4. The ultrasonic wave is applied to the sealing material when the sealing material is melted in the third step, according to any one of claims 1 to 3. A method for coating an electronic member as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11436094A JP3221230B2 (en) | 1994-04-28 | 1994-04-28 | Electronic component coating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11436094A JP3221230B2 (en) | 1994-04-28 | 1994-04-28 | Electronic component coating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07302808A true JPH07302808A (en) | 1995-11-14 |
| JP3221230B2 JP3221230B2 (en) | 2001-10-22 |
Family
ID=14635781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11436094A Expired - Fee Related JP3221230B2 (en) | 1994-04-28 | 1994-04-28 | Electronic component coating method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3221230B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006196701A (en) * | 2005-01-13 | 2006-07-27 | Oki Electric Ind Co Ltd | Manufacturing method for semiconductor device |
| US7224044B2 (en) | 2002-01-31 | 2007-05-29 | Fujitsu Hitachi Plasma Display Limited | Semiconductor chip mounting substrate and flat display |
| JP2015516298A (en) * | 2013-01-08 | 2015-06-11 | エイチズィーオー・インコーポレーテッド | Removal of selected protective coating from substrate |
| US9559514B2 (en) | 2012-01-10 | 2017-01-31 | Hzo, Inc. | Methods, apparatuses and systems for monitoring for exposure of electronic devices to moisture and reacting to exposure of electronic devices to moisture |
| US9894776B2 (en) | 2013-01-08 | 2018-02-13 | Hzo, Inc. | System for refurbishing or remanufacturing an electronic device |
| US10449568B2 (en) | 2013-01-08 | 2019-10-22 | Hzo, Inc. | Masking substrates for application of protective coatings |
| US10541529B2 (en) | 2012-01-10 | 2020-01-21 | Hzo, Inc. | Methods, apparatuses and systems for sensing exposure of electronic devices to moisture |
-
1994
- 1994-04-28 JP JP11436094A patent/JP3221230B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7224044B2 (en) | 2002-01-31 | 2007-05-29 | Fujitsu Hitachi Plasma Display Limited | Semiconductor chip mounting substrate and flat display |
| JP2006196701A (en) * | 2005-01-13 | 2006-07-27 | Oki Electric Ind Co Ltd | Manufacturing method for semiconductor device |
| US9559514B2 (en) | 2012-01-10 | 2017-01-31 | Hzo, Inc. | Methods, apparatuses and systems for monitoring for exposure of electronic devices to moisture and reacting to exposure of electronic devices to moisture |
| US10541529B2 (en) | 2012-01-10 | 2020-01-21 | Hzo, Inc. | Methods, apparatuses and systems for sensing exposure of electronic devices to moisture |
| JP2015516298A (en) * | 2013-01-08 | 2015-06-11 | エイチズィーオー・インコーポレーテッド | Removal of selected protective coating from substrate |
| US9403236B2 (en) | 2013-01-08 | 2016-08-02 | Hzo, Inc. | Removal of selected portions of protective coatings from substrates |
| US9656350B2 (en) | 2013-01-08 | 2017-05-23 | Hzo, Inc. | Removal of selected portions of protective coatings from substrates |
| US9894776B2 (en) | 2013-01-08 | 2018-02-13 | Hzo, Inc. | System for refurbishing or remanufacturing an electronic device |
| US10449568B2 (en) | 2013-01-08 | 2019-10-22 | Hzo, Inc. | Masking substrates for application of protective coatings |
| US10744529B2 (en) | 2013-01-08 | 2020-08-18 | Hzo, Inc. | Materials for masking substrates and associated methods |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3221230B2 (en) | 2001-10-22 |
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