JPH02123599A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To fix rising time for boosted voltage by making the frequency of an oscillation circuit variable when the title nonvolatile semiconductor memory is composed of the oscillation circuit to output an oscillation signal having a constant frequency and a boosting circuit to be driven by the output of the oscillation circuit. CONSTITUTION:In reading out, since a W/E control signal becomes an H level, the level of V2 is fixed, and no boosted voltage is generated. In byte writing and reproducing, the W/E control signal becomes an L level, and a B/C control signal becomes the H level. Consequently, since the output of a clock gate type inverter 12 becomes a high impedance state, and a circuit 13 works as an inverter, an oscillating operation for 6 steps of the inverter is generated in an oscillation circuit 2, and its output V2 becomes constant. On the other hand, in chip writing and erasing, since the number of the steps of the inverter becomes different from that in the above-mentioned byte writing and erasing, while the voltage V2 is not changed, its oscillation frequency becomes different. thus, in the chip writing and erasing, the number of the steps of the inverter is decreased, and the rising time of the boosted voltage is fixed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention is directed to electrically writable and erasable read-only memory among non-volatile informational memories, that is, E"PR.
The present invention relates to a booster circuit for generating a high voltage necessary for writing and erasing an OM (hereinafter referred to as E2PROM).

[Conventional technology I For writing and erasing data in E2FROM, supply amount #i
A higher voltage (15V to 25V) is required.

FIG. 3 is a diagram of a conventional booster circuit. 1 is a booster circuit for generating a boosted voltage, a so-called charge pump circuit (for example, reference JOURNAL OF 5OLID 5T
ATE CIRCUITS, VOL, 5C-16,
NO, 3 JUNE 1981 A1.5V Single
e-3uply 0neTransistor 0M
O5EEPROM description), 3 is its load capacity,
Reference numeral 2 denotes an oscillation circuit that oscillates at a constant frequency for supplying a signal for driving the booster circuit l. The second oscillation circuit is
It consists of inverters 5 to 1O and N0R4. N0R
One input of 4 is a write/erase control signal (hereinafter referred to as Vl/
E control signal) is manually operated. Also, here the inverter is set to 6 stages, but this is not limited to 6 stages, any number of stages may be used as long as it is an even number, and N0R4 also has W/
It may be NAND depending on the logic of the E control signal.

To explain the operation, when reading, the W/E system is used (the wholesale signal is at H level, so the output v2 of the oscillation circuit 2 is fixed at L level, the booster circuit l is not driven and no boosted voltage is generated, and when writing and erasing, the W/E system is used). Since the /E control signal becomes L level, oscillation occurs in the 1 oscillation circuit 2, and its output V
, an oscillation signal of a constant frequency is output. Therefore, the booster circuit 1 is driven and a boosted voltage is generated.

[Problems to be Solved by the Invention] In the conventional booster circuit, since the frequency of the oscillation signal of the single oscillation circuit 2 is constant, the boosted voltage supply capability of the booster circuit 1 is constant. Therefore, due to the difference in the size of the load capacitance 3 during byte-by-byte writing and erasing of the E2PROM and when writing and erasing the entire chip at once, a difference occurred in the rise time of the boosted voltage. In other words, if the frequency of the oscillation signal is set to match byte-by-byte writing and erasing, the load capacity increases when writing and erasing the entire chip at once, resulting in a longer rise time (which leads to an increase in writing and erasing times). In addition, if the frequency of the oscillation signal is set to match the batch writing and erasing of the entire chip, the load capacity will be reduced for byte-by-byte writing and erasing, which will shorten the rise time and increase the stress of applying high voltage to memory cells. This led to a decrease in reliability.

Therefore, in order to solve such problems, the present invention
The purpose is to make the rise time of the boosted voltage constant both when writing and erasing in byte units of OM and when writing and erasing the entire chip at once.

[Means for Solving the Problems] A nonvolatile semiconductor memory device of the present invention includes an oscillation circuit that outputs an oscillation signal with a constant frequency rF1iJ, and a booster circuit that is driven by the output of the oscillation circuit. , the oscillation circuit is characterized in that the oscillation circuit receives a control signal as an input and is capable of variable frequency of an oscillation signal.

[Function] According to the above configuration of the present invention, the frequency of the oscillation signal is varied between E2PROM byte writing and erasing and chip writing and erasing, that is, the frequency is decreased during byte writing and erasing. By increasing the frequency during chip writing and erasing, the charge pump's ability to supply boosted voltage can be varied λ and the rise time of the boosted voltage can be made constant.

[Example 1 Figure 1 shows the first example of the present invention. Here, the same symbols as in the conventional example are the same. 11 is an inverter, 12
．． 13 is a clocked gate type inverter, and a signal for byte write/erase, chip write/erase, and switching λ control (hereinafter referred to as B/C control signal) is used for the clock.

To explain the operation, when reading, the W/E control signal is at H level as in the explanation of the conventional technology, so (2) is fixed at L level and no boosted voltage is generated.When writing and erasing bytes, the W/E control signal is at H level. L level, B/C1li
The lllll signal becomes H level. Therefore, the output of the clocked gate type inverter 12 is in a high impedance state, and since the clocked gate inverter 13 works as an inverter, one oscillation circuit 2 generates an oscillation operation equivalent to six stages of inverters, and its output V2 outputs an oscillation signal of a constant frequency. be done. During chip writing and erasing, the W/E control signal is at L level and the B/C control signal is at L level. Therefore, the output of the clocked gate type inverter 13 is in a high impedance state, 1
2 works as an inverter, the oscillation circuit 2 generates an oscillation operation equivalent to four stages of inverters, and an oscillation signal of a constant frequency is outputted as its output v2. Output in either case
Since an oscillation signal is generated in , the booster circuit 1 is driven and a boosted voltage is generated.However, since the number of inverter stages in the oscillation circuit 2 differs between byte write and erase and chip write and erase, the oscillation The frequency of the signals is also different. As a result, a difference arises in the boosted voltage supply capability of the booster circuit l.

Since the load capacitance 3 is small during byte writing and erasing, the boosting voltage supply capability of the boosting circuit 1 may be low, so the number of inverter stages is increased in order to reduce the frequency of the generated @ signal. On the other hand, during chip writing and erasing, the load capacitance f13 is large, so it is necessary to increase the boost supply capability of the booster circuit l, so the number of inverter stages is reduced in order to increase the frequency of the oscillation signal. In this way, the rise time of the boosted voltage is made constant. Here, the explanation was given by switching the number of inverter stages to 4 stages and 6 stages, but in reality, in order to keep the rise time constant, the load capacitance 3 and the boost voltage supply capacity of the charge pump 1 are taken into consideration. The oscillation frequency is determined, and the number of stages of impark is not limited to the number of stages of this embodiment, but may be set appropriately in accordance with the oscillation frequency.

FIG. 2 shows a second embodiment of the invention. Here, the same symbols as in the conventional example are the same. N1 to N6 are Nch transistors, and Cl-C6 is the load capacitance of the inverter.

Further, a B/C control signal is input to the gates of the transistors N1 to N6.

To explain the operation, when writing and erasing bytes, +;l/
The E control signal becomes L level and the B/C control signal becomes H level. Therefore, the transistors N1 to N6 are turned on, and the load capacitances C1 to C6 are loaded to the imparks 5 to 1O, respectively, so the oscillation frequency becomes small. During chip writing and erasing, the B/C control signal goes to L level. Become.

Therefore, the transistors N1-N6 are turned off, the load capacitances Cl-C6 are not loaded on the imparks 5-10, respectively, and the oscillation frequency increases. In this way, the first
Similarly to the embodiment, it is possible to change the boost voltage supply capability of the booster circuit 1 and make the rise time of the boost voltage constant.

As explained above using Examples 1 and 2, the essence of the present invention is that by changing the frequency of the oscillation signal of the oscillation circuit 1, the boost voltage supply capability of the boost circuit 1 is changed, and its rise time is changed. Therefore, other methods may be used to change the frequency of the oscillation signal, and
The rise time of the boosted voltage does not necessarily have to be the same during bit write/erase and chip write/erase, and may be set to any desired time.

[Effects of the Invention] As described above, according to the present invention, by changing the frequency of one oscillation signal, it is possible to make the rise time of the boosted voltage constant.

This is particularly effective for controlling the data writing and erasing time of E'' FROM and improving the reliability of memory cells.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a second embodiment of the present invention. FIG. 3 is a circuit diagram showing a conventional booster circuit. l・・・・・ 2 ・ ・ ・ ・ 3・・・・・ ４　・　・・・ 5～l　1　・ l 2, l 3 14 ・ ・ ・ 15 ・ ・ ・ l　6　・　・・・ N1~N6 boost circuit oscillation circuit load capacity OR Inpark clocked gate type inverter W/E fri control signal ・B/C control signal ・Boost circuit output Net+transistor Cl-C6 load capacity Below Up

Claims (1)

[Claims] In a nonvolatile semiconductor memory device consisting of an oscillation circuit that outputs an oscillation signal of a constant frequency and a booster circuit that is driven by the output of the oscillation circuit, the oscillation circuit receives a control signal as input and the frequency of the oscillation signal is variable. A nonvolatile semiconductor memory device characterized by being an oscillation circuit.