JPH011472A - boost circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention generates a high voltage necessary for writing and erasing an electrically old erasable read-only memory, EEPROM (hereinafter referred to as EEPROM). This invention relates to a booster circuit.

[Conventional technology]

Writing and erasing data in an EEPROM requires a voltage higher than the supply voltage (15V to 20V). FIG. 4 is a diagram of a conventional booster circuit, which has a so-called charge pump type configuration. Here, NO, Nl...Nn is Nc
h) Transistor, C1, C2...Cn is capacitance, Φ, ■
is a clock signal, and ■ is a reverse phase clock signal of Φ. The operation of this circuit is to increase the voltage at the drain of the transistor using a clock signal and capacitance, thereby sequentially transferring charge to the drain of the next transistor. It outputs high voltage.

[Problem that the invention seeks to solve]

In conventional booster circuits, the boosted voltage is fixed at a certain constant value. Therefore, the voltage applied when writing and erasing data in the EEPROM is also the same. For example, if the voltage applied during erasing requires a higher voltage than the voltage applied during writing, set the boosted voltage to the voltage applied during erasing mode. There is a problem in that the applied voltage becomes too high during writing, increasing stress on the element. Alternatively, if the boosted voltage is set as the applied voltage during writing, the applied voltage during erasing becomes too low, and erasing is not performed sufficiently.
In order to avoid this, there were problems such as having to apply a high voltage for a long time. Therefore, in order to solve such problems, the present invention aims to make the boost voltage of the booster circuit multiple voltages. do.

[Means for solving problems]

The booster circuit of the present invention includes a transistor and a capacitor, the gate and drain of the transistor are connected to the first terminal of the capacitor, and the second terminal of the capacitor is supplied with a clock signal, as one stage, In a circuit in which a plurality of transistors are connected in cascade by connecting the source of the transistor to the drain of the next transistor, supply of the clock signal to an arbitrary capacitor is controlled.

[Effect]

According to the above configuration of the present invention, since the boosting operation of any stage is stopped, the number of boosting stages changes, so that the boosted voltage can be set to a plurality of voltages.

〔Example〕

FIG. 1 shows a first embodiment of the present invention. Here, the same symbols as in the conventional example are the same. 1.2 is NAND circuit, 3
．． 4 is an inverter circuit. A control signal is input to each of the NAND circuits 1 and 2.

Now, the operation when the control signal is H will be explained. In this case, the output of the inverter circuit 3 is a clock signal in phase with Φ1,
The output of the inverter circuit 4 is a clock signal having the same phase as TI. Now, when the clock signal Φl changes from L to H, the transistors Nl, N3...Nn-1 are turned on instantaneously through capacitors ic1, C3...C'n-1, so the transistors N2, N4 , . . . Charge is sent to the drain of Nn. Also, at this time, TI is at L, and transistor N2. N4...Nn is in the off state, and the charge does not flow in the opposite direction (toward the supply voltage VDD side).Subsequently, when TI is changed from L to H, the transistor N
2, N4...Nn drain voltages are boosted, and charges are sent to the drains and output terminals of transistors N3, N5...Nn-1. In this way, the output voltage is increased while the charge is sent to the output terminal side.

The same symbols as in the previous example are the same. 1 and 2 will explain the operation when the 8th order control signal is L. In this case, since the output of inverter circuit 3.4 remains fixed at L, transistors Nn-1 and Nn are not boosted. Therefore, a voltage lower than the output voltage when the control signal is H by the sum of the threshold voltages of transistors Nn-1 and Nn is output.

FIG. 2 shows a second embodiment of the invention. When the control signal is H, clock signals Φ1 and ■1 are output to the outputs of the inverter circuit and 3.4, respectively, so the boost voltage of N stages of transistors is output, but when the control signal is L, Since the output of the inverter circuit 3.4 is fixed at L, the transistor NlN2 does not perform a boosting operation, and the boosted voltage from the transistor N3, that is, the boosted voltage of N-2 stages of transistors is output.

FIG. 3 shows a third embodiment of the invention. In this case, there are two control signals, and the explanation of the first and second embodiments will make it clear that four types of output voltages can be obtained by combining the H and L levels of these two control signals. .

As described above using the embodiments 1.2.3, the key feature of the present invention is to control the supply of clock signals to arbitrary capacitances, thereby changing the number of boost stages of the boost circuit and increasing the output voltage to multiple levels. Therefore, any circuit configuration may be used as long as it does not deviate from this essence.For example, in Example 1
．． The number of transistors for stopping the boost operation described in 2.3 and the position of the stages can be set arbitrarily. Alternatively, it is also possible to combine Example 1.2. Furthermore, it is also possible to stop the voltage boosting operation of the transistor by fixing the supply signal to the capacitor at H instead of L, or by leaving it open.

In addition, we have explained the boosting operation in a direction higher than the supply power supply voltage VDD by assuming that the transistors NO, Nl, . . . Nn are Nch transistors, but the transistors Pc
It is easy to understand that the same effect can be obtained for boosting operation in a direction (one direction) lower than the supply power supply voltage as h.

〔Effect of the invention〕

As described above, according to the present invention, by changing the number of boosting stages of the boosting circuit, it is possible to set the boosted voltage of the boosting circuit to a plurality of voltages.

This is extremely effective especially in responding to the difference in boosting voltage application for data writing and erasing of EEFROM.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a second embodiment of the present invention. FIG. 3 is a circuit diagram showing a third embodiment of the present invention. FIG. 4 is a circuit diagram showing a conventional booster circuit. NO, Nl・7・Nn, NO'-Nch) transistor. 1.2.5.6 - NAND circuit, 3.4.7.8 - Inverter circuit, ΦI, TI - clock signal. Applicant: Seiko Epson Co., Ltd. Representative Patent Attorney Tsutomu Mogami and 1 other person 11 i41 Bond λ Gaku

Claims (1)

[Claims] One stage consists of a transistor and a capacitor, the gate and drain of the transistor are connected to the first terminal of the capacitor, and the second terminal of the capacitor is supplied with a clock signal, and the source of the transistor is connected to the next stage. 1. A booster circuit which controls the supply of the clock signal to an arbitrary capacitor in a circuit in which a plurality of transistors are connected in cascade by being connected to the drains of the transistors.