JPH0696593A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a writing or erasing time while suppressing power consumption by driving a level shifter corresponding to a word line selected by a pre- decoder, and boosting a potential of a word line. CONSTITUTION:A booster 102 steps up a power source voltage VCC to generate a voltage VPP. When the voltage VPP exceeds a predetermined voltage, a VPP detector 106 sets a detection signal KVPP to 'H' to drive a driver of a row decoder 103. Further, a column decoder 105 selects a memory cell array 104 having memory cells to be selected by the decoder 103 and output data. Here, the decoder 103 has a pre-decoder 115, a level shifter 116 and a transmitter 117. The voltage VPP is supplied to the decoder 103, etc., to drive the shifter 116 corresponding to the word line selected by the pre-decoder 115 and to step up the word line to the potential VPP through the transmitter 117. Then, a time required for writing or erasing can be shortened while suppressing power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. The present invention relates to a non-volatile semiconductor memory device that requires a boosted voltage higher than a power supply voltage for writing and erasing data and generates this boosted voltage by a booster circuit.

[0002]

2. Description of the Related Art Generally, a high voltage of 10 V or higher is required for writing and erasing data in a nonvolatile semiconductor memory device. For this purpose, it has been used to take in these voltages from the outside of the chip, as described in detail in Japanese Patent Laid-Open No. 130798/1990. There is also an example in which a booster circuit is mounted inside the chip in order to realize an external single power source. An example in which a booster circuit is mounted inside the chip to realize an external single power supply will be described below.

A conventional internal boosting type nonvolatile semiconductor memory device has a structure shown in FIG. 23. That is, a clock generation circuit 1001 that generates a clock signal (RING) of a predetermined cycle at the time of writing (Prog) and erasing (Erase), and a booster circuit 1002 that boosts the power supply voltage Vcc to generate the boosted power supply voltage Vpp. A row decoder 1 including a limiter circuit 1006 configured by a Zener diode or the like to keep the boosted power supply voltage Vpp at a constant value, and a drive circuit driven by the boosted power supply voltage Vpp.
003. Further, it goes without saying that a memory cell array 1004 in which memory cells selected by the row decoder 1003 are arranged in a matrix and a column decoder 1005 for selecting output data are provided.
This is because the arrangement structure of the memory cell array is NOR type, NA
It does not relate to any of the ND types. The operation at this time is shown in FIG. 24. When the Prog signal becomes “H”, the clock generation circuit 1001 operates to generate the clock signal RING. Driven by this clock signal RING, the booster circuit 1002 boosts the voltage to generate a boosted power supply voltage Vpp (for example, 20V in the case of a NAND type EEPROM) from the power supply voltage Vcc. Data writing to the memory cell is performed using this boosted power supply voltage.

However, as shown in FIG. 24, it takes some time for the booster circuit 1002 to complete boosting. This time actually controls the writing time or erasing time of the nonvolatile semiconductor memory device. As one of the methods for shortening the boosting time, it is conceivable to set the supply capability of the boosting circuit itself to be large. However, if the supply capacity of the booster circuit is increased, the limiter circuit 10 will be activated after the boosting is completed.
A large current flows through 06. Therefore, useless power consumption increases.

[0005]

As described above, in the conventional nonvolatile semiconductor memory device with a built-in booster circuit, there is a problem that power consumption becomes large when the write time and the erase time are attempted to be shortened. . An object of the present invention is to provide a non-volatile semiconductor memory device that eliminates the above-mentioned drawbacks and shortens the write time and erase time while suppressing power consumption.

[0006]

In order to achieve the above object, according to the present invention, boosting means for boosting a power supply voltage to generate a boosted output voltage, and sensing means for sensing the boosted output voltage and outputting a sensing signal. And a high voltage generating circuit including a boost control unit that controls the boost unit according to the detection signal.

Further, boosting means for driving the power supply voltage to generate a boosted output voltage driven by a clock signal, detecting means for outputting a detection signal of a predetermined level when the boosted output voltage is equal to or lower than a predetermined voltage, and the detection signal. There is provided a semiconductor memory device comprising a high voltage generating circuit comprising a clock signal generating means for generating the clock signal when is at a predetermined level.

[0008] Further, boosting means driven by a clock signal to boost a power supply voltage to generate a boosted output voltage, detection means for outputting a detection signal when the boosted output voltage is equal to or higher than a predetermined voltage, and, in accordance with the detection signal, There is provided a semiconductor memory device comprising a high voltage generating circuit including a clock signal generating means for generating the clock signals having different cycles.

Further, boosting means for boosting the power supply voltage to generate a boosted output voltage, limiter means for limiting the boosted output voltage to a predetermined voltage, and detecting means for detecting a current flowing through the limiter means and outputting a detection signal. And a high voltage generating circuit including a boost control unit that controls the boost unit according to the detection signal.

Further, it comprises a plurality of memory cells to be written or erased by applying a voltage higher than a power supply voltage, and a decoder circuit driven by the boosted output voltage and applying a voltage to the plurality of memory cells. The above-mentioned semiconductor memory device is provided.

Further, a booster circuit for boosting a power supply voltage to generate a boosted output voltage and a booster output voltage connected to a plurality of memory cells to be written or erased by applying a voltage higher than the power supply voltage. A decoder circuit to be driven, an external pad for introducing a voltage higher than the power supply voltage, a high voltage detection means for outputting a detection signal when the voltage applied to the external pad is equal to or higher than a predetermined voltage, and the detection signal A semiconductor memory device is provided, which comprises: a transmission unit that responds to transmit the voltage applied to the external pad to the decoder circuit.

[0012]

When the means provided by the present invention is used, a large current does not flow through the limiter circuit as in the conventional case even if the capacity of the boosting means is large, that is, the current driving capability is large. This is because the detection means detects an increase in the boosted output voltage more than necessary, and if the boosted output voltage rises too much, a detection signal is sent to the boosting control means, and the boosting control means controls the boosting operation. Therefore, boosting can be performed at high speed. Therefore, writing and erasing can be performed at high speed while suppressing power consumption.

Also, an external pad, a high voltage detecting means for outputting a detection signal when the voltage applied to the external pad is a predetermined voltage or more, and a voltage applied to the external pad in response to the detection signal to a decoder circuit. By including the transmitting means for transmitting, when a high voltage is applied to the external pad, this voltage is introduced into the decoder circuit, and when the high voltage is not applied, the high voltage is boosted from the power supply voltage by the internal booster circuit. Can be generated. Therefore, the write current can be reduced, the bit line charging time (pre-charge time) can be shortened, and the stability with respect to the fluctuation of the external high-voltage power supply can be improved.

[0014]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of the first embodiment of the present invention. That is, at the time of writing (Prog) and erasing (Erase), a clock signal (RIN
G), a clock generation circuit 101, a booster circuit 102 that boosts the power supply voltage Vcc to generate a boosted power supply voltage Vpp, and a detection signal KVpp that goes "H" when the boosted power supply voltage Vpp exceeds a predetermined voltage Vpp. It includes a detection circuit 106 and a row decoder 103 including a drive circuit driven by the boosted power supply voltage Vpp. Further, a memory cell array 104 in which memory cells selected by the row decoder 103 are arranged in a matrix, a column decoder 105 for selecting output data, and the like are provided.

FIG. 2 shows an example of the booster circuit 102. Although the example of the four-stage charge pump circuit is shown here, it is actually realized by a dozen or more stages of charge pump circuits. In order to increase the boosting efficiency, it is desirable that the MOS transistor used in the charge pump circuit has a threshold value of 0V.

FIG. 3 shows an example of the Vpp detection circuit 106. The Vpp detection circuit may use a normal resistance division, or may use a high threshold MOS transistor. Also,
The level shift may be performed using a Zener diode.

FIG. 4 shows an example of the clock signal generating circuit 101. That is, the RC delay circuit 111 and the inverter 112 are connected in an odd-numbered ring shape. Although not shown, a P-type MOS transistor and an N-type MO
An S-transistor connected in parallel with each gate connected to “L” and “H” is a resistance element
A type MOS transistor in which the source and drain are commonly grounded serves as a capacitive element, and an RC delay circuit is formed by both. Furthermore, in order to control the oscillation, Prog, Er
control input terminals for the case and KVpp are provided. As a result, at the time of writing (Prog is “H”) and at the time of erasing (Erase is “H”), the clock signal RING is output only when KVpp is “L”, and at other times, the clock signal does not oscillate. .

FIG. 5 shows an example of the row decoder 103 and the memory cell array 104. The row decoder 103 includes a predecoder 115, a level shift circuit 116, and a transmission circuit 117. The memory cell array 104 has N
A part of the AND type memory cell is shown. However, the present invention can be applied not only to the NAND type but also to a nonvolatile semiconductor memory device having a NOR type memory cell structure.

Next, the voltage applied to the memory cell will be described. An equivalent circuit of the cell part of the NAND type EEPROM is shown in FIG. This has four floating gate type memory cells MC connected in series in four stages, the drain side is connected to a bit line BL via a selection transistor Q1, and the source side is connected to a source line via a selection transistor Q2. SG1 is used as the gate of the selection transistor Q1, and CG1 and CG2 are used as the control gates of the memory cell MC.
, CG3, CG4, and SG2 is connected to the gate of the selection transistor Q2. When writing to such a memory cell, the bit line is set to 0V, SG1
Is applied to "H", SG2 is applied to "L", CG corresponding to the write cell is applied with 20V, and control gates of other cells are applied with 10V. When erasing is performed on all the cell groups, SG1 is applied to "L", SG2 is applied to "H", 0V is applied to all CGs, and 20V is applied to the substrate. In the case of the NAND type EEPROM, the current consumption is small because both writing and erasing are performed by the tunnel current. Therefore, it is possible to simultaneously write and erase a large number (for example, 2000) of memory cells even by the booster circuit mounted inside the chip.

In the case of a NOR type EEPROM, a gate negative voltage type structure is required to enable erasing using the internal booster circuit. That is, writing is performed by injecting electrons by hot carriers with the source grounded, the drain 5 V (Vcc), the gate 12 V, and erased with the source 5 V, the drain open, and the gate -10 V. In this case, since erasing uses a tunnel current and consumes a small amount of current, a large number of memory cells can be simultaneously erased even by a booster circuit mounted inside the chip. In this way, when the output voltage Vpp of the row decoder 103 is set to 20V, 10V, 12V, and -10V, respectively, NAND type and NOR type can be applied without distinction. However, in the case of the gate negative voltage type and setting Vpp to −10 V, the booster circuit 102 or the step-down circuit, the Vpp detection circuit 106,
Some changes are required to the configurations of the level shift circuit 116 and the decoder circuit 103.

The operation of the first embodiment will be described next. FIG. 7 shows the operation waveform. When a program command is input from the outside of the chip via an I / O terminal (not shown), the command decoder decodes the program command and outputs it at time t.
At 0, the Prog signal is raised to "H". As a result, the clock signal generation circuit 101 outputs the clock signal RING having a predetermined frequency, and the booster circuit 102 starts operating by this clock signal. When Vpp, which is the output of the booster circuit, rises to about 20V at time t1, the Vpp detection circuit 106
Detects this, and sets KVpp to "H". Upon receiving this signal, the clock signal generation circuit 101 stops oscillation. As a result, the booster circuit 102 stops boosting, and Vpp starts to fall according to the amount of current in the load. Vpp drops at time t2,
KV which is the output of the Vpp detection circuit 106 when the predetermined potential is reached
When pp becomes "L", the clock generation circuit 101 starts oscillation again. As a result, the booster circuit 102 starts boosting again. At time t3, Vpp which is the output of the booster circuit rises to about 20V again as at time t1, and the Vpp detection circuit 106 detects this and sets KVpp to "H". Upon receiving this signal, the clock signal generation circuit 101 stops oscillation again. As a result, the booster circuit 102 stops boosting and V
pp starts to fall again according to the amount of load current. Time t4
Vpp drops again to reach a predetermined potential, and Vpp detection circuit 1
When KVpp which is the output of 06 becomes "L", the clock generation circuit 101 starts oscillation again. As a result, the booster circuit 1
02 starts boosting again. In this way, the booster circuit 102
Intermittently repeats boosting / stopping, and as a result, Vpp is maintained at around 20V without using a limiter circuit as in the conventional example. Further, it is possible to prevent unnecessary power consumption because the booster circuit is stopped at the time when the predetermined voltage is reached.

The boosted power supply voltage Vpp thus boosted is supplied to the row decoder 103 and the like, and the predecoder 115 is supplied.
The level shift circuit 116 corresponding to the word line selected by is driven, and the word line is boosted to the Vpp potential via the transmission gate 117. As a result, writing or erasing is performed. As mentioned above, the memory cell is NOR
Type and NAND type, the effect of the present invention can be expected.

As described above, according to the configuration of the first embodiment, there is no current path from the boosted power supply voltage Vpp except for the row decoder 103 acting as a load, so that the power consumption can be reduced. . In particular, since the write and erase voltages in the nonvolatile semiconductor memory device are 10 V or more, the power consumption saved by removing the limiter circuit is large. Further, the circuit configuration described above virtually eliminates the limitation of the capacity of the booster circuit, and a large-capacity booster circuit can be mounted. Therefore, the boosting time is shortened, and the writing and erasing times are shortened.

Further, the conventional nonvolatile semiconductor memory device is equipped with a booster circuit having a considerably large capacity within the limitation of the capacity of the booster circuit described above. This is because the load resistance, which changes rapidly in terms of time, is equipped with a circuit that has a considerable margin assuming the worst case so that Vpp does not drop. However, in the case where the booster circuit that completely follows the load is provided as in the present invention, the booster circuit is almost stopped after the current flowing through the load becomes very small, such as after boosting the word line. Become. Therefore, the present invention contributes to the reduction of power consumption.

The circuit structure of the present invention can be expected to be effective for both the NOR type and the NAND type, but a great effect can be expected when applied to the NAND type EEPROM. That is, NA
In the ND type, it is necessary to set the threshold voltage of the memory cell within a predetermined range during normal writing. Here, intelligent writing is performed in which writing is finely divided. In this case, however, writing and reading are frequently repeated, so that the effect of the present invention for shortening the writing time appears to be enlarged. Therefore, when the present invention is applied to the NAND type EEPROM, a further effect of reducing the writing time can be expected. Subsequently, a second embodiment of the present invention will be described.

The configuration of the second embodiment is also as shown in FIG. 1 similarly to the first embodiment. However, the circuit configuration of the clock generation circuit 101 is different. FIG. 8 shows the configuration of the clock generation circuit 101. That is, the inverter 5
Although it is a ring oscillator of stages, the RC delay circuit inserted between each inverter is different. The number of stages of the RC delay circuit can be switched between one stage and two stages depending on the level of the KVpp signal. When KVpp is "L", the RC delay circuit has one stage and constitutes a first-order low pass filter. When KVpp is "H", the RC delay circuit has two stages and forms a second-order low-pass filter. As a result, this ring oscillator oscillates in a short cycle when KVpp is "L", and oscillates in a long cycle when KVpp is "H".

The operation of the second embodiment will be described next. FIG. 9 shows the operation waveform. When a program command is input from the outside of the chip via an I / O terminal (not shown), the command decoder decodes the program command and outputs it at time t.
At 0, the Prog signal is raised to "H". As a result, the clock signal generation circuit 101 outputs the clock signal RING having a predetermined frequency, and the booster circuit 102 starts operating by this clock signal. When Vpp, which is the output of the booster circuit, rises to about 20V at time t1, the Vpp detection circuit 106
Detects this, and sets KVpp to "H". In response to this signal, the clock signal generation circuit 101 starts oscillating for a longer period. As a result, the boosting capability of the booster circuit 102 is reduced, and the current consumption is also reduced. As a result, Vpp is 20 V without using a limiter circuit as in the conventional example.
To be kept nearby. Here, when the load resistance of the row decoder 103 or the like is temporarily reduced and a large current flows, such as when driving a word line, Vpp slightly decreases. However, Vpp
When the detection circuit detects this, KVpp is lowered to "L", and as a result, the clock signal RING output from the clock signal generation circuit 101 starts oscillating in a short cycle. In this way, when the load resistance changes with time, the cycle of the output clock signal of the clock generation circuit 101 changes accordingly, and as a result, Vpp is maintained at the predetermined voltage (20V).

The boosted power supply voltage Vpp thus boosted is supplied to the row decoder 103 and the like, and the predecoder 115 is supplied.
The level shift circuit 116 corresponding to the word line selected by is driven, and the word line is boosted to the Vpp potential via the transmission gate 117. As a result, writing or erasing is performed. As mentioned above, the memory cell is NOR
Although the effect of the present invention can be expected to be applied to both NAND type and NAND type, the effect is particularly remarkable when applied to a NAND type EEPROM.

As described above, according to the configuration of the second embodiment, there is no current path from the boosted power supply voltage Vpp except for the row decoder 103 acting as a load, so that the power consumption can be reduced. . In particular, a large amount of power consumption is saved by setting the transmission clock to have a long period when the voltage reaches a predetermined voltage. Further, the circuit configuration described above virtually eliminates the limitation of the capacity of the booster circuit, and a large-capacity booster circuit can be mounted. Therefore, the boosting time is shortened, and the writing and erasing times are shortened. It also leads to a reduction in power consumption. Subsequently, a third embodiment of the present invention will be described.

The structure of the third embodiment is also as shown in FIG. 1 similarly to the first embodiment. However, the circuit configuration of the clock generation circuit 101 is different. FIG. 10 shows the configuration of the clock generation circuit 101. That is, it is a ring oscillator with five stages of inverters, and there is R
A C delay circuit is inserted. Furthermore, the cycle is doubled with respect to the oscillation output via the binary counter 121. Further, a multiplexer 122 for selecting either the output of the binary counter 121 or the oscillation output of the ring oscillator is provided. As a result, two different clock signals having different cycles are output to RING depending on the level of the KVpp signal. That is, this clock generation circuit 101 oscillates in a short cycle when KVpp is "L",
When it is "H", it oscillates at a long cycle, that is, at twice the frequency.
The operation and operation waveforms of the third embodiment are the same as those of the second embodiment, so the description thereof will be omitted.

As described above, according to the configuration of the third embodiment, there is no current path from the boosted power supply voltage Vpp except for the row decoder 103 acting as a load, so that the power consumption can be reduced. In particular, since the write and erase voltages in the non-volatile semiconductor memory device are 10 V or higher, the power consumption saved by setting the oscillation clock to a long cycle when the voltage reaches a predetermined voltage is large. Also,
With the above circuit configuration, the capacity of the booster circuit is practically not limited, and a large capacity booster circuit can be mounted. Therefore, the boosting time is shortened, and the writing and erasing times are shortened. It also leads to a reduction in power consumption. Subsequently, a fourth embodiment of the present invention will be described.

The structure of the fourth embodiment is also as shown in FIG. 1 like the first embodiment. However, as shown in FIG. 11, the Vpp detection circuit 106 and the clock signal generation circuit 101 are different, and the KVpp signal is an analog signal. That is, the Vpp detection circuit 106 outputs an analog signal of 2V to 4V to KVpp by the five-stage MOS transistor level shift circuit and the resistance division of the D-type MOS transistor resistance. The clock signal generation circuit 101 is a five-stage ring oscillator, but the resistance value of the RC delay circuit is made variable by using the P-type MOS transistor 131, and the resistance value rises when KVpp rises. As a result, when Vpp drops, KVpp also drops, and P-type MO
The resistance value of the S transistor 131 is reduced, and the oscillation cycle of the ring oscillator is shortened. Therefore, the driving capability of the booster circuit rises and Vpp rises. Also, if Vpp rises, K
Vpp similarly rises, the resistance value of the P-type MOS transistor 131 increases, and the oscillation cycle of the ring oscillator increases. Therefore, the driving capability of the booster circuit is lowered and Vpp is lowered. In other words, negative feedback is working on Vpp. This is shown in FIG. As a result, the capacity of the booster circuit follows Vpp, that is, the load of the row decoder 103 and the like. This follow-up effect is analog, and highly accurate and flexible follow-up can be performed as compared with the case where the first to third embodiments are digital. As a result, the power consumption is further reduced. Further, the ripple of Vpp (small vertical vibration) is suppressed to a minimum. Subsequently, a fifth embodiment of the present invention will be described.

The overall construction of the fifth embodiment is similar to that of the first embodiment [FIG. 1]. However, Vpp detection circuit 1
The difference is that 06 also serves as a limiter circuit. That is, as shown in [FIG. 13], it includes a plurality of stages of Zener diodes 141 acting as limiters and a current detection circuit 142 including a current mirror circuit. In this circuit, when Vpp exceeds a predetermined voltage, a current flows through the Zener diode 141. The current detection circuit 142 detects this current, and the MOS transistor resistor 143 converts the current into a voltage, and the node A becomes "L". As a result, KVpp becomes "H". When Vpp is within the predetermined voltage, KVpp remains "L". In this way, Vpp can be detected.

The operation of the fifth embodiment detects the current flowing through the limiter when a predetermined voltage is exceeded, and this detection signal KV
Since the clock signal generation circuit 101 and the booster circuit 102 are controlled by pp, negative feedback is applied as in the first embodiment and the like, and Vpp does not rise too much. However, it is possible to provide a circuit that is safe against accidental rise of Vpp, such as when Vcc suddenly rises due to the presence of the limiter. Further, it also has the same effect as that of the first embodiment. Subsequently, a sixth embodiment of the present invention will be described.

The overall construction of the sixth embodiment is similar to that of the first embodiment [FIG. 1]. However, the configuration of the clock signal generation circuit 101 is different. [FIG. 14] is a D-type MOS
In this example, an RC delay circuit is configured by using a transistor constant current load resistor 150. In this way, the delay capacitor 151 is charged by the constant current load resistor 150, so that the delay time does not depend on the power supply voltage. This result [Fig. 1
5], the power supply voltage Vcc dependency of the clock signal generation circuit 101 is almost eliminated.

Next, a clock signal generation circuit 101 having a power supply voltage dependency is shown in FIG. By the resistance division of the MOS transistor level shift circuit and the D-type MOS transistor resistance, the change of the power supply voltage Vcc is amplified and output to the node B, and the oscillation cycle of the ring oscillator is changed. The clock signal generation circuit 101 is a 5-stage ring oscillator, but the resistance value of the RC delay circuit is a P-type M
It is variable by using the OS transistor 131, and the resistance value increases as the voltage of the node B increases. As a result, when Vcc drops, the voltage of the node B also drops, and the resistance value of the P-type MOS transistor 131 becomes small and the oscillation cycle of the ring oscillator becomes short. Therefore, the driving capability of the booster circuit is increased to compensate for the decrease in Vcc. This keeps Vpp constant. Further, when Vcc rises, the voltage of the node B also rises, the resistance value of the P-type MOS transistor 131 increases, and the oscillation cycle of the ring oscillator becomes longer. Therefore, the driving capability of the booster circuit is reduced and Vcc
To compensate for the rise. This keeps Vpp constant.
In other words, negative feedback is working on Vpp. This is shown in FIG. That is, when the power supply voltage is low (for example, 3.3 V), the boosting capability is sufficient, and when the power supply voltage is high (for example, 5 V), the boosting capability is slightly reduced and used. As a result, boosting can be performed without wasting power consumption even when used with a high power supply voltage. Therefore,
A nonvolatile semiconductor memory device having a wide allowable range of Vcc can be provided.

The configuration and effects of the present invention have been described above with reference to the first to sixth embodiments. Subsequently, a booster circuit suitable for a NAND type EEPROM will be described as a seventh embodiment.

Unlike the conventional case, the booster circuit provided in the seventh embodiment partially stops the internal booster circuit when a high voltage is input from the outside, thereby realizing low power consumption and high-speed writing. This is to further optimize the circuit configuration in order to generate the write and erase voltages of the NAND type EEPROM.

As described above, the NAND structure EEPR
In the OM, writing is performed with a tunnel current. Therefore, the current flowing through the memory cell at the time of writing is very small. Therefore, it is possible to write to hundreds to thousands of memory cells at the same time. As a result, a single power supply of, for example, 5V can be realized by having a booster circuit having a predetermined capacity inside the chip. Here, the required high voltage is, as described above, 20V and 10V at the time of writing, and 8V which is the write inhibit voltage supplied to the bit line connected to the memory cell in which the writing is not performed. Also, when deleting, 2
0V is required. The entire circuit configuration of the booster circuit according to the seventh embodiment will be described with reference to FIGS. 18 to 22.

FIG. 18 shows the circuit configuration around the booster circuit. That is, high voltage V'pp (in this case, 18 V or more)
External pad 401 for inputting the voltage, a high voltage detection circuit 403 for setting EXPO to “H” when V′pp exceeds a predetermined voltage (18V), and Vpp controlled by the EXPO signal.
Control circuit 4 for making H and Vin higher than V'pp
05, an oscillator 407 that outputs an oscillation output to RINGA at a predetermined frequency when EXPO is “H”, and Vpp
Transistor 431 for connecting / cutting off V'pp by H
And the oscillation output of RINGA, the transistor 431
Booster circuit 420 that further boosts IVpp, which is the output of the booster circuit, to 20V, and outputs VppE and VppW of booster circuit 420
Limiter 431, 432 for controlling so as not to exceed a predetermined voltage, and control circuits 412, 41 for stepping down IVpp by 10V and 8V to generate VM10 and VM8.
1 and limiters 433 and 434, and VppE (2
0V), VppW (20V), VM10 (10V), V
Booster circuits 424 and 42 for boosting M8 (8V) from 5V
1, 422, 423.

Next, details of the external pad 401, the high voltage detection circuit 403 and the transistor 431 are shown in FIG. The transistor 431 is an E-type transistor and a D-type transistor connected in series. In addition, the high voltage detection circuit 403
Is a buffer of a level shift circuit composed of MOS transistors and a voltage divider circuit composed of MOS resistors.
Details of the oscillator 407 are shown in FIG. It is a five-stage ring oscillator that receives the EXPO output from the high voltage detection circuit 403 as an input.

Details of the control circuit 411 are shown in FIG. That is, the amplification unit 501 and the charge pump unit 50
4 and 505 and limiter units 508 and 509. When EXPO is “H”, the amplifier 501 operates and R
A signal obtained by amplifying the oscillation signal of INGA appears at the node A. This is an oscillation signal having an amplitude of 18V from 0V to V'pp. The charge pump units 504 and 507 are node A
Is generated to generate a voltage higher than V'pp of 18V. Limiters 508 and 509 limit this high voltage to a predetermined voltage. Here, the MOS shown with a circle symbol just below the gate is shown.
The transistor is an Itype type MOS transistor having a threshold value of 0V. With this configuration, VppH is 23V
Rise to a degree.

Details of the booster circuit 420 are as shown in FIG. The booster circuit 420 of this embodiment boosts the input voltage of 18V to generate the erase and write voltage of 20V. Since a large capacity such as a well is charged by these voltages, a large capacity capacitor is used. The control circuits 412 and 413 are normal level shift circuits. A predetermined voltage is created by utilizing the drop of the threshold voltage of the MOS transistor.

Next, the operation of the booster circuit will be described.
That is, when a high voltage of about 18 V is applied to the external pad 401, the output signal EXPO of the high voltage detection circuit 403 is output.
Becomes "H" level. Subsequently, this signal boosts the gate of the transistor 431 for transmitting the V'pp voltage input from the outside by the control circuit 411 to the inside. This boosted voltage is VppH. Subsequently, the IVpp transmitted to the inside of the chip is boosted to 20V by the booster circuit 420 to generate VppE and VppW. Further, the control circuit 412 and the control circuit 413 produce VM10 and VM8 of 10V and 8V, respectively. If the voltage applied to the external pad 401 is a predetermined voltage (18V), EXPO
Remains at the "L" level, the control circuit 411 does not boost the gate of the transistor 431, and as a result, a high voltage is not transmitted inside the chip. Also, the oscillator 40
7 also does not operate, and as a result, the booster circuit 420 is not activated.
At this time, the internal booster circuits 424, 421, 422, 4
It goes without saying that the 23 operates independently.

As described above, by realizing an external single power source having only the internal booster circuit, and simultaneously taking in a high voltage from the outside of the chip, it is possible to support two power source modes. Especially when the high voltage is taken in from the outside, the internal booster circuit consumes almost no power. For example, 16M N
In case of AND type EEPROM, write current is 80mA
, But when the high voltage is input from the external pad, the power consumption of the internal booster circuit decreases,
A writing current of 1 mA is enough.

Further, unlike the case where only the internal booster circuit is used, the boosting time becomes very short. This is shown in FIG. 22. The bit charge time (precharge time) during writing is shortened. This leads to a reduction in writing time.

Further, when the external high-voltage power supply drops during use of the chip, the high-voltage detection circuit operates to operate the internal booster circuit to generate the voltage required for writing and erasing. Therefore, it is possible to provide a nonvolatile semiconductor memory device that is stable against variations in the external high voltage power supply.

As described above, since the internal booster circuit is provided and the high voltage can be taken in from the outside, the write current is reduced and the bit line charging time (precharge time) is reduced.
And the stability of the external high-voltage power supply against fluctuations are improved.

[0050]

According to the present invention, writing and erasing times can be shortened and power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a first embodiment of the present invention.

FIG. 7 is an operation waveform according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing a second embodiment of the present invention.

FIG. 9 is an operation waveform of the second embodiment of the present invention.

FIG. 10 is a circuit diagram showing a third embodiment of the present invention.

FIG. 11 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 12 is a diagram showing the operation of the fourth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 14 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 15 is a diagram showing the operation of the sixth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 17 is a diagram showing the operation of the sixth embodiment of the present invention.

FIG. 18 is a circuit configuration diagram showing a seventh embodiment of the present invention.

FIG. 19 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 20 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 21 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 22 is an operation waveform of a conventional example and a seventh embodiment of the present invention.

FIG. 23 is a circuit configuration diagram showing a conventional example.

FIG. 24 is an operation waveform showing a conventional example.

[Explanation of symbols]

 101 Clock Signal Generation Circuit 102 Booster Circuit 103 Row Decoder 104 Memory Cell Array 105 Column Decoder 106 Vpp Detection Circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 29/792 H01L 29/78 371 (72) Inventor Hiroto Nakai 580 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa No. 1 In stock company Toshiba Semiconductor System Technology Center (72) Inventor Yoshiyoshi Tokushige 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba Semiconductor System Technology Center

Claims (6)

[Claims] 1. A boosting means for boosting a power supply voltage to generate a boosted output voltage, a detecting means for detecting the boosted output voltage and outputting a detection signal, and a boosting control for controlling the boosting means according to the detection signal. A semiconductor memory device comprising a high voltage generating circuit including a means. 2. A boosting unit that is driven by a clock signal to boost a power supply voltage to generate a boosted output voltage; a sensing unit that outputs a sensing signal of a predetermined level when the boosted output voltage is less than or equal to a predetermined voltage; and the sensing signal. Is a predetermined level, the semiconductor memory device is provided with a high voltage generating circuit comprising a clock signal generating means for generating the clock signal. 3. A boosting unit that is driven by a clock signal to boost a power supply voltage to generate a boosted output voltage, a detection unit that outputs a detection signal when the boosted output voltage is equal to or higher than a predetermined voltage, and a detection unit that responds to the detection signal. A semiconductor memory device comprising: a high voltage generating circuit including a clock signal generating means for generating the clock signals having different cycles. 4. A boosting means for boosting a power supply voltage to generate a boosted output voltage, a limiter means for limiting the boosted output voltage to a predetermined voltage, and a detecting means for detecting a current flowing through the limiter means and outputting a detection signal. A semiconductor memory device comprising: a high voltage generating circuit including: a boosting control unit that controls the boosting unit according to the detection signal. 5. A plurality of memory cells to be programmed or erased by applying a voltage higher than a power supply voltage, and a decoder circuit driven by the boosted output voltage to apply a voltage to the plurality of memory cells. The semiconductor memory device according to claim 1, further comprising: 6. A booster circuit for boosting a power supply voltage to generate a boosted output voltage, and a booster output voltage connected to a plurality of memory cells to be programmed or erased by applying a voltage higher than the power supply voltage. A decoder circuit to be driven, an external pad for introducing a voltage higher than the power supply voltage, a high voltage detection unit for outputting a detection signal when the voltage applied to the external pad is equal to or higher than a predetermined voltage, and the detection signal A semiconductor memory device, comprising: a transmission unit that responds to transmit the voltage applied to the external pad to the decoder circuit.