JP2011004468A - Power circuit for memory write - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power circuit for memory write that reduces consumption of an electric current in boosting.SOLUTION: A charge pump circuit 14 operates in synchronization with clock signals CLK, CLKB output from a clock generator 12, and outputs a boost voltage Vpp by boosting a supply voltage Vcc. When the voltage value of the boost voltage exceeds a set voltage value Vtn set to a limiter circuit 16, the limiter circuit 16 is powered to prevent the boost voltage Vpp from exceeding the set voltage value Vtn. A current detection circuit 18 outputs a low-level stop signal CLKEN for stopping output of the clock signals CLK, CLKB to the clock generator 12 during the period when the current Vppi flowing to the limiter circuit 16 exceeds the set current value.

Description

  The present invention relates to a memory writing power supply circuit, and more particularly to a memory writing power supply circuit used for a nonvolatile memory that requires a relatively large voltage at the time of writing.

  As shown in FIG. 7, the conventional memory writing power supply circuit 100 includes a clock generator 120, a charge pump circuit 140, and a limiter circuit 160.

  As shown in FIG. 8, the clock generator 120 is connected to a NAND circuit 122 to which a program signal PGM for write control and an output clock signal CLK are input, a plurality of NOT circuits 124 to 130, and a connection point of the NOT circuit. It is composed of a plurality of capacitors 132 to 134 connected at one end. When the program signal PGM is at a high level, the clock generator 120 outputs an intermittent clock signal CLK and a clock signal CLKB obtained by inverting the clock signal CLK.

  As shown in FIG. 9, the charge pump circuit 140 includes a plurality of MOSFETs m1 to mi as switching elements and a plurality of capacitors C1 to Cj. The clock signal CLKB output from the clock generator 120 is input to the capacitors C1, C3,..., And the clock signal CLK output from the clock generator 120 is input to the capacitors C2, C4,. . Charge pump circuit 140 operates in synchronization with clock signals CLK and CLKB, and outputs boosted voltage Vpp obtained by boosting input power supply voltage Vcc. The charge pump circuit 140 includes MOSFET and capacitor stages (hereinafter referred to as boosting stages) that can obtain a boosted voltage higher than a set voltage (for example, 8 V) necessary for writing.

  As illustrated in FIG. 10, the limiter circuit 160 includes a plurality of NMOSFETs-M1 to Mn, an NMOSFET-Mplg, and a resistor R. The limiter voltage Vtn is determined by the threshold voltage Vt of the NMOSFET and the number n of stages of the NMOSFET. When the boosted voltage Vpp is boosted above the limiter voltage Vtn, a current flows in the limiter circuit 160, the potential Vplg at the connection point between the NMOSFET-Mn and the resistor R becomes equal to or higher than the threshold voltage Vt of the NMOSFET, and Vplg is used as a gate. NMOSFET-Mplg is turned on. When boosted voltage Vpp becomes equal to or lower than limiter voltage Vtn, no current flows in limiter circuit 160, the level of Vplg is lowered, and NMOSFET-Mplg is turned off.

  In the conventional memory writing power supply circuit 100 having such a configuration, as shown in FIG. 11, when the program signal PGM becomes high level, the clock signals CLK and CLKB are output and the boosting of the input voltage is started. When the boosted voltage Vpp becomes equal to or higher than the limiter voltage Vtn, the NMOSFET-Mplg is turned on and the level of the boosted voltage Vpp is lowered. To do. By repeating this series of operations, the level of boosted voltage Vpp is maintained at the set voltage.

  In addition, as a booster circuit built in a microcomputer or the like, the frequency of the clock input to the charge pump circuit is set by the pointer, and the frequency corresponding to the value of the pointer is selected by the selector, whereby the output voltage of the charge pump circuit is set. There has been proposed a booster circuit that keeps constant and minimizes the current consumed by the booster circuit (see Patent Document 1). In the booster circuit of Patent Document 1, power saving is achieved by selecting a low frequency in the power saving mode.

JP 2000-236657 A

  However, in the conventional memory writing power supply circuit, when the voltage is boosted from a low voltage to a high voltage, particularly when the boosting stage is increased as in the case of lowering the power supply voltage, the current consumption increases. There is a problem.

  Further, the booster circuit of Patent Document 1 also has a problem that the current consumption in the normal mode cannot be reduced.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power supply circuit for memory writing that can reduce current consumption during boosting.

  To achieve the above object, a power supply circuit for memory writing according to the present invention comprises a clock signal output means for outputting a clock signal when no stop signal is input, and a clock signal output from the clock signal output means. And a booster circuit that outputs a boosted voltage obtained by boosting a power supply voltage, and when the voltage value of the boosted voltage exceeds a predetermined set voltage value, the boosted voltage is turned on and the boosted voltage becomes the set voltage. A limiter circuit for limiting so as not to exceed the value, and a current that flows through the limiter circuit is detected, and a stop signal for stopping the output of the clock signal by the clock signal output means is detected while the current is detected. And a current detection circuit for outputting to the means.

  According to the memory writing power supply circuit of the present invention, the clock signal output means outputs a clock signal when no stop signal is input, and the booster circuit is synchronized with the clock signal output from the clock signal output means. The boosted voltage obtained by boosting the power supply voltage is output. Further, the limiter circuit conducts when the voltage value of the boosted voltage exceeds a predetermined set voltage value and limits the boosted voltage so that it does not exceed the set voltage value. Then, the current detection circuit detects the current flowing through the limiter circuit, and outputs a stop signal for stopping the output of the clock signal by the clock signal output means to the clock signal output means during the period in which the current is detected.

  In this way, during the period when the voltage value of the boost voltage exceeds the set voltage value and the current flows through the limiter circuit, the stop signal is output from the current detection circuit to the clock signal output means, and the output of the clock signal is stopped. To do. As a result, the booster circuit that operates in synchronization with the clock signal also stops operating, so that current consumption can be reduced.

  Further, the period in which the current is detected can be a period in which the current value of the current flowing through the limiter circuit exceeds a predetermined set current value. As a result, the boosted voltage can be controlled to an appropriate value even when the set voltage value set by the limiter circuit varies.

  Furthermore, the current detection circuit can include a selection circuit that selects the set current value from a plurality of different set current values. Thereby, the boosted voltage can be controlled in more detail.

  As described above, according to the memory writing power supply circuit of the present invention, the output of the clock signal is stopped during the period when the voltage value of the boosted voltage exceeds the set voltage value and the current flows through the limiter circuit. Thus, by stopping the operation of the booster circuit that operates in synchronization with the clock signal, it is possible to reduce current consumption during boosting.

1 is a block diagram showing a configuration of a power supply circuit for memory writing according to an embodiment. It is a circuit diagram of a clock generator of the power supply circuit for memory writing of the present embodiment. It is a circuit diagram of a limiter circuit of the power supply circuit for memory writing of the present embodiment. FIG. 3 is a circuit diagram of a current detection circuit of the memory write power supply circuit according to the first embodiment. It is a waveform diagram of the potential of each part of the memory write power supply circuit of the present embodiment. FIG. 5 is a circuit diagram of a current detection circuit of a memory write power supply circuit according to a second embodiment. It is a block diagram which shows the structure of the power supply circuit for memory writing of a prior art example. It is a circuit diagram of the clock generator of the power supply circuit for memory writing of a prior art example. It is a circuit diagram of a charge pump circuit of a power supply circuit for memory writing of a conventional example. It is a circuit diagram of a limiter circuit of a power supply circuit for memory writing of a conventional example. It is a waveform diagram of the potential of each part of a memory write power supply circuit of a conventional example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the memory write power supply circuit 10 according to the first embodiment outputs a clock signal CLK and CLKB based on a program signal PGM for write control and a stop signal CLKEN to be described later. In synchronization with the clock signals CLK and CLKB output from the generator 12, the clock generator 12, the charge pump circuit 14 that boosts the power supply voltage Vcc and outputs the boosted voltage Vpp, and the boosted voltage Vpp output from the charge pump circuit 14 A limiter circuit 16 that restricts to the set voltage and a current detection circuit 18 that detects a current flowing through the limiter circuit 16 and outputs a stop signal for controlling the clock generator 12 based on the detection result.

  As shown in FIG. 2, the clock generator 12 is connected in series with a NAND circuit 20 and a NAND circuit 20 to which a program signal PGM, a clock signal CLK, and a stop signal CLKEN output from a current detection circuit 18 described later are input. One end is connected to the connection point between the plurality of NOT circuits 22 to 28, the NOT circuit 22 and the NOT circuit 24, and the other end is grounded. The other end is connected to the connection point between the NOT circuit 24 and the NOT circuit 26. The capacitor 32 is connected and the other end is grounded. The output signal from the NOT circuit 28 is the clock signal CLK, and the output signal from the NOT circuit 26 is the clock signal CLKB. When the program signal PGM is at a high level, the clock generator 12 outputs an intermittent clock signal CLK and a clock signal CLKB obtained by inverting the clock signal CLK.

  The charge pump circuit 14 corresponds to the booster circuit of the present invention and has the same configuration as that of the conventional charge pump circuit 140 shown in FIG.

  As shown in FIG. 3, the limiter circuit 16 includes a plurality of NMOSFET-M1 to NMOSFET-Mn connected in series. The limiter voltage Vtn is determined by the threshold voltage Vt of the NMOSFET and the number n of stages of the NMOSFET. When boosted voltage Vpp is boosted above limiter voltage Vtn, a current flows in limiter circuit 16. Note that the NMOSFET-Mplg and the resistor R provided in the conventional limiter circuit 160 can be omitted.

  The current detection circuit 18 includes PMOSFETs P1 to P6 and NMOSFETs N1 to N6. A current Vppi flowing through the limiter circuit 16 is input to a connection point between the NMOSFET-N1 and the NMOSFET-N2. A bias voltage Vbias for defining a set current value is applied to the gate of the PMOSFET-P3, and a current Iref defined by the set current value is input to a connection point between the NMOSFET-N3 and the NMOSFET-N4. Is done. A voltage AMPO based on the current Vppi is applied to the gate of the PMOSFET-P5, and a voltage AMPref based on the current Iref is applied to the gate of the PMOSFET-P6. A signal extracted from the connection point between PMOSFET-P5 and NMOSFET-N5 is output as a stop signal.

  The set current value is determined in advance, taking into consideration the limit voltage Vtn of the limiter circuit 16 as the value at which the boost voltage Vpp becomes the set voltage for writing.

  Next, the operation of the memory write power supply circuit 10 of the first embodiment will be described with reference to FIG.

  Since the stop signal CLKEN is at a high level at the start of writing (details will be described later), the clock signals CLK and CLKB are output when the program signal PGM becomes a high level. Note that the clock signal CLKB is a signal obtained by inverting CLK, and is not shown in FIG. The output clock signals CLK and CLKB are input to the charge pump circuit 14. The charge pump circuit 14 operates in synchronization with the clock signals CLK and CLKB, and outputs a boosted voltage Vpp obtained by boosting the input power supply voltage Vcc.

  When boosted voltage Vpp exceeds limiter voltage Vtn set by limiter circuit 16, current Vppi flows through limiter circuit 16. The current Vppi is input to a connection point between the NMOSFET-N1 and the NMOSFET-N2 of the current detection circuit 18. On the other hand, a current Iref defined as a set current value by the bias voltage Vbias is input to a connection point between the NMOSFET-N1 and the NMOSFET-N2. When the current Vppi flows more than the current Iref, the voltage AMPO based on the current Vppi becomes larger than the voltage AMPref based on the current Iref, the PMOSFET-P5 is turned off, and the stop signal CLKEN is grounded. To a low level signal.

  As the stop signal CLKEN changes to the low level, the clock generator 12 stops outputting the clock signals CLK and CLKB. As a result, the charge pump circuit 14 that operates in synchronization with the clock signals CLK and CLKB also stops operating, and thus boosting stops. At this time, the boosted voltage Vpp output from the charge pump circuit 14 gradually decreases in voltage due to the relationship between the charge stored in Vpp, the write current of the memory cell, and the current Vppi flowing through the limiter circuit 16.

  As boosted voltage Vpp decreases, current Vppi flowing through limiter circuit 16 also decreases. When the current Vppi becomes smaller than the current Iref, the voltage AMPO becomes smaller than the voltage AMPref, the PMOSFET-P5 is turned on, and the stop signal CLKEN changes to a high level signal via the PMOSFET-P5. Since the current Vppi is 0 at the start of writing, similarly, the stop signal CLKEN is at a high level.

  As the stop signal CLKEN changes to the high level, the clock generator 12 resumes the output of the clock signals CLK and CLKB. As a result, the charge pump circuit 14 that operates in synchronization with the clock signals CLK and CLKB also resumes its operation, so that boosting is resumed. By repeating this series of operations, the level of boosted voltage Vpp is maintained at the set voltage.

  The stop signal CLKEN has two states, a low level and a high level. When the stop signal CLKEN is at a low level, the output of the clock signals CLK and CLKB is stopped. This corresponds to the stop signal of the invention.

  As described above, according to the memory write power supply circuit of the first embodiment, the current value of the current that has flowed through the limiter circuit when the voltage value of the boosted voltage exceeds the set voltage value is set to the set current value. During this period, a low level stop signal is output from the current detection circuit to the clock generator, and the output of the clock signal is stopped. As a result, the charge pump circuit that operates in synchronization with the clock signal also stops operating, so that current consumption can be reduced.

  In the first embodiment, the case where the state of the stop signal is changed by comparing the current flowing through the limiter circuit with the current defined by the set current value has been described. When it is possible to limit the boosted voltage to the power supply voltage for writing using only the limiter voltage, or when strict control is not required for controlling the boosted voltage, the presence or absence of current flowing through the limiter circuit is detected. However, a low-level stop signal may be output from the current detection circuit to the clock generator during the period in which the current is detected.

  Next, a memory write power supply circuit according to the second embodiment will be described. The memory write power supply circuit according to the second embodiment is different from the first embodiment in that a set current value can be selected. Since other configurations are the same as those of the memory write power supply circuit 10 of the first embodiment, the description thereof is omitted.

  FIG. 6 shows a current detection circuit 218 of the power supply circuit for memory writing according to the second embodiment.

  In addition to the configuration of the current detection circuit 18 of the memory write power supply circuit 10 of the first embodiment, the current detection circuit 218 includes PMOSFETs P311 to P31n and P321 to P32n arranged in parallel. A bias voltage Vbias is commonly applied to the gates of the PMOSFET-P3 and PMOSFET-P311 to P31n. Different voltages OP1 to OPn are applied to the gates of the PMOSFETs P321 to P32n, respectively. The set current value of the current Iref can be selected by selecting whether or not voltage is applied to the gates of the PMOSFETs P321 to P32n.

  For example, when the limiter voltage Vtn is finished low, writing to the memory cell may be insufficient due to a decrease in the boost voltage Vpp. In this case, the boost voltage Vpp necessary for writing can be secured by selecting the set current value to be large. Further, when the limiter voltage Vtn is finished high, the boosted voltage Vpp becomes high and the reliability of writing to the memory cell is lowered. In this case, by selecting the set current value to be small, the boosted voltage Vpp can be lowered to a necessary level, and excessive voltage application to the memory cell can be prevented.

  As described above, according to the memory write power supply circuit of the second embodiment, since the set current value can be selected, the set current value is finely adjusted to set the boost voltage more appropriately. The voltage value can be limited.

10 power supply circuit for memory writing 12 clock generator 14 charge pump circuit 16 limiter circuit 18 current detection circuit CLK, CLKB clock signal CLKEN stop signal Iref current Vcc defined by set current value power supply voltage Vpp boost voltage Vppi current flowing through limiter circuit Vtn limiter voltage (set voltage value)

Claims (3)

Clock signal output means for outputting a clock signal when a stop signal is not input;
A booster circuit that operates in synchronization with the clock signal output from the clock signal output means and outputs a boosted voltage obtained by boosting a power supply voltage;
A limiter circuit that conducts and limits the boost voltage so as not to exceed the set voltage value when a voltage value of the boost voltage exceeds a predetermined set voltage value;
A current detection circuit for detecting a current flowing through the limiter circuit and outputting a stop signal to the clock signal output means for stopping the output of the clock signal by the clock signal output means during a period in which the current is detected;
A power supply circuit for memory writing.   2. The power supply circuit for memory writing according to claim 1, wherein the period during which the current is detected is a period in which a current value of a current flowing through the limiter circuit exceeds a predetermined set current value.   3. The memory write power supply circuit according to claim 2, wherein the current detection circuit includes a selection circuit that selects the set current value from a plurality of different set current values.

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