JP2010035302A - Power control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power control circuit which can surely recognize a change, when the load of a power unit changes from heavy load to light load, or from alight load to a heavy load, and can quickly respond to the stop or resumption of the operation of the power unit in case that it has recognized the change. <P>SOLUTION: A comparator 3 compares a voltage VDET, detected by a voltage detecting circuit 2 with a reference voltage VREF, and generates a voltage according to this comparison result and outputs an output signal S1. The first counter 4 starts the counting of clock signals CLK2, with the rise of the output signal S1 of the comparator 3. The second counter 5 starts the counting of clock signals CLK2, with the fall of the output signal S1. A control signal generating circuit 6 changes a control signal S2, from H level to L level, when the enumerated data of the first counter 4 amount to the first set value, and changes the control signal S2 from L level to H level, when the enumerated data of the second counter 5 become the second set value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power supply control circuit applied to a power supply device such as a DC-DC converter.

Conventionally, as a technique related to a charge pump circuit which is one of DC-DC converters, for example, the invention described in Patent Document 1 is known.
The invention described in Patent Document 1 includes a first oscillating means for oscillating a first clock and a second oscillating means for oscillating a second clock having a frequency lower than that of the first clock in order to operate the charge pump circuit with the clock. And the charge pump circuit is operated by switching between the two oscillation means. Thereby, boosting of the charge pump circuit can be performed in a short time, and current consumption can be reduced in a stable state after boosting.

  However, in the invention of Patent Document 1, a charge pump operation (transistor switching operation) using a capacitor is always performed after boosting, regardless of the light load state of the load. For this reason, even when the load pump is light and the charge pump operation is unnecessary, the transistor performs the switching operation, so that the consumption current flows by the operation. Therefore, in the light load state, the effect of the loss due to the current consumption becomes relatively large, and there is a problem that the voltage fluctuation rate at the light load is reduced.

For solving such a problem, for example, the invention described in Patent Document 2 is known.
The invention described in Patent Document 2 has a comparison means for comparing the output voltage of the charge pump circuit with the set voltage, and controls the operation and stop of the oscillation circuit that drives the charge pump circuit by this output. As a result, the charge pump circuit can be operated intermittently to stabilize the output load fluctuation characteristics.
However, in the invention of Patent Document 2, since the operation and stop of the oscillation circuit are controlled based on the output of the comparison means, the ripple due to frequent repetition of stop and restart of the charge pump operation is included in the output voltage of the charge pump circuit. There is a problem that voltage noise is generated and the output voltage is not stable. Further, since the operation of the oscillation circuit involves starting and stopping, it is considered that it takes time to start the operation of the charge pump circuit and lacks responsiveness to load fluctuations.
Japanese Patent Laid-Open No. 10-312695 JP 2001-326567 A

  Therefore, an object of the present invention is to recognize the change reliably when the load of the power supply device changes from a heavy load to a light load, or conversely changes from a light load to a heavy load. An object of the present invention is to provide a power supply control circuit capable of obtaining a stable output voltage without causing excessive ripple voltage noise in the output voltage when the operation of the apparatus is stopped and restarted.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
A first aspect of the present invention is a power supply control circuit for a power supply device that performs a predetermined operation based on a voltage generation operation clock signal and generates and outputs a desired output voltage by the operation, and includes fluctuations in the output voltage of the power supply device Load state detecting means for detecting the load state of the power supply device based on the load, and when detecting that the load state detecting means has changed from a heavy load to a light load, after the first set time has elapsed from the detection When the operation of the power supply device by the voltage generation operation clock signal is stopped and the load state detection means detects that the load has changed from a light load to a heavy load, the voltage generation operation is performed after a second set time has elapsed since the detection. Control means for resuming the operation of the power supply device by the clock signal for use.

  A second invention is a power supply control circuit of a power supply device that performs a predetermined operation based on a voltage generation operation clock signal, and generates and outputs a desired output voltage by the operation, wherein the output voltage is divided. A divided voltage output means for outputting a divided voltage, and the divided voltage of the divided voltage output means is compared with a reference voltage, and when the divided voltage changes to the reference voltage or more, a first corresponding to the change A comparator that outputs a signal and outputs a second signal according to the change when the divided voltage changes below the reference voltage, and when there is an output of the first signal from the comparator. A first time measuring means for starting time measurement based on the output; a second time measuring means for starting time measurement based on the output when the second signal is output from the comparing means; When measuring by the first time measuring means When the first set value is reached, the operation of the power supply device by the voltage generating operation clock signal is stopped, and when the measurement time of the second time measuring means reaches the second set value, the voltage generating operation Control means for resuming the operation of the power supply device by the clock signal for use.

  According to a third invention, in the second invention, the control means operates the power supply device with the voltage generation operation clock signal when the measurement time of the first time measurement means reaches a first set value. For generating a control signal for performing a control operation for resuming the operation of the power supply device by the voltage generating operation clock signal when the measurement time of the second time measuring means reaches a second set value. A signal generation circuit; and a logic element that controls whether or not to supply the voltage generation operation clock signal to the power supply device according to the control signal generated by the control signal generation circuit.

In a fourth aspect based on the first to third aspects, the power supply device comprises a charge pump circuit.
According to a fifth invention, in the second to fourth inventions, the comparing means comprises a comparator having a hysteresis function.
According to the present invention having such a configuration, when the load of the power supply device changes from a heavy load to a light load, or conversely changes from a light load to a heavy load, the change can be reliably recognized and recognized. In this case, it is possible to quickly respond to the stop and restart of the operation of the power supply device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the power supply control circuit of the embodiment of the present invention is applied to a DC-DC converter 1 which is a power supply device.
The DC-DC converter 1 includes an output capacitor C1, and performs a predetermined operation based on a clock signal CLK1 that is a voltage generation operation clock signal to generate and output a desired output voltage VOUT.
Here, when the DC-DC converter 1 is, for example, a step-up DC-DC converter (charge pump circuit), the DC-DC converter 1 includes a circuit in which a switching element (switching transistor) and a step-up capacitor are combined (not shown). The switching element is turned on / off by the clock signal CLK1, and a desired output voltage VOUT is generated and output.

The power supply control circuit according to this embodiment detects the state of the load based on the fluctuation (change) of the output voltage VOUT of the DC-DC converter 1, and clocks when the load state is a heavy load (including a normal load). It is operated by the signal CLK1. When it is detected that the load state has changed from a heavy load to a light load, the operation of the DC-DC converter 1 by the clock CLK1 is stopped after the first set time has elapsed since the detection. On the other hand, when it is detected that the load state has changed from a light load to a heavy load, the operation of the DC-DC converter 1 by the clock signal CLK1 is resumed after the second set time has elapsed since the detection.
Therefore, as shown in FIG. 1, the power supply control circuit according to this embodiment includes a voltage detection circuit 2, a comparator (comparison circuit) 3, a first counter 4, a second counter 5, and a control signal generation circuit. 6 and an AND gate 7.

The voltage detection circuit 2 detects the output voltage VOUT of the DC-D converter 1, divides the output voltage VOUT by resistors R1 and R2, and uses the divided voltage as a detection voltage VDET.
In this embodiment, the output voltage VOUT is divided by the resistors R1 and R2 to detect the load state. However, a resistor element is used for detecting the load current in series between the output of the DC-D converter 1 and the load. It is also possible to detect the load state with a current-voltage conversion circuit using the voltage at both ends of the resistance element as an input.
The comparator 3 compares the detection voltage VDET of the voltage detection circuit 2 with the reference voltage VREF, and outputs a voltage corresponding to the comparison result to the first counter 4 and the second counter 5 as the output signal S1. Here, the comparator 3 preferably has a hysteresis function in order to ensure the stability of the comparison operation.

The first counter 4 starts counting the clock signal CLK2 at the rising edge of the output signal S1 from the comparator 3, and is reset (initialized) at the falling edge of the output signal S1. The second counter 5 starts counting the clock signal CLK2 at the falling edge of the output signal S1 from the comparator 3, and is reset at the rising edge of the output signal S1.
The control signal generation circuit 6 generates and outputs a control signal S2 for controlling the output of the AND gate 7 based on the high level signal (H level signal), and sets the level of the control signal S2 to the first counter 4 and the first counter 4. According to the count value of the 2 counter 5, it is changed as described later.
That is, the control signal generation circuit 6 controls the DC-DC converter 1 when the power is turned on or after that and when the load of the DC-DC converter 1 is a heavy load (including a normal load). A high level signal is output as the signal S2.

On the other hand, when the count value output from the first counter 4 reaches the first set value, the control signal generation circuit 6 changes the control signal S2 from the high level to the low level, and uses this low level signal as the control signal S2. Output. Further, when the count value output from the second counter 5 becomes the second set value, the control signal S2 is changed from the low level to the high level, and this high level signal is output as the control signal S2.
Here, both the first set value and the second set value can be arbitrarily set from the outside, and both of them may be the same value or different values.

The AND gate 7 controls the passage (supply) of the clock signal CLK1 to the DC-DC converter 1, and the passage is controlled by a control signal S2 output from the control signal generation circuit 6. Therefore, the clock signal CLK1 passes through the AND gate 7 to operate the DC-DC converter 1 when the control signal S2 is at a high level.
In this embodiment, assuming that the frequency of the clock signal CLK1 is f1 and the frequency of the clock signal CLK2 is f2, the relationship is f2> f1.

Next, an operation example of the embodiment configured as described above will be described with reference to FIGS. 1 and 2.
Now, when the output voltage VOUT of the DC-DC converter 1 fluctuates and the detection voltage VDET of the voltage detection circuit 2 becomes equal to or higher than the reference voltage VREF (see FIG. 2A), the output signal S1 of the comparator 3 changes from low level to high level. The level changes (see FIG. 2B). This means that the load of the DC-DC converter 1 has changed from a heavy load (including a normal load) to a light load, and a signal to that effect has been output.

  At the rise of the output signal S1 from the comparator 3, the first counter 4 starts counting the clock signal CLK2 (see FIG. 2C), and the count value is notified to the control signal generation circuit 6. At this time, the control signal S2 generated by the control signal generation circuit 6 remains at a high level (see FIG. 2E), and since this high level signal is output to the AND gate 7, The clock signal CLK1 is supplied to the DC-DC converter. Therefore, the DC-DC converter 1 performs an operation based on the clock signal CLK1 (see FIG. 2H).

Thereafter, when the count value from the first counter 4 reaches a set value (in this example, “4”), that is, when a predetermined time T1 has elapsed from the rise of the output signal S1, the control signal generation circuit 6 sets the control signal S2 to the high level. From low to low (see FIG. 2E). As a result, the AND gate 7 stops supplying the clock CLK1 to the DC-DC converter. For this reason, the DC-DC converter 1 stops the operation by the clock signal CLK1 (see FIG. 2H).
Here, when the output signal S1 from the comparator 3 falls before the count value from the first counter 4 reaches the set value, for example, the output voltage VOUT of the DC-DC converter 1 includes noise, ripple, and the like. If it is, the first counter 4 is reset. For this reason, the DC-DC converter 1 does not continuously stop the operation based on the clock signal CLK1.

Next, as shown in FIG. 2A, when the detection voltage VDET of the voltage detection circuit 2 becomes equal to or lower than the reference voltage VREF, the output signal S1 of the comparator 3 changes from high level to low level (FIG. 2B). reference). This means that the load of the DC-DC converter 1 has changed from a light load to a heavy load, and a signal to that effect has been output.
At the falling edge of the output signal S1 from the comparator 3, the second counter 5 starts counting operation of the clock CLK2 (see FIG. 2D), and the count value is notified to the control signal generation circuit 6. At this time, the control signal S2 generated by the control signal generation circuit 6 remains at a low level (see FIG. 2E), and since this low-level signal is output to the AND gate 7, the AND gate 7 The supply of the clock CLK1 to the DC-DC converter 1 remains stopped. For this reason, the DC-DC converter 1 remains stopped by the clock CLK1 (see FIG. 2H).

Thereafter, when the count value from the second counter 5 reaches the set value (in this example, “4”), that is, when the predetermined time T1 has elapsed from the fall of the output signal S1, the control signal generation circuit 6 sets the control signal S2 to low. The level is changed from high to high (see FIG. 2E). As a result, the AND gate 7 resumes supplying the clock signal CLK1 to the DC-DC converter 1. Therefore, the DC-DC converter 1 resumes the operation based on the clock signal CLK1 (see FIG. 2H).
Here, if the output signal S1 from the comparator 3 rises before the count value from the second counter 5 reaches the set value, the second counter 5 is reset. For this reason, the operation of the DC-DC converter 1 is stopped and the operation by the clock signal CLK1 is stopped.

As described above, according to this embodiment, at the time of light load, the current consumption accompanying the operation of the switching element included in the DC-DC converter is reduced, and the decrease in voltage conversion efficiency at the time of light load can be prevented.
Further, according to this embodiment, when it is detected that the load of the DC-DC converter changes from a heavy load to a light load, or conversely changes from a light load to a heavy load, the DC-DC converter is detected when the change is detected. The DC-DC converter can be reliably implemented without repeating excessive ON / OFF operations without being affected by the noise of the output voltage of the converter. Therefore, since the operation of the DC-DC converter can be reliably stopped and restarted, a stable output voltage can be obtained.

In the above description of the operation, the predetermined time T1 from the rising edge of the output signal S1 from the comparator 3 and the predetermined time T1 from the falling edge of the output signal S1 are described as being the same. Also good.
In the circuit of FIG. 1, the clock signal CLK1 supplied to the AND gate 7 and the clock signal CLK2 supplied to the counters 4 and 5 are separated. However, as the clock signal CLK1, a signal obtained by dividing the clock signal CLK2 by a frequency divider may be used. In this way, the signal source of the clock signal can be shared.

It is a circuit diagram which shows the structure of embodiment of the power supply control circuit of this invention. It is a wave form diagram which shows the example of a waveform of each part of the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... DC-DC converter, 2 ... Voltage detection circuit, 3 ... Comparator, 4 ... 1st counter, 5 ... 2nd counter, 6 ... Control signal generation circuit, 7 ..And gate

Claims (5)

A power supply control circuit of a power supply device that performs a predetermined operation based on a voltage generation operation clock signal and generates and outputs a desired output voltage by the operation,
Load state detection means for detecting a load state of the power supply device based on fluctuations in the output voltage of the power supply device;
When the load state detection means detects that the load has changed from a heavy load to a light load, the operation of the power supply device by the voltage generation operation clock signal is stopped after the first set time has elapsed since the detection, and the load state Control means for resuming the operation of the power supply device by the voltage generation operation clock signal after elapse of a second set time from the detection when the detection means detects a change from a light load to a heavy load;
A power supply control circuit comprising: A power supply control circuit of a power supply device that performs a predetermined operation based on a voltage generation operation clock signal and generates and outputs a desired output voltage by the operation,
Divided voltage output means for outputting a divided voltage obtained by dividing the output voltage;
The divided voltage of the divided voltage output means is compared with a reference voltage, and when the divided voltage changes to the reference voltage or higher, a first signal corresponding to the change is output, and the divided voltage is A comparing means for outputting a second signal corresponding to the change when the voltage changes to a reference voltage or lower;
First time measuring means for starting time measurement based on the output of the first signal from the comparing means,
When there is an output of the second signal from the comparison means, second time measurement means for starting time measurement based on the output;
When the measurement time of the first time measurement means reaches a first set value, the operation of the power supply device by the voltage generation operation clock signal is stopped, and the measurement time of the second time measurement means is a second set value. The control means for resuming the operation of the power supply device by the voltage generation operation clock signal,
A power supply control circuit comprising: The control means includes
When the measurement time of the first time measurement means reaches a first set value, the operation of the power supply device by the voltage generation operation clock signal is stopped, and the measurement time of the second time measurement means is set to a second setting. A control signal generation circuit for generating a control signal for performing a control operation to resume the operation of the power supply device by the voltage generation operation clock signal when the value is reached;
A logic element that controls whether or not to supply the voltage generation operation clock signal to the power supply device according to the control signal generated by the control signal generation circuit;
The power supply control circuit according to claim 2, further comprising:   The power supply control circuit according to claim 1, wherein the power supply device includes a charge pump circuit.   5. The power supply control circuit according to claim 2, wherein the comparison unit includes a comparator having a hysteresis function.

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