JP4412940B2 - Charge pump control circuit - Google Patents

Description

  The present invention relates to a charge pump control circuit that controls the operation of a charge pump that boosts a low power supply voltage to obtain a high voltage.

  2. Description of the Related Art Conventionally, charge pumps that control the charging of a capacitor to boost the voltage are known, and are used for generating a high voltage for erasing a nonvolatile memory or the like.

  For example, in the charge pump using CMOS shown in FIG. 1, the source of the NMOS 10 is connected to the power supply voltage VDD on the input side, and the shift capacitor 12 is supplied with a pulse voltage from the other end to the drain of the NMOS 10. Is connected. The drain of the NMOS 10 is connected to the drain of the PMOS 14, and the source of the PMOS 14 is connected to the voltage holding capacitor 16 and to the output terminal 18.

  The same pulse signal is supplied to the gates of the NMOS 10 and the PMOS 14.

  In such a circuit, the NMOS 10 is turned on by the clock signal H, the PMOS 14 is turned off, and the voltage VDD is held in the shift capacitor 12. Further, the voltage of the shift capacitor is shifted by, for example, the voltage VDD by the voltage shift pulse signal in a state where the NMOS 10 is turned off by the clock signal L and the PMOS 14 is turned on. VDD is held and output.

  In such a charge pump, the output voltage is measured and the frequency of the clock to be supplied is adjusted according to the output voltage value to save current.

  An example of the charge pump is shown in Patent Document 1, for example.

JP 7-298607 A

  However, in the prior art, when erasing the nonvolatile memory or the like, the charge pump continues to operate and consumes a useless current. There is also a method that detects the high voltage and adjusts the clock of the charge pump, but it is not very efficient when the circuit scale is large and the current flows out only to the extent of off-leakage current, such as when erasing nonvolatile memory. It was not good.

  An object of this invention is to perform the power saving effective in a charge pump.

  The present invention is a charge pump control circuit that boosts and outputs an input voltage using a clock, and generates the clock when the output voltage of the charge pump circuit exceeds a first threshold voltage. Prohibiting and generating a clock when the output voltage of the charge pump circuit becomes equal to or lower than a second threshold value lower than the first threshold voltage.

  The present invention also provides a first Zener diode that receives the output voltage at one end and turns on when a voltage equal to or higher than the breakdown voltage is applied, and receives a voltage equal to or higher than the breakdown voltage when the output voltage is received at one end. A second Zener diode that is turned on, current limiting means for limiting the current flowing through the first and second Zener diodes to a predetermined value, the first Zener diode, and the current limiting means. And a second threshold value at which the second Zener diode breaks down based on a voltage drop at the Zener diode, the first threshold voltage at which the first Zener diode breaks down. It is characterized by being set higher than the voltage.

  And a logic circuit that inputs the lower voltage A of the first Zener diode and the lower voltage B of the second Zener diode, is set at the falling edge of B, and is reset at the rising edge of A, It is preferable to control the operation of the clock generation circuit by the output of this logic circuit.

  According to the present invention, two threshold values are set for the output of the charge pump circuit, and the clock supplied to the charge pump circuit is turned on and off so that the output voltage is between the two threshold values. As a result, it is possible to measure the effective power saving by turning off the charge pump circuit when unnecessary.

  In particular, by using two Zener diodes, the above-described control can be achieved with a simple circuit.

  Note that what is required for erasing in the nonvolatile memory is a high voltage and does not require a large current. Therefore, the control as in the present invention is very effective.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is an example of a control circuit according to the present embodiment, and a high voltage that is an output of the charge pump is supplied to the line HV. The cathodes of the Zener diodes D1 and D2 are connected to the line HV. The anode and the drain of the Zener diode D1 are short-circuited between the gate and the drain, and the drain of the NMOS transistor M1 that functions as a Zener diode is connected. The source of the NMOS transistor M1 is connected to the drain of the NMOS transistor M2, and the source of the NMOS transistor M2 is connected to the ground. Here, the drain side of the NMOS transistor M2 is a node A.

  The drain of the NMOS transistor M3 is directly connected to the anode of the Zener diode D2, and the source of the NMOS transistor M2 is connected to the ground. Here, the drain side of the NMOS transistor M2 is a node B.

  A predetermined voltage is supplied from the BIAS line to the gates of the NMOS transistors M2 and M3, and the current flowing therethrough is limited to a sufficiently small value.

  In such a circuit, when the HV voltage increases and the Zener diodes D1 and D break down, the nodes A and B become high. Here, an NMOS transistor M1 is inserted between the Zener diode D1 and the NMOS transistor M2. Accordingly, the HV voltage at which the Zener diode D1 breaks down is 1GS (gate-source voltage) higher than the voltage at which the Zener diode D2 breaks down due to the action of the NMOS transistor M1. Therefore, when the voltage of the line HV increases, the Zener diode D2 breaks down first, and then the Zener diode D1 breaks down when the voltage becomes higher by 1GS.

  The node A is input to the NAND gate N1, and the node B is input to the NAND gate N2 via the inverter I1. Here, the output of the NAND gate N1 is input to the NAND gate N2, the output of the NAND gate N2 is input to the NAND gate N1, and the output of the NAND gate N1 is taken out. Therefore, this circuit operates as a flip-flop that is set by the fall of node B and reset by the rise of node A.

  The output of the NAND gate N1 is input to the NAND gate N3, and the control signal WRITE is also input to the input of the NAND gate N3. Have been entered.

  Therefore, the clock generation circuit CP has an input indicating that it is in an operating state by the control signal WRITE, and the voltage of the line HV becomes equal to or lower than the voltage (second threshold voltage) at which the Zener diode D2 breaks down. When the voltage of the line HV exceeds the voltage at which the Zener diode D1 breaks down (first threshold voltage), a signal that is low is supplied, and the clock generation circuit CP supplies A clock is generated when the signal to be output is at a high level.

  FIG. 3 shows an operation timing chart of this circuit. The signal ENABLE operates the charge pump when it is H (high level). Therefore, when the signal WRITE becomes H, ENABLE also becomes H. The charge pump operates due to the ENABLE H, and the voltage of the line HV as the output rises.

  When the voltage of the line HV exceeds the threshold voltage of the Zener diode D2 (B determination level), a breakdown current flows through the Zener diode D2, and the voltage at the point B becomes H. Next, when the voltage of the line HV exceeds the threshold voltage of the Zener diode D1 (determination level of A), a breakdown current flows through the Zener diode D1 and the voltage at the point A becomes H. Then, when the voltage at the point A becomes H, ENABLE becomes L, the generation of the clock is stopped, and the operation of the charge pump is stopped.

  As a result, the voltage of the line HV drops, and when the voltage of the line HV falls below the threshold value (B determination level) of the Zener diode D2, ENABLE becomes H due to the fall, and clock generation is generated. The charge pump is started again.

  In this way, by the intermittent operation of the charge pump, the voltage of the line HV rises and falls between the voltage at which the Zener diode D1 is turned on and the voltage at which the Zener diode D2 is turned on.

  Here, the precaution of this circuit is to add a sufficient capacity to the HV in order to prevent malfunction of the control circuit due to the ripple of the charge pump output. That is, it is necessary to make the output ripple of the charge pump sufficiently smaller than the difference between the voltage at which the Zener diode D1 is turned on and the voltage at which the Zener diode D2 is turned on.

  Thus, according to this embodiment, when the off-leakage current to the transistor is sufficiently small, even if the operation time of the charge pump is short, a high voltage can be maintained for a long time, so that the total current consumption can be greatly reduced. . That is, what is required for erasing the nonvolatile memory is a high voltage and not a large current. Therefore, the voltage drop at the output of the charge pump is mostly due to the off-leakage current of the transistor. Therefore, the charge pump does not need to be operated at all times, and the power consumption of the circuit can be greatly reduced by operating only when the voltage drops.

It is a figure which shows the structure of a charge pump circuit. It is a figure which shows the structure of one Embodiment. It is a timing chart showing the waveform of each part.

Explanation of symbols

  12 shift capacitor, 16 holding capacitor, 18 output, CP clock generation circuit, D1, D2 Zener diode, I1, I2 inverter, M1, M2, M3 transistor, N1, N2, N3 NAND gate.

Claims (2)

A charge pump control circuit that boosts and outputs an input voltage using a clock,
A first Zener diode that receives the output voltage at one end and is turned on when a voltage equal to or higher than a breakdown voltage is applied;
A second Zener diode that receives the output voltage at one end and is turned on when a voltage equal to or higher than a breakdown voltage is applied;
Current limiting means for limiting the current flowing through the first and second Zener diodes to a predetermined value,
A transistor is inserted between the first Zener diode and the current limiting means, and a first threshold voltage at which the first Zener diode breaks down based on a voltage drop in the transistor is set to the second threshold voltage. The zener diode is set higher than a second threshold voltage at which breakdown occurs, and the generation of the clock is prohibited when the output voltage of the charge pump circuit exceeds the first threshold voltage, and the charge pump A control circuit for a charge pump, wherein generation of a clock is started when an output voltage of the circuit falls below a second threshold value lower than a first threshold voltage. The circuit of claim 1 , wherein
The logic circuit has a logic circuit that inputs the lower voltage A of the first Zener diode and the lower voltage B of the second Zener diode, is set at the fall of B, and is reset at the rise of A. A charge pump control circuit which controls operation of a clock generation circuit according to an output of the circuit.

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