KR101040001B1 - Voltage supply circuit - Google Patents

Abstract

PURPOSE: A voltage supply circuit is provided to change a current consumption in a clock driver according to a period where generated voltage rises and a period where the generated voltage is maintained. CONSTITUTION: A pump circuit outputs a pumped voltage. A regulation circuit outputs a pump enable. A driver control circuit(260) generates a current control enable signal. A clock driver generates first and the second clock driving signal. The clock driver provides the first and the second clock driving signal to a pump circuit. The current amount of the first and second clock driving signal is controlled by a current control enable signal. A driver control circuit comprises a comparator circuit and a level shift circuit(262) The comparator circuit compares a multiple voltage and a second reference voltage. The level shift circuit outputs the current control enable signal.

Description

Voltage supply circuit

The present invention relates to a voltage supply circuit.

A semiconductor memory device is a memory device that stores data and can be read when needed. Semiconductor memory devices are roughly divided into random access memory (RAM) and read only memory (ROM). Data stored in RAM is destroyed when power supply is interrupted. This type of memory is called volatile memory. On the other hand, data stored in the ROM is not destroyed even when the power supply is interrupted. This type of memory is called nonvolatile memory.

An electrically erasable and programmable semiconductor memory device performs FN tunneling and hot electron in performing an erase operation for erasing data stored in a memory cell and a program operation for storing data in the memory cell. Hot electron injection is used.

In this case, in order to program the data of the memory cell, a program voltage to be applied is typically a high voltage between 15V and 20V. In general, a semiconductor memory device operating under a low power supply voltage includes a voltage supply circuit that generates a high voltage inside the chip. The voltage supply circuit is generally configured to pump and output a low voltage input to a high voltage using a voltage pump circuit or the like.

Therefore, the voltage supply circuit according to an embodiment of the present invention provides a circuit that can control the amount of current consumed by the clock driver according to the section in which the output voltage is rising and the section in which the voltage is maintained. do.

Voltage supply circuit according to an embodiment of the present invention,

A pump circuit for outputting a pumped voltage in response to the first and second clock signals; A regulation circuit for outputting a pump enable signal to the pump circuit depending on whether an output has reached a target level; A driver control circuit for generating a current control enable signal according to whether the output of the pump circuit is close to a target level; And generating the first and second clock driving signals inverted from each other in response to the input clock signal according to the pump enable signal, and providing the first and second clock driving signals to the pump circuit. And a clock driver controlled by a current control enable signal.

The driver control circuit may include a comparison circuit configured to compare the divided voltage with a second reference voltage that is equal to or lower than the first reference voltage; And a level shift circuit outputting the current control enable signal in response to the output of the comparison circuit.

The clock driver may include a logic gate inverting and outputting the input clock signal in response to the clock enable signal; A first inverter group including an even number of inverters connected in series for outputting the output of the logic gate as the first clock signal; And a second inverter group including an odd number of inverters connected in series to output the output of the logic gate as the second clock signal.

Voltage supply circuit according to another embodiment of the present invention,

A pump circuit for outputting a pumped voltage; a regulation circuit for outputting a pump enable signal according to whether the output reaches the target level in the pump circuit; A driver control circuit for generating a current control enable signal according to whether the output of the pump circuit is close to a target level; And generating the first and second clock driving signals inverted from each other in response to the input clock signal according to the pump enable signal, and providing the first and second clock driving signals to the pump circuit, wherein the current amount of the first and second clock driving signals is the current. And a clock driver controlled by the control enable signal.

As described above, the voltage supply circuit according to the embodiment of the present invention varies the current consumed by the clock driver according to the section in which the voltage generated by the voltage providing circuit is rising and the section being maintained, and each section A clock driver optimized for this can be provided.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to make the disclosure of the present invention complete and to those skilled in the art. It is provided for complete information.

In a typical voltage supply circuit, the output voltage can be controlled by a clock driver that provides a clock to enable the pump.

1 shows a voltage output from a general voltage supply circuit.

Referring to FIG. 1, a voltage providing circuit generally controls a pump operation by inputting a clock signal to output a voltage VPP.

The voltage VPP output from the pump rises slowly at 0V. When the set voltage is reached, the operation of the pump is disabled by stopping the inputs of the clock signal to control the voltage VPP not to be greater than the set voltage.

In FIG. 1, a section in which the voltage VPP is output is divided into a section T1 in which the voltage gradually rises and a section T2 maintaining a constant level.

In order to increase the efficiency of outputting the voltage VPP from the voltage supply circuit, it is necessary to increase the driver capability of the clock driver that provides the clock signal.

That is, since the capacitor of the pump circuit that generates the voltage is configured to be very large, the size of the clock driver must be large to occupy the voltage for the capacitor, and to deliver the clock signal without delay when discharged.

In general, a clock driver is configured to output a clock signal by connecting a plurality of inverters. In order to increase the size of the clock driver, there is a method of increasing the size of the inverter.

If the size of the inverter is increased to improve the output performance, the clock signal is transmitted quickly, so that the pump circuit can quickly increase the voltage.

Increasing the size of the inverter increases the current consumption. In other words, the efficiency of increasing the voltage increases, but the current consumption increases.

2 is a voltage supply circuit according to an embodiment of the present invention.

2, the voltage providing circuit 200 according to an embodiment of the present invention includes a pump circuit 210, an oscillator 220, a clock driver 230, a regulation circuit 240, and a reference voltage generation circuit 250. , And driver control circuit 260.

Pump circuit 210 includes capacitors between diode stages (not shown). The pump circuit 210 generates the output voltage VPP by pumping the power supply voltage VDD according to the first and second clocks CLK1 and CLK2.

The regulation circuit 240 includes first and second resistors R1 and R2 and a first comparator COM1.

The first and second resistors R1 and R2 are connected in series between the output terminal of the pump circuit 110 and the ground node. The voltage output from the node D1, which is a connection point between the first and second resistors R1 and R2, is the first voltage V1. The first voltage V1 is a voltage at which the output voltage VPP of the pump circuit 110 is divided by the first and second resistors R1 and R2.

The first voltage V1 is input to the inverting terminal (−) of the first comparator COM1.

The first reference voltage Vref1 is input to the non-inverting terminal + of the first comparator COM1.

The first reference voltage Vref1 is a voltage from the reference voltage generation circuit 250 and maintains a constant voltage level.

The reference voltage generator 250 generates not only the first reference voltage Vref1 but also a second reference voltage Vref2 having a voltage level equal to or lower than that of the first reference voltage Vref1. The second reference voltage Vref2 is also a voltage maintaining a constant voltage level.

The first comparator COM1 compares the first voltage V1 with the first reference voltage Vref1, and outputs a low level signal when the first voltage V1 is higher than the first reference voltage Vref1. When the first voltage V1 is lower than the first reference voltage Vref1, the high level signal is output.

The output of the first comparator COM1 is a clock enable signal CLK_EN.

The oscillator 220 generates a clock signal CLK_osc.

The clock signal CLK_osc is input to the clock driver 230.

When the current control enable signal (Current control_EN) from the driver control circuit 260 is input at the low level, the clock driver 230 according to the embodiment of the present invention consumes a large current but increases the driver capability, thereby increasing the clock signal CLK_osc. ) Is output to the first and second clocks CLK1 and CLK2 to minimize delay.

When the current control enable signal (Current control_EN) from the driver control circuit 260 is input to the voltage VPP1, the clock driver 230 may reduce the driver capability so that the clock driver CLK_osc may receive the first and the first signals. The delay occurs slightly when outputting to the two clocks CLK1 and CLK2, but current consumption can be reduced.

The driver control circuit 260 outputs the output from the pump circuit 210 using the first voltage V1 from the regulation circuit 240 and the second reference voltage Vref2 from the reference voltage generation circuit 250. It is determined whether the voltage VPP is rising or maintained and outputs a current control enable signal Current control_EN.

3 illustrates the driver control circuit of FIG. 2.

Referring to FIG. 3, the driver control circuit 260 includes an operation sensing circuit 261 and a current control circuit 262.

The motion detection circuit 261 outputs the motion detection signal IN by comparing the first voltage V1 from the regulation circuit 240 with the second reference voltage Vref2 from the reference voltage generation circuit 250.

The current control circuit 262 outputs the current control enable signal Current control_EN as 0 V or the voltage VPP1 in response to the operation detection signal IN.

In more detail, the motion detection circuit 261 includes a second comparator COM2. The second reference voltage Vref2 is input to the inverting terminal − of the second comparator COM2.

The first voltage V1 is input to the non-inverting terminal + of the second comparator COM2.

The second comparator COM2 outputs a low level signal when the second reference voltage Vref2 is higher than the first voltage V1. The second comparator COM2 outputs a high level signal when the second reference voltage Vref2 is lower than the first voltage V1.

The signal output from the second comparator COM2 is the motion detection signal IN.

The current control circuit 262 is a level shift circuit that outputs 0V when the operation detection signal IN is at a high level, and outputs a voltage VPP1 when the operation detection signal IN is at a low level. The voltage VPP1 is a voltage which is set slightly lower than the power supply voltage VDD.

The current control circuit 262 includes first to fifth PMOS transistors P1 to P4 and first to fourth NMOS transistors N1 to N4.

The fifth PMOS transistor P5 is connected between the input terminal to which the voltage VPP1 is input and the node D2, and the ground voltage VSS is input to the gate of the fifth PMOS transistor P5. Therefore, the fifth PMOS transistor P5 is always kept turned on.

The first PMOS transistor P1 is connected between the node D2 and the node D3, and the second PMOS transistor P2 is connected between the node D2 and the node D4. The voltage VPP1 is input to the node D2 through the fifth PMOS transistor P5.

The gate of the first PMOS transistor P1 is connected to the node D4, and the gate of the second PMOS transistor P2 is connected to the node D3.

The first NMOS transistor N1 is connected between the node D3 and the node D5, and the second NMOS transistor N2 is connected between the node D4 and the node D5. Node D5 is connected to the ground node.

The operation detection signal IN is input to the gate of the first NMOS transistor N1, and the inverted operation detection signal IN_N is input to the gate of the second NMOS transistor N2.

The third PMOS transistor P3 is connected between the node D6 and the node D8, and the gate of the third PMOS transistor P3 is connected to the node D4.

The fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected in series between the node D6 and the node D7. The gate of the fourth PMOS transistor P4 is connected to the node D3, and the inverted motion detection signal IN_N is input to the gate of the fourth NMOS transistor N4.

The third NMOS transistor N3 is connected between the node D8 and the node D7, and the operation detection signal IN is input to the gate of the third NMOS transistor N3.

The voltage VPP1 is input to the node D6, and the node D7 is connected to the ground node.

The current control enable signal Current control_EN is output at the node D8.

In addition, the clock driver 230 whose driver capability is controlled by the driver control circuit 260 is configured as shown in FIG. 4.

4 illustrates the clock driver of FIG. 2.

Referring to FIG. 4, the clock driver 230 includes a NAND gate NAND and a plurality of inverters INV. In addition, inverters are generally connected to a larger size toward the rear end.

In an embodiment of the present invention, among the inverters having a larger size toward the rear end, only the rear end may be adjusted in size, or only a certain number of inverters may be adjusted in the rear end.

In an embodiment of the present invention, in order for all the inverters to be adjustable in size, each of the inverters INV is made larger or smaller according to the current control enable signal Current control_EN. Here, the size is the size of the ability to invert the input signal to pull up or pull down.

The clock signal CLK_osc and the clock enable signal CLK_EN are input to the NAND gate NAND of the clock driver 230.

In response to the clock enable signal CLK_EN, the NAND gate NAND inverts the clock signal CLK_osc or outputs the inverted signal at a high level.

The inverter INV of the last stage among the inverters that output the first clock CLK, among the inverters INV, will be described.

Inverters INV included in the clock driver 230 according to an exemplary embodiment of the present invention include fifth and sixth PMOS transistors P5 and P6 and fifth NMOS transistor N4, respectively.

The fifth and sixth PMOS transistors P5 and P6 and the fifth NMOS transistor N5 are connected in series between a power supply voltage VDD and a ground node.

The gates of the sixth PMOS transistor P6 and the fifth NMOS transistor N5 are connected in common and are connected to the output terminal of the previous inverter.

The first clock CLK1 is output from the connection point of the sixth PMOS transistor P6 and the fifth NMOS transistor N5.

The current control enable signal Current control_EN is input to the gate of the fifth PMOS transistor P5.

When the current control enable signal Current is input at 0V, the fifth PMOS transistor P5 is turned on. Therefore, the inverter INV speeds up the pull up. That is, there is an effect of increasing the size of the inverter INV.

When the current control enable signal Current is input to the voltage VPP1, the fifth PMOS transistor P5 is turned off. As a result, the inverter INV becomes smaller in size. The smaller size reduces current consumption.

FIG. 5 is a diagram illustrating voltages output for describing an operation of the voltage providing circuit of FIG. 2.

Referring to FIG. 5, when the voltage providing circuit 200 starts to operate, the output voltage VPP of the pump circuit 210 is initially 0V.

At this time, the first voltage V1 is also 0V. Therefore, the clock enable signal CLK_EN is output at a high level.

Since the clock enable signal CLK_EN is at a high level, the clock driver 230 outputs the first and second clocks CLK1 and CLK2.

At this time, since the first voltage V1 is 0V, the current control enable signal Current control_EN from the driver controller 260 is 0V.

When the current control enable signal (Current control_EN) is input as 0V, the fifth NMOS transistor P5 of the inverter IN of the clock driver 230 maintains a turn-on state. Therefore, the driver capability of the clock driver 230 is increased. As the driver capability of the clock driver 230 increases, the pumping circuit 210 also increases the pumping efficiency, so that the voltage VPP rises rapidly.

As the voltage VPP rises, the first voltage V1 becomes greater than the second reference voltage Vref2 when the time t1 is reached. When the first voltage Verf2 is greater than the second reference voltage Vref2, the driver control circuit 260 outputs the current control enable signal Current control_EN at the voltage VPP1 level.

When the current control enable signal Current control_EN is output as the voltage VPP1, the fifth PMOS transistor P5 of the inverter IN of the clock driver 230 is turned off.

When the fifth PMOS transistor P5 is turned off, the size of the inverter IN decreases. Therefore, the driver capability of the clock driver 230 is reduced. However, the pump circuit 210 is not significantly affected by the decrease in the driver capability of the clock driver 230 because the voltage VPP is already raised to some extent.

In addition, since the current flowing through the inverter IN becomes small, the current consumption can be reduced.

When the voltage VPP rises to a desired level, the first voltage V1 becomes greater than the first reference voltage Vref1. Therefore, the regulation circuit 240 changes the clock enable signal CLK_EN to a low level. If the clock enable signal CLK_EN is at the low level, the clock driver 230 does not output the first and second clocks CLK1 and CLK2.

Therefore, the pump circuit 210 stops the pumping operation. When the pumping operation is stopped and the voltage VPP is lowered, the regulation circuit 240 changes the clock enable signal CLK_EN to a high level so that the pump circuit 210 pumps the voltage.

After the pump circuit 210 raises the voltage VPP to the desired voltage level, the driver control circuit 260 sets the current control enable signal Current control_EN to a high level while the operation is controlled by the regulation circuit 240. To keep.

Therefore, the current consumption can be reduced in the clock driver 230.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 shows a voltage output from a general voltage supply circuit.

2 is a voltage supply circuit according to an embodiment of the present invention.

3 illustrates the driver control circuit of FIG. 2.

4 illustrates the clock driver of FIG. 3.

FIG. 5 is a diagram illustrating voltages output for describing an operation of the voltage providing circuit of FIG. 2.

* Brief description of the main parts of the drawings *

200: voltage supply circuit 210: pump circuit

220: oscillator 230: clock driver

240: regulation circuit 250: reference voltage generation circuit

260: driver control circuit

Claims (11)

A pump circuit for outputting a pumped voltage in response to the first and second clock signals; A regulation circuit for outputting a pump enable signal to the pump circuit depending on whether an output has reached a target level; A driver control circuit for generating a current control enable signal according to whether the output of the pump circuit is close to a target level; And The first and second clock driving signals which are inverted from each other in response to the input clock signal according to the pump enable signal are generated and provided to the pump circuit, wherein the current amount of the first and second clock driving signals is the current. Clock Driver Controlled by Control Enable Signal Voltage supply circuit comprising a. The method of claim 1, The driver control circuit, And outputting the current control enable signal by determining whether a voltage level output from the pump circuit is a target level or a second voltage level lower than the target level by a first voltage. 3. The method of claim 2, The regulation circuit, A voltage supply circuit comprising comparing the divided voltage obtained by distributing the output voltage of the pump circuit by using the first and second resistors and the first reference voltage, and outputting the clock enable signal according to the comparison result; . The method of claim 3, The driver control circuit, A comparison circuit for comparing the divided voltage with a second reference voltage equal to or lower than the first reference voltage; And And a level shift circuit outputting the current control enable signal in response to an output of the comparison circuit. The method of claim 4, wherein The comparison circuit, And output a signal of a first logic level when the divided voltage is lower than the second reference voltage, and output a signal of a second logic level when the divided voltage is higher than the second reference voltage. The method of claim 5, The level shift circuit, If the signal output from the comparison circuit is of a first logic level, the current control enable signal is output at 0V, And output the current control enable signal at a second voltage if the signal output from the comparison circuit is at a second logic level. The method of claim 6, The clock driver, A logic gate inverting and outputting the input clock signal in response to the clock enable signal; A first inverter group including an even number of inverters connected in series for outputting the output of the logic gate as the first clock signal; And And a second inverter group including an odd number of inverters connected in series for outputting the output of the logic gate as the second clock signal. The method of claim 7, wherein In the first and second inverter group, And one or more inverters including the last stage inverter at which the first or second clock signal is output, in response to the current control enable signal, having a pull-up capability greater than that of other inverters. The method of claim 7, wherein In the first and second inverter group, each of the one or more inverters including the last inverter of the first or second clock signal is output, A first transistor receiving a power supply voltage and outputting a voltage according to a voltage level of the current control enable signal; A voltage comprising a second transistor and a third transistor connected in series between a terminal for outputting a voltage and a ground node and alternately turned on or off in response to a signal output from an inverter immediately preceding the first transistor; Supply circuit. The method of claim 9, And a connection point of the second and second transistors is an output terminal of the inverter. The method of claim 9, And the voltage output by the first transistor is inversely proportional to the voltage of the current control enable signal.

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