JPH02119443A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of high frequency noise by providing a mirror capacitor on a buffer circuit employing a C-MOS. CONSTITUTION:An output stage circuit 4 consists of a P-channel MOS-FET 41 and an N-channel MOS-FFT 43 in pairs connected in series between power supplies VDD and VSS, a P-channel MOS-FET 44 and an N-channel MOS-FET 45 acting like inverters in pairs, a mirror capacitor 42 connected between gates and drains of the MOS-FETs 44, 45 and an output terminal 46 connecting to the mirror capacitor 42 and the drain. Then an output being the inverted input obtained from an input stage circuit 3 is outputted from the output terminal 46. Thus, production of high frequency noise is prevented and sure digital communication is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is directed to a C-
This invention relates to an output buffer circuit using MOS.

(Prior art) Conventionally, output buffer circuits are C-M in terms of noise resistance, etc.
It was generally configured by an OS. This C-M
The output buffer circuit consisting of the OS has inverters configured as shown in FIG. 10 connected in two stages. The diagram shown in FIG. 1 shows only one stage of inverters for the sake of explanation. When an input signal is applied to the input terminal 32 of this inverter, the output is inverted as shown by the dashed line in FIG. This output waveform was not necessarily ideal because it was affected by overshoot and transmission line impedance.

When this output buffer circuit made of a CMOS inverter is used as an output section for pulse transmission, its switching operation becomes a major source of electromagnetic noise. Further, when an overshoot as shown in the figure is added to this switching operation, even higher frequency electromagnetic noise is generated.

Therefore, if this output buffer circuit is used in a transmission circuit for multiplex communication in a car, for example, the generated electromagnetic wave noise becomes radio noise and interferes with radio reception.

Therefore, several preventive measures have been considered to prevent these radio wave interferences generated from the output stage of the output buffer circuit.

One method is to connect an RC filter.

In this method, as shown in FIG. 12, an RC filter consisting of a resistor 5 and a capacitor 6 is connected to the output side of the subsequent inverter. Thereby, as shown by the broken line in FIG. 13, it is possible to attenuate high frequency components and at the same time make the rise of the waveform gradual.

Another method is to use an integrator, a simplified form of which is shown in Japanese Patent Application Laid-Open No. 6/152125.

This can be done by forming an integrator with an operational amplifier 7, a resistor 5, and a capacitor 6 as shown in FIG. 14, and connecting it to the output of the output buffer circuit, as shown in FIG.
The rise time and fall time can be controlled.

(Problem to be Solved by the Invention) However, when the RC filter is connected as described above, the steepest part of the rise and fall occurs immediately after the start of the rise or fall, as shown in Figure 13. be. Therefore, if the resistor 5 and capacitor 6 are set so that the slope of the steepest part is gentle, the slope after that will become even gentler, and the overall waveform of the pulse will be greatly distorted. It becomes susceptible to noise (GND noise, etc.), and the benefits of digital communication are diminished.

In addition, since the deformation of the pulse waveform also depends on the stray capacitance on the output side, it is difficult to accurately control the flJl at the rising and falling times.
For example, it is impossible to reliably prevent the generation of electromagnetic noise in radio bands and the like.

If an integrator consisting of an operational amplifier of another method is connected, it is possible to accurately control the rise and fall times as shown in Figure 15, but the start of rise and fall and the There is a drawback that the end portion has a steeper slope and generates high frequency components.

As described above, in a vehicle equipped with a radio receiver, it is necessary to remove at least the band corresponding to the radio band from the electromagnetic noise generated from the output buffer circuit installed on the transmission path in the vehicle. for that,
When an RC filter or an integrator is installed at the output of the output buffer circuit, these conventional methods may remove harmful high-frequency components, but the pulse waveform will be distorted, and the benefits of digital communication may be lost. I can't.

Furthermore, each method has its advantages and disadvantages, such as even if it is possible to control the rise and fall times without impairing the pulse waveform, it is not possible to prevent the generation of high-frequency noise. As a result, there is a problem in that the applications for installing pulse transmission lines equipped with these output buffer circuits are limited.

(Purpose of the Invention) This invention was made to solve the above-mentioned conventional problems, and its purpose is to prevent the generation of high frequency noise and to enable accurate digital communication. An object of the present invention is to provide an output buffer circuit.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a pair of current sources installed on the positive power supply side and a ground side, respectively, and a current source connected between the pair of current sources. an inverter consisting of a C-MOS inverter having an input terminal and at least one of an N-channel and a P-channel MOS-FET connected to the output terminal of the inverter; and between the input terminal and the output terminal of the inverter. and a capacitor connected to.

(Function) In this invention, when the pulse input from the input terminal rises or falls, the M
In the non-saturated region of the OS-FET, the output starts rising or falling smoothly4, and when it moves to the saturated region,
Due to the capacitor connected between the input terminal and output terminal of the inverter, the slope changes according to the capacitance of the capacitor, and when it moves to the non-saturation region of other MOS-FETs,
The convergence value is reached smoothly. Therefore, by appropriately adjusting the capacitance of the capacitor, the slope of the output pulse can be set so as not to interfere with digital communication, and harmful high frequency components can be removed from the output pulse.

(Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of a buffer circuit according to the present invention.

The buffer circuit includes a reference potential generation circuit 1, a high impedance (HZ) setting circuit 2, an input stage circuit 3, and an output stage circuit 4.

The reference potential generation circuit 1 includes a P-channel type MO3-FETI 1 connected in series between the power supply VDIl+vss,
It is composed of a resistor 12 and an N-channel type MO5-FETI 3, and generates reference voltages V, , Vt at the gate terminals connected to the respective drains. This reference voltage v1 passes through the transmission gate 24 of the high impedance (HZ) setting circuit 2, and then passes through the P of the input stage circuit 3 and the output stage circuit 4.
They are added to the gate terminals of channel type MO3-FETs 31 and 41, respectively. Similarly, the reference voltage vt is high.
After passing through the transmission gate 25 of the impedance (HZ) setting circuit 2, it is applied to the gate terminals of the N-channel type MO3-FETs 33 and 43 of the input stage circuit 3 and the output stage circuit 4, respectively.

High impedance (HZ) setting circuit 2
m. , ■P-channel type MO3-F connected between 88
ET21, N-channel type MO3-FET23, transmission gate 24.25, inverter 22, and terminal 26. A digital signal applied to terminal 26 opens and closes transmission gate 24.25, and the reference voltages V + and V t. By controlling the transmission, the output from the output stage circuit 4 is selectively designated as an output state and an output inhibited state.

The input stage circuit 3 includes two pairs of P-channel type MO3-FETs 31 connected in series between power supplies VIllll+VB2,
N Chi+ * JL/type MO3-FET33, and P
Channel type MO3-FET34, N channel type MO3-
Consists of FET35, input terminal 32, input terminal 3
2, the input signal input to P-channel type MO3-FET34 and N-channel type M
An inverted output is applied to the gate terminal of the O3-FET 35 and obtained from their mutually connected drain terminals, and sent to the output stage circuit 4.

The output stage circuit 4 includes two pairs of P-channel type MO3-FET41 and N-channel type MO3-FET43 connected in series between the power supply ■Dl+vss, and a P-channel type MOS-FET44 and N-channel type that function as an inverter. MO3-FET45, Cholera MO3-FET44.
The mirror connected between the gate terminal and drain terminal of 45
It is composed of a capacitor 42, a mirror capacitor 42, and an output terminal 46 connected to the drain terminal, and an output obtained by inverting the input obtained from the input stage circuit 3 is sent to the output terminal 4.
It is output from 6.

Next, the operation of this buffer circuit will be explained.

Reference voltages V, , V generated in the reference potential generation circuit l
t is expressed as follows.

V+=V*e (V?MP+ΔF) −・・・−T
l1V, = V, H, +Δ8 ・・・・・・・・・・・・
・・・－・・・(2) Here, Vllll is the power supply voltage, V
? MN+V? MPs are N and P channel type MOs, respectively.
3-FBTII, which is the threshold voltage of 13.

Also, the gains of N and P channel type MO3-FETI 1°13 are β8. Let β□ be, and the current flowing through the resistor 12 is 1. Then, Δ□ Δ, respectively, are Δ−5 million pi・・・・・・・・・・・・・・・(
3) Δage 2 t, //j, +・・・・・・・・・・・・
......(4).

In addition, the current 11 is calculated as follows: i I= (V+-Vx)/R-・=・=・=(51
is given by

Therefore, if the current flowing through the input stage circuit 3 is 18, the current ig is 1l-a-t,...
......(6).

Here, high impedance (HZ) Q constant circuit 2
In a state where the input to the terminal 26 of is kept at the L level, that is, the manual stage circuit 3 and the output stage circuit 4 are in the operating state, the signal input to the input stage circuit 30 input terminal 32 changes from the L level to ■( When the voltage rises to level ■..., N-channel type MO3-FET35 is turned on,
3-FET34 is turned off, and N-channel type MO3-F
A current l flows through the ET33.

As a result, N, P channel type MO3-FET34.35
The potential of the node 36 connecting the drain terminal of the output stage circuit 4 and the mirror capacitor 42, etc. falls, and the output terminal 4 of the output stage circuit 4 drops.
The potential of 6 increases and reverses.

In the process of increasing and inverting the potential of the output terminal 46, when the P-channel type MO5-FET 34 turns off and the N-channel type MO3-FET 35 turns on, the charge starts to flow from the node 36 to the ground side. When the current iz passing through the N-channel MO3-FET 33 is (6
), the value is proportional to the current 11, and the rate of fall of the potential of the node 36 is determined according to the capacitance of the mirror capacitor 42. As the potential of node 36 decreases, the potential of output terminal 46 increases. Also, at this time, node 3
P-MO 344 of output stage circuit 4 as the potential of 6 decreases.
turns on after passing through the non-saturation region, and a current flows from the positive power supply side of the output stage circuit 4 to the ground side.

When the potential of the node 36 further decreases, the N-MO545
turns off after passing through the non-saturation region, current is supplied from the positive power supply side of the output stage circuit 4 to the output terminal 46, and the output terminal 46
becomes stable at H level.

In this way, at the start and end of the rise of the H level signal input to the input terminal 32, either the P-MO 344 or the N-MO 345 that constitutes the inverter of the output circuit 4 enters the non-saturation region, and the gate terminal The output terminal 4 exhibits the characteristic of flowing current according to the voltage applied to the
It acts to soften the change in potential of 6.

In addition, in the saturated region between these upper and lower unsaturated regions, due to the action of the Miller capacitor, a constant slope ΔV/Δt
By changing the potential by = V z / Cz,
An output waveform as shown in FIG. 2 is obtained. Note that C2 is the capacitance of the Miller capacitor, and in this case, stray capacitances such as gate capacitance and wiring capacitance are ignored.

Note that even when the input signal falls, a warm output waveform can be obtained.

Next, the waveform of the output signal will be explained in more detail.

FIG. 3 shows an equivalent circuit at the start of rising of the buffer circuit shown in FIG. 1, in which the input side voltage v1. The output side voltage v0 can be expressed by the following differential equation.

C0 is the load capacitance after the output terminal 46.

'P+ IN is a radio wave flowing through the N and P channel type MO3-FETs 44 and 45 of the output stage circuit 4;
If the gains of P-channel type MO3-FET44 and P-channel type MO3-FET44.45 are β7 and β8, respectively, the current ' P l i
H is expressed as follows.

β.

i8=βN(v, vytt)V.・・・・・・・・・・・・
...01 At the start of rising, N-channel type MO3
- Since the FET 45 is a non-saturated tilting gate, formula 01 applies.

Furthermore, if we solve equations (7) and (8) for ■1, we get d
t dt dt CH dt dt Note that C7 is the capacitance of the Miller capacitor, C9N is the gate capacitance of the N-channel MO5-FET 45, and CH C, +C.

io becomes ■. is included, so the coalition is not solved.Here, Co:'$' is regarded as CM, and 2O
If we omit the second term on the right side of D, then if we further set C, , 1 < C, and set it as C umbrella''-C0, then 2 α1 is dV.

0M Then, by integrating, ■. =At3+Bt"+Ct C♂ C2, and when solved considering the initial conditions, t V, = V., -v7 At......a9 0M Furthermore, equations (7), (8) Solving for V, we get 2
CM Ct Here, when comparing the coefficients A, B, and C, A>B)D, so 2〇l is V, #At'・・・・・・・・・・・・・・・・・・・・・・・・
・CM from 0 type (to) which can be considered as close to the evil waveform”
C9N Furthermore, formula (9), 01. , Q! 9 is substituted into the equation Q*2, t CM "C*) 1 (C-2 In other words, at the start of the rise, the slope of Start.

As described above, according to the present invention, a waveform having a gentle curve at the start of rising can be obtained, and generation of high frequency components can be prevented.

Next, think about your midsection when you stand up. Since the N-channel type MO3-FET 45 of the output stage circuit 4 has reached the saturation region, feedback is applied by the Miller capacitor 42, and the formula (7) becomes: V, = t...・・・・・・
...(24) Since the value is within the range of 0.001, it is possible to easily set an output waveform with an arbitrary slope. As a result, it is possible to prevent the occurrence of harmful high frequency components with a steep slope, and it is also possible to prevent distortion of the waveform due to the slope being too gentle, which can be an obstacle to digital IL communication.

Furthermore, in the process of settling down to the final H level voltage after the midpoint of the rise, a waveform consisting of a smooth curve can be obtained based on the same logic as at the beginning of the rise.

In this way, at the time of rise, the waveform changes to have extremely gentle curves at the beginning and end, and in the middle, the displacement occurs almost in a straight line with a slope that can be arbitrarily set on the circuit.

Similarly, each part acts on the falling edge as well as the rising edge, resulting in a smooth waveform change.

FIG. 4 is a circuit diagram showing the second embodiment.

This embodiment simply configures the high impedance (HZ) setting circuit 2 in the first embodiment, and transfers the control signal input to the terminal 26 to the N-channel type MO3 of the output stage circuit 4.
-FET 43, and the control signal is inverted by the inverter 22. Therefore, the slope of the output waveform is that of the P-channel type MO3-FET 41.

In this embodiment, compared to the first embodiment, the rise
Although the straight line part in the middle of the fall is slightly narrowed, it has the advantage that the circuit can be easily constructed.

Since the details are the same as those in the first embodiment, their explanation will be omitted.

FIG. 5 is a circuit diagram showing a third embodiment.

This embodiment is based on the reference potential generation circuit 1 in the first embodiment.
The resistor 12 is replaced with an N-channel MO5-FET 17.
a, a capacitor 18 with a capacity C, and an N-channel MO
3-FETI7b. N-channel type MO3-FE
An equivalent resistance R1 is generated by applying clock pulses φ and φ of frequency Hr to T17a and 17b via NOR gates 16a and 16b. This equivalent resistance R3
is R,−・・・・・・・・・・・・(25) fC2 Δt fC.

becomes.

In this way, the frequency f of the clock pulse that determines the slope of the output waveform can be obtained from a highly accurate CERALOCK or crystal oscillator, and the capacitance ratio C+/C2 can also be manufactured with high precision on a semiconductor substrate. In this example,
The rising or falling slope ΔV/Δt can be controlled with high precision.

FIG. 6 is a circuit diagram showing a fourth embodiment.

This embodiment is based on the reference potential generation circuit 1 in the second embodiment.
, N-channel type MO3-FET17a, and capacitance IC+
capacitor 18 and N-channel type MO3-FETI
7b is replaced with a switched capacitor consisting of N-channel type MO3-FBTI 7 a,
By applying clock pulses φ and φ of frequency r to 17b, an equivalent resistance R3 is generated as in the third embodiment. The rest of the structure is the same as in the 2.3 embodiment. Note that the capacitor 47 shown on the output terminal 46 side is a capacitor obtained by removing stray capacitance on the load side.

FIG. 7 is a circuit diagram showing the fifth embodiment.

In this embodiment, the output stage circuit 4 is composed of a P-channel type MO3-FET 44 connected to the power supply Vllll side, and this MOS
- It is constituted by a mirror capacitor 42 connected between the gate terminal and the drain terminal of the FET 44, and an output terminal 46 connected to the mirror capacitor 42 and the drain terminal, and has an open drain output. Other parts are the same as the fourth embodiment.

FIG. 8 is a circuit diagram showing a sixth embodiment.

In this embodiment, the output stage circuit 4 is composed of an N-channel type MO3-FET 45 connected to the power supply VS3 side, and this MOS-FET 45.
Consisting of a Miller capacitor 42 connected between the gate terminal and drain terminal of the FET 45, an output terminal 46 connected to the Miller capacitor 42 and the drain terminal,
This is an open drain output. Other parts are the same as the fourth embodiment.

FIG. 9 is a circuit diagram showing a seventh embodiment.

This embodiment is provided with three reference potential generation circuits 1.1' and 1.1'', each composed of a switched capacitor, and the reference potential generation circuit 1 is connected to the input stage circuit 3.
drive the current source.

The reference potential generation circuit 1' generates a reference voltage v1 for driving the P-channel type MO3-FET 41, which is one current source of the output stage circuit 4.

The reference potential generation circuit 1' generates a reference voltage V for driving the N-channel type MO3-FET 43, which is the other current source of the output stage circuit 4.

In this embodiment, independent reference potential generation circuits 1' and 1# are provided on the power supply side and the ground side, so the slope of the rising and falling waveforms of the output waveform can be adjusted by setting the capacitance of each capacitor. can be set separately.

As is clear from the description of each of the embodiments above, the buffer circuit according to the present invention has a relatively simple circuit configuration, making it possible to set the shape of the output waveform to a smooth arbitrary slope. Not only can communications be performed reliably, but also the generation of high frequency components harmful to digital communications can be prevented.

(Effects of the Invention) As described above, the present invention provides a buffer circuit using C-MOS with a Miller capacitor, thereby making it possible to arbitrarily set the rising or falling slope of the output waveform. As a result, when used in digital communications, it is possible to optimize the slope of the output waveform and prevent the generation of high frequency noise that is harmful to radio receivers and the like.

In particular, when the buffer circuit according to the present invention is used in a pulse transmission circuit for a vehicle or the like, there is no need to consider noise countermeasures for nearby radio receivers, and the degree of freedom in design can be increased accordingly.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of a buffer circuit according to the present invention, FIG. 2 is a diagram showing input and output waveforms,
Fig. 3 is an equivalent circuit diagram at the start of rising in Fig. 1, Fig. 4 is a circuit diagram showing the second embodiment, Fig. 5 is a circuit diagram showing the third embodiment, and Fig. 6 is a circuit diagram showing the fourth embodiment. FIG. 7 is a circuit diagram showing the fifth embodiment, and FIG. 8 is a circuit diagram showing the sixth embodiment.
9 is a circuit diagram showing a seventh embodiment, FIG. 10 is a diagram showing a part of a conventional buffer circuit,
Fig. 11 is a diagram showing the input and output waveforms in Fig. 10, Fig. 12 is a circuit diagram showing a conventional example, and Fig. 13 is a diagram showing the input and output waveforms in Fig. 10.
14 is a circuit diagram showing the integrator used in the conventional example, and FIG. 15 is the circuit diagram showing the integrator used in the conventional example.
FIG. 4 is a diagram showing input and output waveforms in FIG. 4; 1.1', 1'...Reference potential generation circuit l Q
a; l Ob...P channel type MOS -
F ETll, 14...P channel type MO3-
FET12...Resistance 13.15...--N-channel type MO3-FET1
6 a, 16 b...---NOR gate 16 c,
16 d---NAND gate 17a-d-N channel type MOS-FET18.18a~C... Capacitor 19 a, 19 b---P channel type MO3-FET2... ...High impedance (H2) setting circuit 21...P channel type MO
3-FET22.22a, 22b...Inverter 23...N-channel type MO3-FET22.
25...Transmission gate 26...Terminal 3...Input stage circuit 31...P channel type MOS-FET32
...Input terminal 33.35...N-channel type MO3-FET3
4...P channel type MOS-F RT36・
...Node 4...Output stage circuit 41.44...P-channel type MO3-FET4
2...Miller capacitor 43.45...N-channel type MO3-FET4
6... Output terminal patent applicant Shigenori Wada, representative patent attorney for Nissan Motor Co., Ltd. 1 Figure 35.45: N-MOSFET 4 Figure 2 Figure 3 Figure 5 Figure 6 Figure 35.45: N-MOSFET 4 Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 Figure 8 Figure 10 Figure 12

Claims (1)

[Claims] 1. A pair of current sources installed on the positive power supply side and the ground side, a C-MOS inverter connected between this pair of current sources and equipped with an input terminal, and connected to the output end of this inverter. N and P channel type MO
An output buffer circuit comprising an inverter made of at least one S-FET, and a capacitor connected between an input end and an output end of the inverter.