JPH08204517A - Oscillation circuit - Google Patents

Abstract

PURPOSE: To suppress the frequency fluctuation of a clock signal obtained from the oscillation circuit even in the case of occurrence of fluctuation of a power supply voltage or of dispersion in components of the oscillation circuit provided in an integrated circuit in the case of manufacturing the semiconductor integrated circuit. CONSTITUTION: When an output voltage from a comparator 13 is Vss, a PMOS transistor(TR) 16 is conductive and a constant current ΔI in response to the potential difference between a power supply voltage Vdd and a reference voltage flows to the PMOS TR, a resistor 18 and an NMOS TR 21. A capacitor 9 is discharged through an NMOS TR 25 by a constant current ΔI attended therewith, and when an NMOS TR 17 is conductive with the output voltage of the comparator 13 reaching a voltage Vdd, a constant current ΔI in response to the potential difference between a ground level voltage and the reference voltage is supplied to a PMOS TR 20, the resistor 18 and the NMOS TR 17. Thus, a capacitor 9 is charged by the constant current ΔI flowing to the PMOS TR 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit using resistors and capacitors.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a conventional RC oscillator circuit. It should be noted that the one-dot chain line is, for example, inside the microcomputer. In FIG. 3, (1) and (2) are oscillation terminals provided in the microcomputer (3).
A resistor (4) is externally connected between the oscillation terminals (1) and (2), and a capacitor (5) is externally connected between the oscillation terminal (1) and ground. Further, inside the microcomputer (3), the input terminal of the Schmitt inverter (6) is connected to the oscillation terminal (1) and the output terminal of the Schmitt inverter (6) is connected to the oscillation terminal (2). As described above, the RC oscillation circuit is configured, and the clock signal for controlling the internal operation of the microcomputer (3) is obtained from the output terminal of the Schmitt inverter (6).

[0003]

However, the hysteresis width and the output impedance of the Schmitt inverter (6) in FIG. 3 are caused by fluctuations in the power supply voltage, variations in element characteristics when manufacturing a semiconductor integrated circuit such as a microcomputer, and the like. Due to the cause, it was difficult to keep constant, and as a result, it was difficult to obtain a clock signal of constant frequency.

Therefore, the present invention can be obtained from an oscillation circuit even when the power supply voltage fluctuates or variations occur in the element characteristics of the components of the oscillation circuit provided inside the semiconductor integrated circuit when the semiconductor integrated circuit is manufactured. It is an object of the present invention to provide a configuration capable of suppressing frequency fluctuation of a clock signal to be generated.

[0005]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a reference voltage generating circuit for generating a reference voltage and one input terminal are provided. Is connected to a comparator to which a hysteresis reference voltage created based on the reference voltage is applied and the terminal voltage of the capacitor is applied to the other input end, and a first P connected in series between the power supply and ground. A first inverter circuit including a channel type MOS transistor and a first N-channel type MOS transistor, which operates by receiving the output of the comparator, and a resistor having one end connected to the output end of the first inverter circuit. And an operational amplifier in which the reference voltage is applied to one input terminal and the other input terminal is connected to the other end of the resistor, and a second P-channel connected in series between the power supply and ground. A second inverter circuit, which comprises a channel MOS transistor and a second N-channel MOS transistor, is operated by receiving the output of the operational amplifier, and the output is fed back to the other input terminal of the operational amplifier; A third P connected in series between the power supply and ground
A third inverter circuit comprising a channel-type MOS transistor and a third N-channel-type MOS transistor, which operates by being applied with the output of the operational amplifier, and whose output is fed back to the other input terminal of the comparator. According to a constant current flowing through the resistor according to the output of the comparator, the capacitor charges and discharges linearly within the hysteresis width of the comparator, and the charging and discharging voltage of the capacitor is a triangular wave signal. Is.

[0006]

According to the present invention, when the output of the comparator is at the first voltage level, the first P-channel type MOS transistor becomes conductive, and accordingly, the constant current is changed to the first value in accordance with the potential difference between the power supply and the reference voltage. 1 P-channel type MOS transistor,
It flows through the resistor and the second N-channel type MOS transistor, and accordingly, the capacitor is connected to the third N-channel type M transistor.
Discharging only the constant current through the OS transistor,
When the output of the comparator is at the second voltage level, the first N
A constant current flows through the second P-channel MOS transistor, the resistor and the first N-channel MOS transistor in accordance with the potential difference between the reference voltage and the ground as the channel MOS transistor becomes conductive. Charges according to the constant current flowing through the third P-channel MOS transistor.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing an oscillator circuit of the present invention. The right side from the chain line shows the inside of the microcomputer. In FIG. 1, (7) is an oscillation terminal provided in the microcomputer (8), and a capacitor (9) is connected between the oscillation terminal (7) and the ground outside the microcomputer (8). There is. The internal configuration of the microcomputer (8) will be described below.

Numerals (10) and (11) are resistors connected in series between the power source Vdd and the ground. In the present embodiment, the resistors (10) and (11) have the same resistance value, and the resistors (10) and (11) are the same.
It is assumed that Vdd / 2 can be obtained from the connection point of (11). (12) is an operational amplifier, the + (non-inverting input) terminal is connected to the connection midpoint of the resistors (10) and (11),
The (inverting input) terminal is connected to the output terminal. That is,
A voltage follower circuit is composed of the resistors (10) and (11) and the operational amplifier (12), and a reference voltage of Vdd / 2 is generated from the output terminal of the operational amplifier (12). The above is the configuration of the reference voltage generation circuit.

Reference numeral (13) is a comparator, the negative terminal of which is connected to the non-grounded end of the capacitor (9) through the oscillation terminal (7), and the output terminal of which is connected in series with the resistor (14).
It is connected via (15) to the output terminal of the operational amplifier (12), and the + terminal is connected to the connection midpoint of the resistors (14) and (15). In this embodiment, the resistance values of the resistors (14) and (15) are the same, and although not shown, the comparator (1
The power supply input 3) is connected between the power supply Vdd and the ground. That is, in the comparator (13), a reference voltage (Vdd / 4 or 3Vdd / 4) having hysteresis is applied to the + terminal, and the reference voltage and the charging / discharging voltage of the capacitor (9) applied to the-terminal are compared. It is for comparison. Specifically, the output c of the comparator (13) is at a high level (= Vdd)
At this time, the reference voltage b applied to the + terminal becomes 3Vdd / 4, and 3Vdd / 4 is compared with the terminal voltage of the capacitor (9). When the output c of the comparator (13) is at a low level (= 0), the reference voltage b applied to the + terminal is Vd.
d / 4, and Vdd / 4 is compared with the terminal voltage of the capacitor (9).

(16) is a (first) P-channel MO
S transistors (hereinafter referred to as PMOS transistors) and (17) are (first) N-channel type MOS transistors (hereinafter referred to as NMOS transistors), and each drain / source path is connected in series between the power supply Vdd and ground. The respective gates are connected together and are commonly connected to the output terminal of the comparator (13). The PMOS transistor (16) and the NMOS transistor (17)
The first inverter circuit is constituted by the above. Reference numeral (18) is a resistor, one end of which is connected to the output of the first inverter circuit, that is, the drains of the PMOS transistor (16) and the NMOS transistor (17).

Reference numeral (19) is an operational amplifier, the + terminal is connected to the other end of the resistor (18), and the reference voltage a is applied to the-terminal.
(= Vdd / 2) is applied. That is, the operational amplifier (19) operates so that the + terminal input coincides with the-terminal input. (20) is a (second) PMOS transistor,
(21) is a (second) NMOS transistor, P
In the MOS transistor (20), the source is connected to the power supply Vdd through the resistor (22) and the drain is N
It is connected to the drain of the MOS transistor (21) and its gate is connected to the gate of the NMOS transistor (21). The source of the NMOS transistor (21) is grounded via the resistor (23). The above constitutes the second inverter circuit. The inputs of the second inverter circuit, that is, the gates of the PMOS transistor (20) and the NMOS transistor (21) are connected to the output terminal of the operational amplifier (19), and the second inverter circuit is connected. Inverter circuit output or PMO
S transistor (20) and NMOS transistor (2
The drain of 1) is connected to the + terminal of the operational amplifier (19).

Further, (24) is a (third) PMOS transistor, and (25) is a (third) NMOS transistor. In the PMOS transistor (24), the source is connected to the power supply Vdd via the resistor (26). The drain is connected to the drain of the NMOS transistor (25), and the gate is connected to the gate of the NMOS transistor (25). The source of the NMOS transistor (25) is grounded via the resistor (27). The above constitutes the third inverter circuit, and the input of the third inverter circuit, that is, the PMOS transistor (24) and the NM.
The gate of the OS transistor (25) is an operational amplifier (1
The output of the third inverter circuit, that is, the drains of the PMOS transistor (24) and the NMOS transistor (25) are connected to the output end of the capacitor 9), and one end of the capacitor (9) on the non-grounded side through the oscillation terminal (7). Connected with.

Although not shown, the operational amplifier (1
The power input of 9) is also connected to Vdd and ground. However, the maximum output voltage of the operational amplifier (19) is Vdd-
It is α and it is difficult to have linearity in the range of Vss + α. Therefore, in order to obtain an output with linearity, both the second and third inverter circuits have resistors (22) (2
3) (26) and (27) are provided.

The operation of the oscillator circuit of the present invention having the above configuration will be described below with reference to the waveform chart of FIG. First, a description will be given from the time when the capacitor (9) discharges and the terminal voltage d of the capacitor (9) drops to the hysteresis reference voltage b of the comparator (13). At this time, the output voltage c of the comparator (13) is 0 volt (= Vss), and the hysteresis reference voltage b applied to the + terminal of the comparator (13) is Vdd / 4. When the terminal voltage d of the capacitor (9) drops to the hysteresis reference voltage b (= Vdd / 4), the output voltage c of the comparator (13) rises to Vdd and the hysteresis reference voltage b rises to 3Vdd / 4. Then, the output voltage c of Vdd causes NMO
The S-transistor (17) becomes completely conductive, and accordingly, the + terminal input of the operational amplifier (19) becomes lower than the-terminal input, and the output according to the potential difference between the + and-terminals of the operational amplifier (19) causes PMOS. The transistor (20) is conducting,
A current ΔI flows through the path of the resistor (22), the PMOS transistor (20), the resistor (18) and the NMOS transistor (17). Here, since the operational amplifier (19) operates so as to match the voltage at the + terminal with the reference voltage Vdd / 2 at the − terminal, the voltage at one end of the resistor (18) is 0 V and the voltage at the other end is Vdd / 2. And the resistance value of the resistor (18) becomes R
Then, the current flowing through the resistor (18) ΔI = Vdd / 2
It becomes R. Therefore, a constant current of ΔI flows through the PMOS transistor (20). In other words, PM
The output of the operational amplifier (19) is determined so that a constant current of ΔI flows through the OS transistor (20). Therefore, PM
A constant current ΔI also flows through the OS transistor (24), the capacitor (9) charges this constant current ΔI, and the terminal voltage d of the capacitor (9) increases linearly.

After that, when the terminal voltage d of the capacitor (9) rises to the hysteresis reference voltage b (= 3Vdd / 4) applied to the + terminal of the comparator (13), the comparator (1
The output voltage c of 3) falls to Vss, and the hysteresis reference voltage b falls to Vdd / 4. Then Vss
The output voltage c of the PMOS transistor (16) makes the PMOS transistor (16) completely conductive, and accordingly, the + terminal input of the operational amplifier (19) rises higher than the-terminal input, and the + of the operational amplifier (19) becomes +.
The NMOS transistor (21) is turned on by the output corresponding to the potential difference between the and terminals, and the PMOS transistor (1
The current ΔI flows through the path of 6), the resistor (18), the NMOS transistor (21) and the resistor (23). Here, the operational amplifier (19) changes the voltage at the + terminal to the reference voltage V at the − terminal.
Since it operates so as to match dd / 2, the voltage at one end of the resistor (18) is Vdd and the voltage at the other end is Vdd / 2, that is, the potential difference across the resistor (18) is the same as when the capacitor (9) is discharged. If the resistance value of the resistor (18) is R, the current ΔI = Vdd / 2R flowing through the resistor (18) is obtained. Therefore, a constant current of ΔI flows through the NMOS transistor (21). In other words, the output of the operational amplifier (19) is determined so that a constant current of ΔI flows through the NMOS transistor (21). Therefore, the constant current ΔI also flows through the NMOS transistor (25), the capacitor (9) discharges the constant current ΔI, and the terminal voltage d of the capacitor (9) linearly drops. Hereinafter, the above operation is repeated.

Here, PMOS transistors (20) (24) and N are provided on the chip of the microcomputer (8).
When MOS transistors (21) (25) are built in, each transistor (20) (21) (24) (25)
Even if variations occur in the device characteristics of the operational amplifier (19), each of the transistors (20) (21) (24)
Since the operation is performed so that the current flowing through (25) is ΔI, the variations in the transistors (20), (21), (24) and (25) can be ignored.

Further, when the power supply Vdd fluctuates, the hysteresis width of the reference voltage applied to the + terminal of the comparator (13) is ΔV, the capacitance of the capacitor (9) is C, and the charge and discharge of the capacitor (9). ΔT is one cycle of
= C * ΔV / ΔI. Specifically, the resistance value R of the resistor (18) is R = 30 KΩ, and the capacitance C of the capacitor (9) is 39
Let's consider an example in which the power supply Vdd is changed from originally 5V to 6V or 4V with 0 pF. First, if the power supply Vdd fluctuates to 6 volts, Δ
I = 100 μA, ΔV = 3 volts, and ΔT is 11.7 μsec. Next, when the power supply Vdd fluctuates to 4 volts, ΔI = 66.7 μA and ΔV = 2 volts, and ΔT is 11.7 μsec. Both of them take a time to charge / discharge the capacitor (9) once. Will be the same.

From the above, even if the element characteristics on the chip of the microcomputer (8) vary or the power supply Vdd fluctuates, the terminal voltage d obtained by the charge / discharge operation of the capacitor (9) changes linearly, In addition, the time required for one charge / discharge does not change. Therefore, the third
Waveform obtained from the connection point of the PMOS transistor (24) and the NMOS transistor (25) which is the output of the inverter circuit of the above, that is, the terminal voltage d of the capacitor (9)
Through an inverter circuit having a threshold voltage of Vdd / 2, a clock signal having a constant frequency can be obtained. Then, the internal configuration of the microcomputer (8) can be stably operated based on this clock signal.

[0019]

According to the present invention, the characteristics of the constituent elements of the oscillation circuit may vary in the process of manufacturing the semiconductor integrated circuit,
Alternatively, even if the power supply voltage fluctuates during operation of the completed semiconductor integrated circuit, a triangular wave signal having a constant frequency can be obtained, and the controlled object can be stably operated.
Also, since the terminal voltage of the capacitor becomes a triangular wave signal with a constant frequency, a comparator that can change the reference voltage is provided in the latter stage,
The application of outputting the PWM control waveform is also possible.

[Brief description of drawings]

FIG. 1 is a diagram showing an oscillator circuit of the present invention.

FIG. 2 is a waveform diagram showing the operation of FIG.

FIG. 3 is a diagram showing a conventional oscillator circuit.

[Explanation of symbols]

 (10) (11) (14) (15) (18) Resistance (12) (19) Operational amplifier (13) Comparator (16) (20) (24) PMOS transistor (17) (21) (25) NMOS Transistor

Claims (2)

[Claims] 1. A reference voltage generating circuit for generating a reference voltage, wherein a hysteresis reference voltage created based on the reference voltage is applied to one input terminal and a terminal voltage of a capacitor is applied to the other input terminal. Comparator, a first P-channel MOS transistor and a first N-channel MOS transistor connected in series between a power supply and ground
A first inverter circuit which is formed of a transistor and operates by applying the output of the comparator, a resistor having one end connected to the output end of the first inverter circuit, and the reference voltage applied to one input end. An operational amplifier having the other input terminal connected to the other end of the resistor, a second P-channel type MOS transistor and a second N-channel type M connected in series between the power source and the ground.
A second inverter circuit, which is composed of an OS transistor, operates by receiving the output of the operational amplifier, and whose output is fed back to the other input terminal of the operational amplifier, and is connected in series between the power supply and ground. Third P-channel type MOS transistor and third N-channel type M
A third inverter circuit which is composed of an OS transistor, operates by receiving the output of the operational amplifier, and whose output is fed back to the other input terminal of the comparator, wherein the third inverter circuit is provided according to the output of the comparator. An oscillator circuit, wherein the capacitor charges and discharges linearly within a hysteresis width of the comparator according to a constant current flowing through a resistor, and the charging and discharging voltage of the capacitor is a triangular wave signal. 2. When the output of the comparator is at a first voltage level, a constant current is generated according to a potential difference between the power source and the reference voltage as the first P-channel type MOS transistor becomes conductive. First P-channel type MOS transistor, the resistor and the second N-channel type MOS transistor
When the capacitor discharges the constant current through the third N-channel type MOS transistor and the output of the comparator is at the second voltage level, the first voltage flows through the transistor. N-channel MOS
A constant current flows through the second P-channel type MOS transistor, the resistor and the first N-channel type MOS transistor in accordance with the potential difference between the reference voltage and the ground as the transistor is turned on. 2. The oscillator circuit according to claim 1, wherein the capacitor charges according to the constant current flowing through the third P-channel MOS transistor.