JPH02119319A - Crc code generation circuit - Google Patents

Abstract

PURPOSE:To realize a fast processing and to reduce the scale of a hardware by performing the time divisional multiplex processing of the CRC arithmetic operation of each line to a signal in which the signals with the same bit rate are multiplexed, and storing a computed value in an FF and a shift register transiently. CONSTITUTION:A CRC arithmetic circuit 11 performs a new arithmetic operation by an input serial signal and a CRC computation value before one cycle outputted from the FF 13 for holding CRC computation value. The computed value is held by the FF 13 again. Also, the arithmetic operation is applied on the frames from a first frame to an N-th frame, and the computed value of each of the lines CH1-CHm in each frame is written in the shift register 14 for retracting m-bit CRC arithmetic value. Also, a first arithmetic operation on the lines CH1-CHm in each frame is performed by selecting a shift register 14 side by a selection circuit 12, and continuing the arithmetic operation from a preceding frame. Therefore, fast processing can be realized, and the scale of the hardware can be miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a multi-processing type CRC code generation circuit for data communication. In particular, the present invention relates to a CRC code generation circuit at the line multiplex signal level in a transmission terminal equipment, etc., which employs a CRC code transmission method suitable for monitoring line failures.

〔overview〕

The present invention uses a multiprocessing type CRC code generation circuit to time-divisionally multiplex CRC calculations for each line on a signal obtained by multiplexing signals with the same bit rate, and temporarily converts the calculated value and CRC code. 1. Write down the flip-flop and shift register. α enables high-speed processing, reduces the scale of hardware, and improves economic efficiency.

[Conventional technology]

FIG. 4 is a block diagram of a conventional CRC code generation circuit. Figure 5 shows C and R of a conventional CRC code generation circuit.
FIG. 2 is a circuit diagram of a C calculation circuit. FIG. 6 is a time chart showing the operation of a conventional CRC code generation circuit.

Conventionally, multiprocessing type CRC code generation circuits have generated CRC codes for each line at the multiline signal level, but because the speed of the multiplex lines is multidimensional, the calculated value of the CRC operation and the CRC code cannot be generated. It was necessary to use a read/write memory as a temporary storage element.

4 to 6, the serial/parallel conversion circuit 22 converts the input serial signal into parallel data of the number n of CRC codes of the CRC generating polynomial. The CRC performance circuit 21 is
A new calculation is performed using this parallel data and one cycle of CRC calculation up to one cycle before output from the memory 25 for saving CRC calculation values. This calculated 1st shift is stored in the address area to which the line is assigned in the memory 25 for saving the CRC calculation value. Further, the calculation is performed from the first frame to the Nth frame. The final calculated value of each line (CHI to CHm) of the Nth frame, that is, the CRC
The code is extracted by the D-type flip-flop 26 and output in the next frame after the operation is completed. However, at the time of the first calculation of each line in the first frame, CR
By sending the initialization pulse P for C calculation, the CRC
The calculated values from the memory 25 for saving calculated values are cleared and the first calculation for each line is performed.

Figure 5 shows the degree n of 6 and the CRC code generation polynomial formula% A circuit example of the arithmetic circuit 21 in this case is shown.

In addition, in FIG. 6, FIG. 6(a) is a data signal having an N multi-frame configuration, FIG. 6(b) is a detailed diagram of the data signal of the lth multi-frame configuration, and FIG. 6(C) is a detailed diagram of the data signal of the address counter 24. 6(d) shows the initialization pulse P3 for CRC calculation, and FIG. 6(e) shows the CRC calculation result in the D-type flip-flop 23 in the memory for saving the CRC calculation value in multi-frame 1. 6(f) is the output of the D-type flip-flop 26 captured in FIG. 6(e) during multiframe 1. Here eLl~e (
β=1 to 6) is the CRC for channel CH, ~CH,
It is a sign.

[Problem that the invention seeks to solve]

However, in such a conventional multiprocessing type CRC code generation circuit, when the speed of multiple lines is multiple, the fourth
As shown in the figure, a read/write memory is used as an element to temporarily store the first operation of CRC operation and the CRC code,
Since it is necessary to access the memory 25 in one calculation cycle, it is necessary to convert the calculation signals into serial and parallel signals to make it possible to read and write to the memory 25 at a low speed. Further, when serial-parallel conversion is performed, one calculation becomes complicated, and the scale of the CRC calculation circuit increases as shown in FIG. 5. Such a circuit was also used when multiple lines had the same speed.

The present invention solves the above-mentioned drawbacks, and aims to provide an economical CRC code generation circuit with a small hardware scale when the speed of multiple lines is unified.

[Means for solving problems]

The present invention inputs a multi-frame data string in which multiple lines of the same speed are multiplexed, and initializes the 1-bit previous CRC calculation value and the 1-bit previous CRC calculation value with the first frame of the multi-frame. A CRC calculation circuit that performs CR and C calculations based on the initialization pulse, and this CRC
a flip-flop that temporarily stores the output of the arithmetic circuit; a shift register that stores the final value of the arithmetic operation of each line of each multi-frame among the outputs of the CRC arithmetic circuit; and an arithmetic operation of each line of each multi-frame. first start
It is characterized by comprising a selection means that selects the contents of the shift register at the bit, selects the output of the flip-flop at a timing other than the first bit, and provides the output as the CRC operation value of the previous bit. The CRC calculation circuit inputs a multi-frame data string in which multiple lines of the same speed are multiplexed, and calculates the CRC of the previous bit.
This 1 in the calculated value and the first frame of the multi-frame
A CRC operation is performed based on an initialization pulse that initializes the CRC operation value of the previous bit. The flip-flop temporarily records the output of the CRC calculation circuit.1. @do. shift register is C
The final value of the calculation for each line of each multiframe is stored in the RC function among the outputs of the circuit. The selection means selects the contents of the shift register at the first bit of the calculation start of each line of each multi-frame, selects the flip-flop output at a timing other than the first bit, and selects the contents of the shift register at the timing other than the first bit, and selects the contents of the shift register at the timing other than the first bit, and selects the contents of the shift register at the timing other than the first bit, and selects the contents of the shift register at the timing other than the first bit.
It is given to the CRC calculation circuit as a calculation company. The above operations enable high-speed processing, reduce the scale of hardware, and improve economic efficiency.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a CRC code generation circuit according to an embodiment of the present invention. In FIG. 1, the CRC code generation circuit inputs a multi-frame data string in which multiple lines of the same speed are multiplexed, and calculates the CRC calculation value of the previous bit and the first frame of the multi-frame. CR of
CR based on the initialization pulse P1 that initializes the C calculation value.
A CRC calculation circuit 11 that performs C operation I, and a D-type flip-flop 13 that temporarily stores the output of the CRC calculation circuit 11.
and a shift register 14 that stores the final value of the calculation of each line of each multi-frame among the outputs of the CRC calculation circuit 11, and a shift register 14 that stores the final value of the calculation of each line of each multi-frame; A selection circuit 12 serves as a selection means for selecting the contents of the register 14, selects the output of the flip-flop 13 at a timing other than the first bit, and provides the same as the CRC operation value of the previous bit, and a control circuit 15 provides a control pulse. The reason is that we have prepared the following.

The operation of the CRC code generation circuit having such a configuration will be explained. Figure 2 shows the CRC of the CRC code generation circuit of the present invention.
FIG. 3 is a circuit diagram of an arithmetic circuit. FIG. 3 is a time chart explaining the operation of the CRC code generation circuit of the present invention.

In FIG. 1, the CRC calculation circuit 11 performs a new calculation using the input serial signal and the CRC calculation (the CRC calculation residue from one cycle before, which is output from the flip-flop 13 for direct holding).The calculated value is as follows. It is held again in the flip-flop 13 for holding the CRC calculation value.The calculation i is performed from the 1st frame to the Nth frame, and each line (CH, -CH) of each frame from the 1st frame to the Nth frame is
, ) are written into the m-bit CR'C operation 1 direct save shift register 14. However, when calculating each line in the first frame, the CRC calculation circuit 11
The CRC calculation initialization pulse P1 clears the calculation value from the shift register 14 for saving the CRC calculation value,
The first to nth calculations for each line are performed.

In addition, for the first calculation of each line (CH, ~CH,) of each frame, the selection circuit 12 selects the shift register 14 side for saving the CRC calculation value, and continues the calculation from the previous frame. . Incidentally, FIG. 2 shows an example of the CRC calculation circuit 11 when the order n is 6 and the CRC code generation polynomial is the following formula.

In addition, in FIG. 3, FIG. 3(a) is a data signal with an N multi-frame configuration, FIG. 3(b) is a detailed diagram of the data signal of the first multi-frame, and FIG. 3(C) is a diagram of the CRC calculation. The initialization pulse Pl, FIG. 3(d) is used to capture the final calculated value of each line (CH to CH,) of each frame from the 1st frame to the Nth frame in the shift register 14 for direct saving of CRC calculation 1. The clock of FIG.
The final calculated value from the 1st frame to the Nth frame of each line (CH, -CH,) output from 4, that is, the CRC
This is the output of the sign. Here, eLl~e, 1 (β=1~
6) is a CRC code for channels CH, to CHffi.

[Effect of departure station]

As described above, the present invention enables high-speed processing and reduces the hardware scale, which has an excellent effect of improving economic efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a CRC code generation circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the CRC calculation circuit of the CRC code generation circuit of the present invention. FIG. 3 is a time chart explaining the operation of the CRC code generation circuit of the present invention. FIG. 4 is a block diagram of a conventional CRC code generation circuit. FIG. 5 is a circuit diagram of a CRC calculation circuit of a conventional CRC code generation circuit. FIG. 6 is a time chart explaining the operation of a conventional CRC code generation circuit. 11... CRC calculation circuit, 12... selection circuit, 13
．． 23.26...Flip-flop, 14...Shift register, 15...Control circuit, 21...CRC calculation circuit, 22...Serial-to-parallel conversion circuit, 24...Address count, 25 ...Memory for saving CRC calculation values,
Pl...Initialization pulse. Isen ♂ Re tie 4±〒-to iris 3 ■ Fugi example shoulder 1 Nichii Koma example CRCB circuit erase 2 mouth

Claims (1)

[Claims] 1. Input a multi-frame data string in which multiple lines of the same speed are multiplexed, and calculate the CRC calculation value of the previous bit and the CRC calculation value of the 1-bit previous in the first frame of the multi-frame. C based on the initialization pulse that initializes the value
a CRC calculation circuit that performs RC calculation; a flip-flop that temporarily stores the output of the CRC calculation circuit; and a shift register that stores the final value of the calculation of each line of the multi-frame among the outputs of the CRC calculation circuit. Select the contents of the shift register at the first bit of the calculation start of each line of each multi-frame, and select this first bit.
A CRC code generation circuit comprising: selection means for selecting the output of the flip-flop at a timing other than the bit-th timing and providing it as the CRC calculation value of the 1-bit previous bit.