JPH04245532A - Data rate converting circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a date rata converting circuit through the common use of an address counter by securing the relation between the writing and reading address values and actuating the address counter in response to a desired conversion rate. CONSTITUTION:An address generator 13 supplies the writing and reading addresses to a memory 11 and contains an address counter 14. When a rate is converted wit compression, the more significant M bits of a single output of (M+n) bits of the counter 14 are written as a writing address. Then the less significant M bits are read out at a high speed as a reading address. When the rate is converted with expansion, the output of less significant (M+n)-bit output of the counter 14 are written at a high speed as a writing address. At the same time, the more significant M bits are read out as a writing address and the more significant M bits are read out as a reading address. Thus a common counter 14 can be obtained. As a result, the constitution is simplified for a date rate converting circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data rate conversion circuit that performs time axis compression conversion and time axis expansion conversion when transmitting data at high speed.

0002

2. Description of the Related Art A method of converting the data rate by dividing digital data into m pieces and compressing the time axis has been considered. For example, a method of converting an input digital data string to a double rate will be explained with reference to FIG.

First, the digital data string before rate conversion is divided into units of m units (in the case of an even number), and each bit constituting this unit is sequentially written into memory from the beginning (Fig. 5(A)). After writing half of the m pieces of data into this memory, reading is started sequentially from the beginning of the memory at twice the rate. Continuing this operation, when the last data with m pieces as one unit, that is, the m-th data am, is written, this data is immediately read out and these m pieces are converted into one unit of digital data rate conversion (or compression) ends.

[0004] In this case, the second half of the digital data with m pieces as one unit, that is, (m/2)+1
Writing W and reading R occur at the same time in the portions starting from the number. As shown in FIG. 5C, digital data writing W in the latter half is performed at the third cycle from the beginning when one cycle on the low-speed rate side, that is, one period TW of the write cycle is divided into four. On the other hand, in the latter half of the digital data read R, one period TW of the data write cycle is 4
1st (or 2nd) and 4th time T of the divisions
I'm using R. If we control the memory in this way, m
It is possible to perform twice the rate conversion with half the memory capacity of the data.

By the way, when the reading R is started, as shown in FIG. ), and the read start address is (m/2)+1
The th data a(m/2)+1 is written within the next third period. Therefore, the data at the last address am
is 3 out of 4 parts of one period of the above write cycle.
Data am is written in the fourth and final period, and then data am at the last address is read out in the fourth and final period. In this way, digital data can double the data rate without data loss.

[0006]

[Problems to be Solved by the Invention] However, in this method, the address counter is divided into a conventional write cycle address counter used for writing in the compression conversion data rate circuit, and an address counter that operates at twice the write cycle used for reading. Two pieces are required for each. Further, the address counters in the decompression/conversion data rate circuit similarly require two independent address counters. In other words, when writing 2
Two address counters are required, one that operates at double times and the other that operates at conventional write cycles. Therefore, using two address counters is problematic in simplifying the circuit configuration of the data rate conversion circuit. In view of the above-mentioned circumstances, the present invention provides a data rate conversion circuit that can simplify the circuit by unifying address counters in address generators that are used independently for writing and reading. It is intended for the purpose of providing.

[0007]

[Means for Solving the Problems] A data rate conversion circuit according to the present invention writes m pieces of continuous digital data into a memory, and writes 2n pieces of continuous digital data from the memory at the above writing rate.
When reading at a double rate, the memory has an address generator that supplies a write address and a read address, and this address generator outputs an address of M+n bits, which is n bits more than the number of bits M of the address of the memory. , using a counter that increases by 1 in accordance with the clock for reading, the counter uses the upper M bits of the M+n-bit counter output as a write address and the lower M bits as a read address, m× (
When the writing of 1-1/2n) pieces of data is completed, data reading is started, and the write address and read address of the last data of the m pieces of data are M-bit address values with all bits "1". When m continuous digital data are written to the memory and read from the memory at a rate of 1/2n times the above write rate, the write address and read address are set to the above memory. The address generator outputs an address of M+n bits, which is n bits more than the number of bits M of the address of the memory, and uses a counter that increases by 1 in accordance with the write clock. , the counter is
The lower M bits of the above M+n bit counter output are used as the write address, and the upper M bits are used as the read address, and when the first data write is completed, data reading is started, and the above m data The above-mentioned problem is solved by setting the first data write address and read address to be an M-bit address value with all bits "0" and performing expansion conversion. Here, the number M of bits of the memory address when n is 1 is the smallest integer value M that satisfies m/2≦2M. Furthermore, M for any integer n may be the smallest integer that satisfies m×(1-1/2n)≦2M.

[0008]

[Operation] When the data rate conversion circuit according to the present invention compresses and converts the rate, the upper M bits of the counter output of one M+n bit address counter are written as a write address, and the lower M bits are used as a read address. When reading at high speed and converting by stretching the rate,
By writing the lower M bits of the counter output of the M+n bit address counter at high speed as a write address and reading out the upper M bits as a read address, the address counter can be shared.
Simplify the circuit configuration.

[0009]

[Example] Generally, when compressing the data rate by 2n times on the time axis using the data rate conversion circuit according to the present invention, data divided into m pieces of continuous digital data is written into memory, and Rate conversion is performed by reading data from memory at a rate 2n times higher. When the storage capacity of this memory is 2M pieces of data, M may be the smallest integer that satisfies m×(1-1/2n)≦2M.

[0010] An address generator that supplies write addresses and read addresses to this memory has an address counter built therein. This built-in address counter is a counter with M+n bits, which is n bits more than the number of bits M of the memory address, and is a counter that increases by 1 in accordance with the high-speed rate side clock, that is, the clock for reading. .

[0011] Reading from memory is m×(1-1/
Data reading is started when the writing of 2n ) pieces of data is completed, and the write address and read address of the last data of the above m pieces of data are set to the address value of M bits with all bits “1”. It is set.

The block diagram shown in FIG. 1 and the operating principle shown in FIG. I will explain while referring to it. Here, the above n
The number of bits M of the above memory address when is 1 is m
/2≦2M and is the smallest integer value M. Based on the above conditions, when continuously input digital data m=10, the number of bits M of the memory address is 3 bits.

The address generator 13 that supplies write addresses and read addresses to the memory 11 shown in FIG.
An address counter 14 is built into this. This built-in address counter 14 outputs a 4-bit address that is 1 bit more than the number of bits of the address in the memory (see FIG. 2(C)), and outputs a 4-bit address that is 1 bit more than the number of bits of the address in the memory (see FIG. This is a counter that increases by 1 in accordance with the clock for. This address counter 14 uses the upper 3 bits of the 4-bit counter output as a write address WA, and the lower 3 bits as a read address RA.

[0014] Here, the relationship between the rate or update period between the upper 3-bit address and the lower 3-bit address of the 4-bit count output will be explained. The update cycle of the upper three bits used as the write address is 1/2 of the count cycle of the four bits. Furthermore, since the update cycle of the lower three bits used as the read address is equal to the count cycle of the four bits, this read address is incremented at twice the rate of the write address.

This address counter 14 is set so that the last counter value is all "1". Figure 2 (A
), the address value of the last data a10 is "111" using the upper 3 bits of the address counter shown in FIG. 2(C), and all 3 bits are "1".
It shows. The read address shown in FIG. 2(B) is
When writing of the fifth data a5 is completed using the lower three bits of the address counter shown in FIG. 2(C), the data written to the memory is sequentially read out from a1 at twice the rate. . Therefore, both memory write and read addresses are represented by eight addresses ranging from 0 to 7 with a maximum value.

In order to ensure that the last write address value and the last read address value are all "1", the start address is found by searching backwards from the last address value of the 4-bit address counter 14. can be determined.

[0017] Therefore, this starting address can be found by the following arithmetic algorithm. That is, in this case, this address counter 14
Since we are counting 0 pieces at twice the rate, we need to count 20 pieces. However, this counter 14 is 16
Since this is a decimal count, the starting address to be found is "1100", which is obtained by subtracting this difference of 4 counts from "1111". When the start address is set in this way, Figure 2 (A
) can be made to match the start address of the read address in FIG. 2(B). Then, when the count of the address counter 14 is "1111", the last data a10 is read out at the time when writing is completed.

The upper side 3 of the starting address "1100" of this counter output obtained by the above-mentioned algorithm
Bit “110” becomes the write address. The first address “01” in the second half of this address counter 14
If the lower 3 bits of "10" are taken out and used as a read address, this read address has a matching relationship with the above write address "110". The coincidence of this write address and read address, and the above write and read When counting is incremented by 1 at each rate, the write address and read address of the last of the 10 data will be a 3-bit address value with all bits "1".In this way, write and read By establishing a relationship between each address value and making the address counter operate according to the desired conversion rate, the write address counter supplied from the address generator 13 and the read address counter are unified into one, simplifying the circuit configuration. can be converted into

FIG. 3 shows an example of a more specific circuit configuration.
This will be explained with reference to. FIG. 3 shows a specific example in which serial data supplied via the input terminal 20 is converted into parallel data to perform rate conversion. Control of writing and reading for this rate conversion is performed by an address generator 28 that supplies write addresses and read addresses to the static RAM 24. The shift register 22 converts the recording signal inputted via the input terminal 20 into 8-bit parallel data using the clock CLK1 inputted via the input terminal 21, and stores the data in the static RAM 2 via the enable buffer 23.
I am writing in 4.

In this case, the write address counter supplied to the static RAM 24 converts the recording signal input as serial data into 8-bit parallel data, so that the write address counter is input to the shift register 22 via the input terminal 21. Clock CLK, which is the standard for 1x speed
The address count is increased by 1 at a frequency of 1/8 of 1. Similarly, the read address counter also clocks C.
The address count is increased by 1 at a frequency of 1/8 of LK1. In this way, when writing to memory, the data supplied to the memory is converted from serial to parallel, and when reading from memory, the read data is converted from parallel to serial, so that the address count is shifted from serial to parallel. 1/( of the clock input to the register)
(parallel output bit count) times the frequency.

Further, a clock CLK0 having twice the frequency of the clock CLK1 is sent to a shift register 26 and an address generator 28 via an input terminal 25. The shift register 26 takes in the load signal supplied from the address generator 28 at the "L" level, and performs parallel-to-serial conversion at the clock 0. Therefore, the data rate is converted to the ratio of clock 0 supplied to shift register 25 to clock 1 supplied to shift register 22, that is, doubled. This serial data is sent to the enable buffer 29, which outputs a recording compression signal through the output terminal 30 when the level of the enable signal supplied by the address converter 28 is "L".

Note that the write address and read address of the last data of the m pieces of data are set to all bits “1”.
With the above configuration in which the address value is set to be an M-bit address value of ``, it is possible to convert the data rate of m pieces of continuous digital data to double the data rate.

Next, the operating principle of rate conversion is to write continuous digital data divided into m pieces into memory and read it from this memory at a rate of 1/2n times (that is, to extend the time axis by 2n times). I will explain about it. Generally, an address generator that supplies write and read addresses to the memory includes an address count. This address counter is a counter that increases by one in response to the high-speed clock, that is, the write clock. This address counter uses the lower M bits of the M+n bit counter output as a write address and the upper M bits as a read address. Furthermore, M for any integer n may be the smallest integer that satisfies m×(1-1/2n)≦2M.

As a specific example, M for continuous digital data m=10 and n=1 satisfies 23=8, and the minimum integer is M=3 bits. The principle of operation of time axis expansion for increasing the data rate by 1/2 will be explained with reference to FIG. 4. The address counter provided in the address generator has 4 bits, which is 1 bit more than the number of bits M=3 of the memory address (see FIG. 4C). This address counter has
It is incremented by 1 according to the writing clock, and furthermore, the initial counter value of this counter is all “
0'' (see FIG. 4(C)).

In writing, the first write address of 10 consecutive pieces of data is determined by using the lower three bits of the address counter so that the address value of the first data a1 is "000" and all three bits are "0". (See Figure 4(A)).

In reading, the first read address of 10 consecutive pieces of data is determined by using the lower 3 bits of the address counter and setting the address value of the first data a1 to ``000'' so that all 3 bits become ``0''. (See Figure 4(B)). This is because the start address of the address counter is operated with all 4 bits being "0", so there is no need to calculate the start address of the address counter that was performed when compressing the data rate described above. This reading is started by the upper 3-bit counter of the address counter at the time when this first writing is completed (see FIG. 4(B)).

The relationship between the rate or update period between the lower 3-bit address and the upper 3-bit address of the 4-bit counter output will now be explained. Since the update cycle of the lower 3 bits used as the write address is equal to the count cycle of the 4 bits, this write address is twice as long as the read address.
is being incremented at twice the rate. Further, the update cycle of the upper three bits used as the read address is 1/2 of the count cycle of the four bits.

By establishing a relationship between write and read address values in this manner and operating the address counter according to the desired conversion rate, one write address counter and one read address counter are supplied from the address generator. The circuit configuration can be simplified by making them common. At this time, if the memory operation according to the memory write cycle and the memory read cycle cannot be done in time, it is possible to use two memories and access them alternately to make up for the missed time and convert the rate. There is.

In this way, by making the address counter operate according to the coincidence of each address value and the desired conversion rate, the write address counter supplied from the address generator and the read address counter are unified into one circuit. The configuration can be simplified.

By operating as described above, the address counter used in the data rate conversion circuit conventionally required two independent counters for writing and reading, but now both of the above counters can be made common. Thus, the circuit configuration can be simplified.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can also be applied to data rate conversion of 2n (or 1/2n) times other than 2 (or 1/2) times the data rate. can. In this case, if continuous data is divided into m pieces, M for any integer n satisfies m×(1-1/2n)≦2M and is the smallest integer. The memory capacity at this time is 2M words, which is (1-1/2n) times the number of m pieces of data that divide the input continuous data.

The address counter in the address generator is
When converting the rate to 2n times, the memory address M
Set n bits more than bits, take M bits from the upper side of the write address, and discard the lower n bits. Furthermore, the read address can be obtained by taking M bits from the lower order side and discarding the upper n bits.

Furthermore, when converting the rate to 1/2n times, n bits are set more than the M bits of the memory address, and the write address takes M bits from the lower side and discards the upper n bits. Further, the read address may be obtained by taking M bits from the upper side and discarding the n bits from the lower side.

[0034]

Effects of the Invention As is clear from the above description, according to the data rate conversion circuit of the present invention, when m pieces of continuous digital data are written to the memory and read at a rate 2n times the write rate, the address An address counter that increases by 1 in accordance with the read clock in the generator outputs an address of M+n bits, which is n bits more than the number of bits M of the address in the memory, and
The upper M bits of the bit counter output are used as the write address, the lower M bits are used as the read address, and m
When the writing of ×(1-1/2n) pieces of data is completed, data reading is started, and the write address and read address of the last data of the above m pieces of data are set to M bits with all bits “1”. By setting the address value to be the same as the address value, the address counters in the address generator, which used to be two independently used for writing and reading, can be unified into one, thereby simplifying the circuit.

When reading at a rate 1/2n times the write rate, a counter of M+n bits, which increases by 1 in accordance with the write clock in the address generator, is used to set the lower M bits to the write address. bit as a read address, start reading data when writing of the first data is completed, and set the write address and read address of the first data of the m pieces of data as the address of M bits with all bits “0”. By setting this value, the write and read address counters can be shared and the circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram for rate compression conversion showing an embodiment of a data rate conversion circuit according to the present invention.

[Figure 2
] Schematic diagram explaining the operating principle of a rate compression circuit

[Figure 3] Data rate conversion circuit diagram for rate compression

[Figure 4] Schematic diagram explaining the operating principle of the rate stretching circuit

[Figure 5] Schematic diagram showing conventional data rate conversion

[Explanation of symbols]

11・・・・・・・・・Memory

Claims (2)

[Claims] 1. A data rate conversion circuit for writing m pieces of continuous digital data into a memory and reading it from the memory at a rate 2n times the writing rate, wherein the address generation circuit supplies a write address and a read address to the memory. The address generator has an address generator with n bits more than the number of bits M of the memory address M+
A counter is used that outputs an n-bit address and increments by 1 in accordance with the reading clock, and the upper M bits of the M+n bit counter output are used as the write address, and the lower M bits are used as the write address. Used as a read address, data reading is started when writing of m×(1-1/2n) pieces of data is completed, and the write address and read address of the last data of the m pieces of data are all bits. 1. A data rate conversion circuit characterized in that the data rate conversion circuit is set to have an M-bit address value of 1''. [Claim 2] Writing m pieces of continuous digital data into a memory, and writing m pieces of continuous digital data from the memory at 1/2n of the above writing rate.
A data rate conversion circuit that reads data at a double rate, and has an address generator that supplies a write address and a read address to the memory, and this address generator generates a data rate of M+n which is n bits larger than the number of bits M of the address of the memory. Using a counter that outputs a bit address and increments by 1 in accordance with the write clock, the counter uses the lower M bits of the M+n bit counter output as the write address and reads the upper M bits. It is used as an address, and data reading is started when the writing of the first data is completed, and the write address and read address of the first data of the m pieces of data are M-bit address values with all bits “0”. A data rate conversion circuit characterized in that the data rate conversion circuit is configured to