JPH01255332A - Frame converting circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution, to facilitate a control, and to execute the low energy consumption of a circuit by composing the circuit constitution of a basic frame unit and executing the control in the basic frame unit. CONSTITUTION:A code rearranging circuit 10 to temporarily convert an input multiframe A or N-bit/M-frame to an intermediate multiframe A' to have the number of basic frames equal to the number N of bits of a basic frame is composed of a serial/parallel converter 1 to execute conversion in a bit number unit of the basic frame, a shift latch memory 2, a latch parallel/serial converter 3, a signal selecting circuit 4, and a counter 5 for an input. Consequently, the intermediate multiframe A' is written into an elastic store 20 by a timing signal (b) in the basic frame unit of the counter 5 for the input, and it is read by a timing signal B in the basic frame unit of the output of a counter 6 for an output. Thus, the circuit constitution can be simplified, the control can be facilitated, and the energy consumption can be reduced.

Description

[Detailed Description of the Invention] [Summary] A basic method in which the input multi-frame^ is synchronized with an output clock CKB which is asynchronous with the input clock CK^ and in which the basic frame number i and the basic frame bit number N are mutually exchanged. Regarding the frame conversion circuit that converts the number of frames N to the output multi-frame B with the basic frame no-hit number M, the input a serial/parallel converter that converts a serial code for one multiframe into a parallel code with N bits of a basic frame;
A shift function that individually shifts the output to the input multi-frame by the number of basic frames H, converts it into parallel, and latches it.
A latch/parallel/serial that launches the latch memory and its parallel output, converts it into a serial code with a number of bits equal to the number of basic frames of multi-frame A, and outputs the converted signal in parallel in a number equal to the number of bits N of the basic frame. A converter, a signal selection circuit that sequentially selects the parallel outputs of the converter and outputs an intermediate multi-frame A' with a basic frame number N, and a clock C.
K A is the number of bits of the basic frame N to multiframe
A first timing signal al that is reset and outputs one pulse every time one multi-frame is counted; a second timing signal a2 that outputs a basic frame number H pulse every time one multi-frame is counted; The third pulse outputs the number of bits N of the basic frame every time the number of bits is counted.
A code rearrangement circuit is configured with an input counter that generates a timing signal A, and the first timing a of the input counter is
l controls the serial/parallel converter, second timing a2 controls the shift/latch memory, and third timing b controls the latch/parallel converter and signal selection circuit, converting the input multi-frame A into its basic frame. An intermediate multiframe A' having a basic frame number N equal to the bit number N of
Read out each basic frame using the output clock CK B, which is asynchronous with A, to obtain an output multi-frame B in which the number of bits of the basic frame is equal to the number H of input basic frames and the number of basic frames is equal to the number N of bits of the input basic frame. Configure to output.

[Industrial application field]

The present invention relates to converting the frame structure of a multi-frame when multiplexing, separating, etc. data in data transmission, and particularly relates to an input multi-frame consisting of eight basic frames of N bits synchronized with an input clock CKA. A, the number of basic frames and the number of bits N of the basic frame are exchanged with each other through an elastic store, and the input clock CK is an output clock CK asynchronous to A.
By B, the number of basic frames N is the number of bits of the basic frame H
The present invention relates to a frame conversion circuit that converts the output multi-frame B into an output multi-frame B.

[Conventional technology]

An example of the configuration of a conventional frame conversion circuit for the above application is shown in FIG. In this conventional example, the input multi-frame A is a 3-bit/8-frame multi-frame system in which the number of basic frames synchronized with the input clock CKA consists of 8 frames, and the number of bits N of the basic frames is 3 bits. Frame tomorrow, output multiframe B is input clock CK
Controlled by output clock CX B asynchronous to A,
The basic frame ¥1. Fj and the number of bits N of the basic frame are exchanged with the input multiframe A, the number of basic frames is 3, and the number of bits of the basic frame is 8, which is 8 bits/3.
It is a frame.

This conventional example is shown in the operation time chart of Fig. 3.
The input clock CK is input to the RAM memory 108 for code conversion shown in the block diagram of the figure, and the input clock CK is input to the write control circuit 51A.
1 pulse is generated by 3 pulses of A ■Timing B1 and 1
The RAM memory LOA is generated by the write pulse Wp at timing a2, which generates 8 pulses with 24 pulses for multi-frames.
Control circuit 5 that controls the O write address and is written continuously.
24 for one multiframe to input clock CK at 2A
■The read pulse Rρ at timing b controls successive addresses RA to generate 3 pulses in the RAM memory I.
OA, and at the output of the RAM memory IOA, the first
frame and the second frame are 9 clocks for 3 basic frames, and the third frame is 8 bits/3 synchronized with the input clock CKA, which is 6 clocks for 2 basic frames.
Sorted by frame. Then, this rearranged intermediate multi-frame A' is inputted from the RAM memory 108 to the pit buffer 20 of the elastic store, which inputs the read pulse Rρ generated by the successive control circuit 528. The multi-frame A' data written in the elastic memory 20 by controlling the write address of the bit buffer 20 of the elastic memory 20 as a pulse is input to the input clock CK A by another successive control circuit 6A. The frequency is the same as that, but the phase is generally different ■ Output clock CK B generated by ■ Timing B controls successive addresses R to generate three basic frames of one multi-frame, each with 8 clocks, equally spaced 11 fi ■ Output multi-frame B 8 bits/3
Outputting frames.

Then, the data of the input multi-frame 8 and the output multi-frame B are continuously code-converted in the RAM memory 104 and the pit buffer 20 of the elastane ink memory, and the input multi-frame 8 is interrupted. Even in this case, if the clock CK B is alive, the output ■
Multiframe B is continuously transmitted to the outside without momentary interruption.

[Problem to be solved by the invention]

The conventional frame conversion circuit shown in FIG. 4 operates as described above, and consists of a RAM memory IOA, a write control circuit 518, and a successive output control circuit 52A.
The code reordering circuit 100 in the first half that rearranges the codes into the intermediate multiframe A' has one of its components, RA.
When the input transmission data becomes high speed and large capacity, the capacity of the M memory 108 increases, and when the capacity of the RAM memory IOA increases, write pulses Wf++ and read pulses Rp are created to control the addresses WA and RA for writing/reading. The circuit scale of the write control circuit 51A and the read control n circuit 52A becomes large and complicated.

As the circuit scale of the RAM memory IOA, write control circuit 51A, and successive control circuit 52A becomes larger and more complex, power consumption also increases, and the code reordering circuit 100 that rearranges codes from multiframe A to multiframe 8' becomes larger. There is a problem that the frame conversion circuit device becomes a doll due to the complexity and power consumption.

[Means to solve the problem]

The problem of increasing the size of this frame conversion circuit is that it converts the serial signal to the input multiframe into the intermediate multiframe A.
This problem is solved by the structure of the code reordering circuit 10 that converts the intermediate multiframe 8' into the output multiframe B, and the structure of the present invention in which the conversion from the intermediate multiframe 8' to the output multiframe B is not a bit-by-bit conversion but a basic frame-by-frame conversion. .

In the principle diagram of FIG. 1 showing the configuration of the frame conversion circuit of the present invention, l is N bits 1M in which one multiframe is made up of a certain number H of basic frames made up of a certain number N of bits.
This is a serial/parallel converter that inputs a serial code for one multiframe of frames and converts it into parallel codes of a number N equal to the number N of bits of a basic frame using a timing signal a1 described later.

Reference numeral 2 denotes a shift/latch memory that individually shifts the output of the serial/parallel converter 1 by a number of stages H equal to the basic frame number H of the multi-frame A, converts it into parallel, and latches it.

3 latches the parallel output of the shift/latch memory 2 using a timing signal, converts it into a serial code with a number of bits H equal to the number of basic frames to be input to the input multi-frame, and converts the converted serial signal into a serial code of the input multi-frame. Multi frame A
This is a latch/parallel-to-serial converter that outputs in parallel a number N equal to the number N of bits of the basic frame.

4 sequentially selects the parallel outputs of the latch/parallel/serial converter 3 according to the timing signal, and selects an intermediate multiframe A' in which the number of basic frames of one multiframe is equal to the number of bits N of the input multiframe A. This is a signal selection circuit for output.

5 is a first timing signal al that is reset every time the input clock CKA is counted by the number N of bits of the basic frame of the input multiframe, and outputs l pulse by decoding the counted value, and a second timing signal a2 that outputs pulses of the basic frame number H while counting, and a third timing signal that outputs a number of pulses equal to the number of bits N of the basic frame every time one input multi-frame is counted. This is an input counter that generates a

Then, the serial/parallel converter 1 is controlled by the first timing signal al of the input counter 5, and the second timing signal a
2, the shift/latch memory 2 is controlled by a third timing signal, and the latch/parallel/serial converter 3 and the signal selection circuit 4 are controlled by a third timing signal.
Configure to control.

10 is a serial/parallel converter 1. Shift latch memory 2
．． Latch/parallel/serial converter 3. Signal selection circuit 4. Consists of an input clock frame counter 5, and an input clock CK
An input multi-frame A with a basic frame number H and a basic frame bit number N synchronized with A is also input with an input clock C.
This is a code rearrangement circuit that synchronizes with KA and converts it into an intermediate multiframe A' having the number of basic frames equal to the number of bits N of the input basic frame.

Then, the data of the intermediate multiframe A' output from the code rearrangement circuit 10 is written into the elastic store 20 by the third timing signal of the input counter 5.

6 generates a timing B that outputs a number of pulses of equal length equal to the number of bits N of the input basic frame every time the output clock CK B, which has a different phase from the input clock CK A, is counted for one multiframe. This is an output counter.

20 writes the data of the intermediate multi-frame A' output from the signal selection circuit 4 of the rearrangement circuit IO by controlling the write address by the third timing pulse b of the input counter 5; The successive address R is controlled and read according to the output timing B, and the number of bits of the basic frame is equal to the number of basic frames to the input multi-frame, and the number of basic frames is equal to the number of bits N of the input basic frame. (This is an elastic store that outputs output multiframe B asynchronously with J8 to the outside.

[Effect]

The serial/parallel converter 1 inputs the input multi-frame 8 of the basic frame fiM, one multi-frame at a time, with the number of bits N of the basic frame synchronized with the input clock CKA,
duLy 50 every time the input counter 5 counts the number N of clocks CK A equal to the number of bits N of the basic frame.
The first timing signal a1 that generates and outputs one pulse of % converts the input serial data into N columns of parallel data and outputs the converted data to the shift/latch memory 2.

The shift/latch memory 2 individually converts the N parallel data output from the serial/parallel converter 1 into four pulses while the input counter 5 counts MN clocks CKA for one multiframe. Using the second timing signal a2 to be output, the parallel data of the shift l-L and M columns is once latched in the H stage and output to the latch/parallel-to-serial converter 3 in the next stage.

The latch/parallel/serial converter 3 individually converts one row of parallel data output from the shift/latch memory 2 into an input counter 5.
While counting MN clocks CKA for multi-frames, the third timing signal generates and outputs a number N of duty 50% pulses equal to the input basic frame bit number N, and re-latches. and parallel/
A serial conversion is performed, and serial codes whose number of bits is an integral multiple of the basic frame of the input multi-frame are output in parallel to the signal selection circuit 4 by a number N equal to the number N of bits.

The signal selection circuit 4 selects the serial codes of the parallel number N of the outputs of the latch/parallel-to-serial converter 3 by using the third timing signal.
Sequentially select basic frames IiN equal to the number of bits N of the basic frames of the input multiframe A, and intermediate multiframes whose number of bits of the basic frame is a serial code of an integer multiple of the number of basic frames to the input multiframe. A frame A' is formed and its data is output to the Extix 1-A 20.

The elastic store 20 writes the data of the intermediate multiframe A' output from the signal selection circuit 4 using a third timing signal synchronized with the clock CKA output from the input counter 5, and writes the data asynchronously with the clock CKA. Every time the output counter 6 counts 1 for one multiframe, the output clock CK [1] generates and outputs a number N of pulses with the same clock length equal to the number N of bits of the basic frame to the input multiframe. Read at timing B. And the output clock (H bit/N which is synchronized with J B but asynchronous with input clock CK A)
Multi-frame B of frames is output to the outside.

The frame conversion circuit of the present invention once converts an input multiframe A of N bits and 7M frames synchronized with the input clock CK^ into an intermediate multiframe A' having the number of basic frames equal to the number of bits N of the basic frame. The code reordering circuit 10 requires complicated addresses for bit-by-bit conversion and consumes a lot of power. A serial/parallel converter 1, a shift/latch memory 2, a latch/parallel/serial converter 3, and a signal selection circuit 4 that convert in units of the number of bits of a basic frame without using an AM memory or its writing/reading control circuit. and frame counter 5, the code rearrangement circuit 10 has a simple circuit configuration, is easy to control, consumes less power, and solves the problems of the prior art. Then, the intermediate multi-frame 8' rearranged by the code rearranging circuit 10 of the present invention is written to the elastic store 20 by the third timing signal of the basic frame unit of the input counter 5, and is written to the output counter 6. Since it is read at timing H in basic frame units of the output of
The configuration of one successive control circuit is also simplified and power consumption is reduced, so there is no problem.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a frame conversion circuit according to an embodiment of the present invention, and FIG. 3 is a time chart for explaining its operation.

The embodiment of the block diagram in FIG. 2 is based on the time chart in FIG.
The bit RN of the basic frame is 3 bits/8 frames with 'l<3, and the output multiframe B is
This is an example of an 8-bit/3 frame in which the number H of basic frames and the number N of bits of the basic frame are exchanged.

The code reordering circuit 10 of the embodiment shown in FIG. 2 includes serial/parallel converters 1. Shift/latch memory 2. Rudge/parallel/serial converter No. 3, 13 selection circuit 4. It is composed of an input counter 5. The serial/parallel converter I is a three-stage shift register 1.
The 3-stage shift register 11 is composed of 1 and 3 columns of latches 12, and a 3-bit basic frame C1i, C2i+C3i, i=1 to 8 synchronized with the input clock CKA.
(7) One multi-frame for one 87J wooden frame
The input multi-frame A generated by rR is input for 1 frame -]-7 frames at a time, and each time the counter 51 of the input counter 5 counts three clocks CK A for one basic frame of the input clock CK A. Although not shown, the duty
At the first timing al when one 50% pulse is output from the decoder 512, three columns of parallel outputs are outputted and input to the latch 12, and three columns of parallel signals are outputted from the latch 12 to the shift/latch memory 2.

The shift/latch memory 2 consists of a cascade circuit in which each set has eight stages of shift registers 211 and eight columns of latches 212 (
For example, the shift register 2 of the 1st Mi elementary path 21
11 is the output 3 of the launch circuit 12 of the serial/parallel converter 1
The frame counter 51 outputs 8 pulses every time the frame counter 51 measures the clock CK of 1 multi-frame for the output of the first column of the column. ■By the second timing B2, each column is shifted to 8 stages to form 8 columns in parallel. The output is output to the latch/parallel/serial converter 3 via the launch 212. Shift latch memory 2
The second and third sets of preset paths 22 and 23 have similar configurations, and the second timing a when the frame counter 51 occurs.
2, the signals are converted into eight columns of parallel outputs and output to the latch/parallel/serial converter 3 via eight stages of latches 222 and 232.

The latch/parallel/serial converter 3 has three sets of elementary paths 3L32°33
The latches 311 and 8 are composed of 8 rows of latches 311 and 8.
It consists of a stage shift register 312 (second and subsequent sets are omitted). The latches 311, 321.331 once latch the outputs of the latches 212.222.232 of the shift latch memory 2, respectively, and shift registers 312.322.3
32 is 2 of the frame counter 51 is 1 multiframe
3 cluty while measuring 4 clocks CK
50% pulse is output in 3-bit basic frame units in synchronization with timing B2. By timing b,
The first and second sets output serial signals of 9-bit configuration, and the third set outputs serial signals of 6-bit configuration, and the three columns of serial signals are input to the signal selection circuit 4.

The signal selection circuit 4 is composed of a selector 41, and the selector 4
1 sequentially selects three columns of serial codes output from the latch/parallel-to-serial converter 3, and the first frame of
19, the data of the intermediate multi-frame A', in which the second frame consists of 9 bits C21 to C29 and the third frame consists of 6 bits C31 to C36, is output and input to the elastic store 20.

The elastic store 20 controls the sending address A according to the third timing b generated by the input counter 5 using the input clock CKA, corrupts the data of the intermediate multiframe A', and reads the data. , d while counting 824 multi-frame clocks CK generated by the output counter 6 using the output clock CK B, which has the same frequency as the input clock CK A but is asynchronous.
Uty 3 pulses of 50% are output with the same clock length of 8 clocks ■The successive address R is controlled and read by timing B, and as shown in ■Output multi-frame B, the first frame is CI1 to C18. , the second frame is C21 to C28, and the third frame is C31 to C38, each of which is an 8-bit/3 frame output multi-frame B consisting of 8-bit basic frames.

As described above, the frame conversion circuit of the embodiment of the present invention shown in FIG.
Serial/parallel converter 1. Conversion from input multiframe 8 to intermediate multiframe A' operates in units of 3 bits of input basic frame. Shift/latch memory 2. Latch/parallel/serial converter 3. Signal selection circuit 4. The code rearrangement circuit 10 composed of the input counter 5 converts the input multiframe 1, ^ of 3 bits/8 frames synchronized with the input clock CKA to the basic frame number 3 and the basic frame number. The number of bits is 9 bits for the first frame, and 9 bits for the second frame.
In the intermediate multiframe A' where one frame is 9 bits and the third frame is 6 bits,
It is converted in units of 3-bit basic frames and written to the output elastic store 20.

Data reading from the elastic store 20 is also performed using the output clock CK output from the output frame counter 6.
Since this is performed at timing B in units of 8-bit basic frames of B, all circuit configurations of the frame conversion circuit are simple, control is easy, and power consumption is low, causing no problems.

In addition, in the frame conversion circuit of this embodiment shown in FIG. 2, data writing to the elastic store 20 of intermediate multiframe A' is performed using the input clock (timing b generated by J8), and data reading is performed using the output clock. clock C
Since the configuration is such that reading is performed at timing R created by KB, even if the input clock CKA disappears or the data to the input multi-frame is cut off, as long as the output clock CKB is present, the output will continue. There is no problem because the output multi-frame B can be constructed and output by the counter 6.

〔Effect of the invention〕

As explained above, according to the present invention, the circuit configuration of a multi-frame frame conversion circuit is simplified by configuring it in units of basic frames, and since side doors are installed in units of basic frames, control becomes easy and power consumption can be reduced. Even if the number of bits that make up a frame of multi-frame data increases, it can be easily expanded by simply connecting the same circuit, which has the effect of standardizing the frame conversion circuit and making it easier to integrate it into LSI. It will be done.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the configuration of a frame conversion circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of a frame conversion circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a frame conversion circuit according to an embodiment of the present invention and a conventional example. A time chart for explaining the operation. FIG. 4 is a block diagram of a conventional frame conversion circuit. In the figure, 1 is a serial/parallel converter, 11 is a shift register, I2 is a launch, and 2 is a shift register.
Latch memory, 211. 221, 231 are shift registers, 212, 2
22.232 is a latch, 3 is a latch/parallel/serial converter, 311.32L331 is a latch, 312, 322.332 is a parallel/serial converter, IO is,
The code reordering circuit 20 is an elastic store.

Claims (1)

[Claims] Serial data of an input multiframe A, in which one multiframe is composed of a constant number M of basic frames with a constant number N of bits, is converted into intermediate multiframes with a basic frame number equal to the bit number N of the basic frame. (A') and write it to the elastic store (20) and read it using the output clock CKB which has a different phase from the input clock CKA.
In a frame conversion circuit that converts an input multi-frame A into an output multi-frame B having a number of bits equal to the number M of basic frames of an input multi-frame A and a number of basic frames equal to the number N of bits of the basic frame asynchronously with an input clock CKA, the input multi-frame A is A serial/parallel converter (1) that converts one multi-frame worth of serial data into parallel codes of a number equal to the number of bits N of the basic frame using a timing signal (a1), and an output of the serial/parallel converter. A shift/latch memory (2) that individually shifts and latches a number of stages equal to the basic frame number M of input multi-frame A using a timing signal (a2) and outputs the same in parallel, and a timing signal that outputs the parallel output of the shift/latch memory. (b), and the basic frame number M of input multiframe A.
A latch/parallel/serial converter (3) that converts into a serial code with a number of bits M equal to , and outputs the converted serial code in parallel in a number equal to the number of bits N of the basic frame, and an output of the latch/parallel/serial converter. a signal selection circuit (4) which selects an intermediate multi-frame (A') using the timing signal (b) and outputs an intermediate multi-frame (A') in which the number of basic frames is equal to the number of bits N of the input basic frame; A first timing signal (a1
), a second timing signal (a2) that outputs a number of pulses equal to the number M of basic frames every time one multi-frame of input is counted, and a third timing signal (a2) that outputs a number of pulses equal to the number N of bits of the basic frame. an input counter (5) that generates a timing signal (b); and an input counter (5)
Generates timing (B) to output pulses of equal length equal to the number of bits N of the input basic frame every time one multi-frame of the output clock CKB, which has the same frequency and different phase as the input clock CKA, is counted. an output counter (6) that outputs a first timing signal (
a1) controls the serial/parallel converter (1), and a second timing signal (a2) controls the shift/latch memory (2).
The latch/parallel/serial converter (3) and signal selection circuit (4) are controlled by the third timing signal (b), and the data of the input multi-frame A is changed to the bit number N of the basic frame. is converted in basic frame units into intermediate multi-frames having the number of basic frames N equal to , and written to the elastic store (20), and according to the basic frame unit timing (B) of the output of the output counter (6) according to the output clock CKB. A frame read from the elastic store (20) and converted into an output multiframe B having a number of bits equal to the number M of basic frames of the input multiframe A and a number of basic frames equal to the number N of bits of the basic frame. conversion circuit.