JPH02119188A - Superconducting transistor and its manufacture - Google Patents

Abstract

PURPOSE:To realize integration by separating superconducting source and drain electrodes from each other with a thin film channel. CONSTITUTION:Superconducting material of which source and drain electrodes 2 and 3 are made is in a superconducting state in an operating environment under a temperature below the critical temperature of the material. A superconducting wave function is emitted from impurity diffused layers 5 and 5' of respective electrodes which, are brought into contact with the electrodes 2 and 3 and provided with a required interval. At that time, an electric field is applied by a gate electrode 6 through a gate insulating film 7 to a channel 4 which is brought into contact with the electrodes 2 and 3 and provided between the electrodes 2 and 3 and composed of an Si thin film protruding continuously from an Si substrate 1 surface to control the emission of the wave function, so that a superconducting current applied to the channel 4 can be controlled by the electrode 6. With this constitution, as the source and drain electrodes can be provided on the substrate, integration can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a superconducting transistor that utilizes superconducting phenomena and a method for manufacturing the same, and particularly to a superconducting transistor suitable for integration and a method for manufacturing the same.

[Conventional technology]

Conventional superconducting transistors are described in Physical Review, Volume 33 (February 1986) No. 2042-204.
Page 5 (Physical Review, volume
e 33°February (1986) pp20
42-2045).

In the structure of the superconducting transistor described herein, source and drain electrodes made of a superconducting material are provided on the surface of a silicon (Si) substrate at a predetermined interval, and
The portion of the Si substrate between the source and drain electrodes is made into a thin film, and Si
A gate electrode made of Afl is provided via an O2 film.

[Problems to be Solved by the Invention] The conventional superconducting transistor described in the above document has a structure in which a gate electrode is provided on the back surface of the Si substrate opposite to the surface of the Si substrate on which the source/drain electrodes are formed. Therefore, there was a problem that □ integration was not possible.

An object of the present invention is to provide a superconducting transistor that can be integrated by having a source electrode, a drain electrode, and a gate electrode on one surface of a substrate, and a method for manufacturing the same.

[Means to solve the problem]

The superconducting transistor of the present invention includes a substrate, a pair of source/drain electrodes made of a superconducting material provided on the substrate at a predetermined minute interval, and in contact with the source/drain electrodes and between the two. The semiconductor device includes a channel and a gate electrode provided on the channel with a thin insulating film interposed therebetween.

The channel is preferably formed of a thin film portion that is integral with the semiconductor substrate and protrudes in a direction perpendicular to the surface of the substrate.

The method for manufacturing a superconducting transistor of the present invention includes a step of forming a first mask pattern on a semiconductor substrate, a step of depositing a second mask film on the entire surface of the substrate, and a step of depositing a second mask film on the entire surface of the substrate. a step of injecting etching gas to perform anisotropic dry etching of the second mask film, leaving the second mask film only on the sidewalls of the first mask pattern to form a second mask pattern; , using the second mask pattern as a mask, injecting an etching gas substantially perpendicularly to the surface of the substrate to perform anisotropic dry etching of the substrate to form a channel portion.

[Effect]

In the superconducting transistor of the present invention, the superconducting source and drain electrodes are separated by a thin film channel.
A gate electrode can be placed above the channel. Therefore, source, drain.

A gate electrode can be formed on the top surface of the substrate.

Further, in the method for manufacturing a superconducting transistor of the present invention, it is possible to form a superconducting transistor having the above-described structure and having a minute channel length, which is difficult to achieve by using photolithography. In addition, in the superconducting transistor manufactured by this method.

Highly doped impurity regions can be provided near the surface of the channel, in contact with each of the source and drain electrodes, and spaced apart from each other by a predetermined distance.

〔Example〕

Embodiment 1 FIG. 1(a) is a plan view of a superconducting transistor according to a first embodiment of the present invention, and FIG. 1(b) is a plan view of A- in FIG. 1(a).
It is an A sectional view.

1 is a Si substrate, 2.3 is a source electrode and a drain electrode formed of a superconducting material, and 4 is in contact with the source/drain electrode 2.3, exists between the two, and is integral with the Si substrate 1. a channel consisting of a protruding Si thin belly; 5;
5' is an impurity diffusion layer of each electrode, which is in contact with the source/drain electrode 2.3 and is formed at a predetermined interval;
is a gate electrode, 7 is a gate insulating film, 8 is an interlayer insulating film, 9
10 is a source lead wiring, and 10 is a drain lead wiring.

In an operating environment below the critical temperature of the superconducting material constituting the source/drain electrodes 2.3, the materials of the source/drain electrodes 2, 3 are in a superconducting state, and the superconducting wave function is saturated from the impurity diffusion layer 5.5'. put out. At this time, by applying an electric field to the channel 4 through the gate insulating film 7 using the gate electrode 6, the leakage of this wave function can be changed.
The superconducting current that flows through can be controlled.

FIGS. 2(a) to 2(g) are process cross-sectional views showing a method for manufacturing the superconducting transistor shown in FIG. 1.

First, a Si substrate with a thickness of about 10 to 20 nm is placed on the Si substrate 21.
After forming a Si oxide film (SiO2 film) (not shown) for protecting the substrate, a Si nitride film 22 with a thickness of approximately 0.5 to 1 μm is deposited by vapor phase epitaxy, and then photoetching is performed. These 2M were patterned using the same method, and the entire surface was further patterned with a thickness of 0.
A Si oxide film 23 of about 1 to 0.2 μm is deposited by vapor phase growth (FIG. 2(a)).

Next, by injecting etching gas perpendicularly to the surface of the substrate 81, the Si oxide film 23 is anisotropically etched in the perpendicular direction by RIE (reactive ion etching). As a result, the patterned Si
A spacer 24 of Si oxide with a width of about 0.2 μm is formed on the side wall of the nitride film 22 (FIG. 2(b)).
).

Due to the width F of this Si oxide film spacer 24, Si
The width of the channel portion formed on the surface of the substrate 21 is determined. A good superconducting transistor channel can be realized by setting the width r to about 0.2 μm, preferably 0.1 μm or less.

The Si nitride film 22 is removed by etching, and using the Si oxide film spacer 24 as a mask, for example, 20 to 4
Ion implantation is performed at a low energy of about 0 keV, and shallow impurity diffusion with an impurity concentration of 10" to 10"(!11-") is performed [2
5 (Fig. 2(C)).

Spacer 2 made of Si oxide instead of photoresist
4 is used as a mask for ion implantation, the substrate is annealed in an inert gas, the doped impurities are activated, and an impurity profile with a low impurity concentration can be formed in the center of the channel.

Next, using the spacer 24 as a mask, the Si substrate 21 is moved vertically to the surface of the substrate to a depth t=0.1 to 0.5 μm.
After etching is performed to a depth of approximately m to form a protrusion 26 that protrudes perpendicularly to the surface of the substrate and is integral with the Si substrate 21, the spacer 24 is removed by etching (FIG. 2(d)).
. The protrusion 26 is a part that becomes a channel, and impurity diffusion F! J27.27'.

At this time, the etching depth t is set to the impurity diffusion layer 27.2.
By forming the impurity diffusion layers 27 and 27' closer to the substrate surface,
Since parasitic channel paths inside the substrate can be prevented and parasitic current components due to leakage current can be suppressed, the characteristics of the superconducting transistor can be improved.

In addition, as another method for forming the impurity diffusion layers 27 and 27', in FIG. 2(0), no impurity is doped, and in FIG. 2(d), the substrate etching is temporarily stopped at a depth of about t/2, and introduced by exposing it to an impurity atmosphere,
It can also be formed by etching the substrate again.

Next, superconducting material 28 is deposited on the entire surface of the substrate (second
Figure (e)). For example, niobium (Nb) is deposited by sputtering, and etched back to the broken line in FIG. 2C by sputter etching using CF and gas to form the source electrode 29 and the train electrode 30. At this time, by applying a high voltage, the etched back surface can be made into a good flat surface.

In addition, in the above example, the thickness of niobium 28 is approximately twice the depth t.
However, when niobium is deposited to a depth of t,
Due to the presence of the walls of the channel 26, it rises only above the channel 26. Therefore, in this case, by spin-coating an organic film such as a resist on top of it, flattening the surface, and then etching, only the raised niobium on the channel 26 is removed, and the source/drain electrodes 29° and 30° are removed. can be left behind by masking with an organic film. In this way, it is also possible to obtain a structure in which niobium is etched and niobium is filled up to the dotted line portion in FIG. 2(e).

Note that in this embodiment, the source/drain electrodes 29.30
Although niobium was used as the superconducting material used in the present invention, it goes without saying that similar effects can be obtained by using other materials exhibiting superconducting properties, such as indium-lead alloys or oxide superconductors.

Hereinafter, in the same way as the normal MOS transistor manufacturing process,
A Si oxide film, which will become a gate insulating film, is deposited on the entire surface of the substrate to a thickness of 2
A polycrystalline Si film, which will become a gate electrode, is deposited to a thickness of about 300 nm and both are patterned.
After forming the gate insulating film 310 and the gate electrode 320,
An insulating film 330 made of a Si oxide film is formed on the gate electrode 320 and on the sidewalls (FIG. 2(f)').The gate insulating film 310 is formed by heating the upper surface of the channel 26 instead of the deposited Si oxide film. A Si oxide film may be grown by oxidation.

Next, after depositing a passivation film 340, contact holes for the source electrode 29 and drain electrode 30 are opened in the passivation film 340.

Depositing and patterning the AQ wiring to form the source lead wiring 350 and drain lead wiring 360 is as follows.
Similar to a typical MoS transistor.

Example 2 FIGS. 3(a) to 3(d) are process sectional views showing a manufacturing method different from that shown in FIG. 2 for the structure shown in FIG. 1.

First, a Si oxide film (not shown) for protecting the Si substrate is formed on the Si substrate 31 to a thickness of about 1 Onm, and then a Si oxide film (not shown) to a thickness of about 1 Onm is formed.
A Si nitride film 32 of about 5 to 1 μm is deposited by vapor phase epitaxy, and these two layers are patterned using photolithography (FIG. 3(a)).

Next, using the Si nitride film 32 as a mask, the Si substrate 31 is moved vertically to the substrate surface to a depth t=0.1 to 0.5 μm.
Etch approximately m. After this, a thickness of 0.2 is applied to the entire surface of the board.
A Si oxide film 33 of approximately 0.5 μm is deposited by vapor phase growth, and a polycrystalline Si film 34 is deposited on top of the Si oxide film 33.
The polycrystalline Si film 34 is deposited by vapor phase epitaxy to a thickness of 172 or more times the size of the patterned opening.
Flatten the top surface. Next, the polycrystalline Si film 34 is etched back to a level between the upper and lower surfaces of the Si nitride film 32, as shown in FIG. 3(b).

Next, using the polycrystalline Si film 34 as a mask, the Si oxide film 33 is
is patterned by isotropic etching. As a result, the Si oxide film 33 is etched to the level of the polycrystalline Si film 34, that is, to the position indicated by the broken line in FIG. 3(b).

Next, after removing the polycrystalline Si film 34 and the Si nitride film 32 by etching, a Si oxide film 35 is formed on the entire surface of the substrate.
is deposited to a thickness of about 0.3 μm, and a patterned photoresist film 36 is formed thereon (FIG. 3(C)).

Next, the Si oxide film 35 is anisotropically etched in the direction perpendicular to the substrate surface using the photoresist film 36 as a mask to prevent unnecessary etching.
A Si oxide film spacer 37 having a width r is formed on the side wall of the oxide film 33 (FIG. 3(d)).

Next, using the Si oxide film spacer 37 as a mask, the Si substrate 31 is anisotropically etched in a direction perpendicular to the surface of the substrate using the RIE method, so that the substrate is etched as shown by the dotted line in FIG. 3(d). A protrusion 38 is formed that protrudes perpendicularly to the surface and becomes a channel integral with the Si substrate 21. The subsequent process is the second
This can be done in the same way as shown in the figure.

In this example, while masking and protecting the source or drain on each side, the width r=o, os is self-aligned.
~0.1 μm channels can be formed.

In the manufacturing method shown in FIGS. 2 and 3, etching is performed without using a fine photomask, and more specifically, the thickness of the Si oxide film (23 in FIG. 2, 35 in FIG. 3) is , there is an advantage that the channel width r can be well controlled.

In the structure of the above embodiment, the source/drain electrodes and the gate electrode are formed on the upper surface of the substrate, so elements can be integrated and a circuit can be constructed in the same way as when using a conventional MOSFET.

Example 3 FIGS. 4(a) and 4(b) show a third example in which two superconducting transistors are connected. (a) is a cross-sectional view, (b)
is a plan layout diagram.

41 is a Si substrate, 42.43 is a superconducting source electrode and a drain electrode, respectively; 44 is a channel made of a Si thin film that is integrated with the Si substrate 1 and protrudes from the substrate surface; 45.45'
are the impurity diffusion layers of the source and drain electrodes IJii42 and 43, respectively, 46 is the gate electrode, 47 is the gate insulating film,
48 is an interlayer insulating film, 49 is a source lead wiring, and 50 is a drain lead wiring.

In this embodiment, it is possible to integrate the gate width with a processing dimension Wg or a gate interval Wp. Therefore, for example, if a design rule of 0.5 μm is used,
Wg (w
It is possible to realize superconducting integrated circuits for memory and logic with p) of approximately 0.5 μm.

Note that, as shown in the cross-sectional view of FIG. 4(c), a superconducting transistor according to the present invention can be combined with a normal MoS transistor. (c) In the figure, 52,
Reference numeral 53 indicates source and drain regions formed by impurity diffusion layers.

Example 4 FIG. 5(a) is a plan layout diagram of a fourth example in which two superconducting transistors are connected, and FIG. 5(b) is a plan view of A in (a).
-A sectional view. This example is an example in which the channel width is increased in order to obtain a large superconducting current.

51 is a Si substrate, 52 and 53 are a superconducting source electrode and a drain electrode, respectively, 54 is a channel made of a Si thin film that is integral with the Si substrate 1 and protrudes from the substrate surface, 56 is a gate electrode, 57 is a gate insulating film, and 58 is a An interlayer insulating film, 59 a source lead wiring, and 5o a drain lead wiring. Note that the impurity diffusion layers of the source/drain electrodes 42 and 43 are not shown. In this embodiment, as shown in the plan view of (a), the channel 54 has a closed annular shape, so that the source electrode 52 and the drain electrode 53 can be separated from each other by the inside and outside of the channel.

〔Effect of the invention〕

As described above, according to the present invention, the source, drain, and gate electrodes of a superconducting transistor can be provided on a substrate, so that integration can be achieved. Furthermore, since the impurity diffusion layer can be formed only near the surface of the substrate, parasitic channel paths inside the substrate can be prevented, parasitic current components due to leakage current can be suppressed, and the characteristics of the superconducting transistor can be improved.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of a superconducting transistor according to a first embodiment of the present invention, and FIG. 1(b) is a plan view of a superconducting transistor according to a first embodiment of the present invention.
A sectional view, FIGS. 2(a) to (g) are process sectional views showing the method for manufacturing the superconducting transistor shown in FIG. 1, and FIGS. 3(a) to (d) are the steps shown in FIG. FIGS. 4(a) and 4(b) are cross-sectional views showing a manufacturing method different from those shown in FIG. 2 of the structure shown in FIG. (c) is a cross-sectional view showing another configuration example, the fifth
Figure (a) is a plan layout diagram of the fourth embodiment in which two superconducting transistors are connected, and (b) is A-A in (a).
FIG. 1...Si substrate 2...Superconducting source electrode 3...Superconducting drain electrode 4...Channel 5.5'...Impurity diffusion layer 6...Gate electrode 7...Gate insulating film 8... Interlayer insulating film 9... Source lead-out wiring 10... Drain lead-out wiring 21... Si substrate 22... Si nitride film 23... Si oxide film 24... Si oxide film spacer 25... Impurity Diffusion layer 26... Projection (channel) 27.27'... Impurity diffusion layer 28... Superconducting material 29... Source electrode 30... Drain electrode 310... Gate insulating film 320... Gate electrode 330...Insulating film 340...Pudge page film 350...Source lead wiring 360...Drain lead wiring 31...Si substrate 32...Si nitride film 33...Si oxide film 34... Polycrystalline Si film 35... Si oxide film 36... Photoresist film 37... Si oxide film spacer 38... Projection (channel) 41... Si substrate 42... Superconducting source Electrode 43...Superconducting drain electrode 44...Channel 45.45'...Impurity diffusion layer 46...Gate electrode 47...Gate insulating film 48...Interlayer insulating film 49...Source lead wiring 50... Drain lead wiring 52... Source impurity diffusion layer 53... Drain impurity diffusion layer 51... Si substrate 52... Superconducting source electrode 53... Superconducting drain electrode 54... Channel 56... ...Gate electrode 57...Gate insulating film 58...Interlayer insulating film 59...Source lead-out wiring 50...Drain lead-out wiring

Claims (1)

[Claims] 1. A substrate, a pair of source/drain electrodes made of a superconducting material provided on the substrate at a predetermined minute interval, and in contact with the source/drain electrodes and between the two. A superconducting transistor comprising a channel provided on the channel and a gate electrode provided on the channel with a thin insulating film interposed therebetween. 2. The superconducting transistor according to claim 1, wherein the channel is integral with the substrate and consists of a thin film portion protruding in a direction perpendicular to the surface of the substrate. 3. Highly doped impurity regions are provided near the surface of the channel in contact with each of the source and drain electrodes and spaced apart from each other by a predetermined distance. The superconducting transistor described in Section 1. 4. An integrated circuit using the superconducting transistor according to any one of claims 1, 2, and 3. 5. In a superconducting memory element comprising a memory section that retains information using a superconducting current, the superconducting transistor according to any one of claims 1, 2, and 3 is used to store information in the memory section. A superconducting memory element characterized by accessing a superconducting current. 6. A step of forming a first mask pattern on a semiconductor substrate, a step of depositing a second mask film on the entire surface of the substrate, and a step of injecting an etching gas almost perpendicularly to the surface of the substrate, Anisotropic dry etching is performed on the mask film No. 2, and the second mask film is etched only on the sidewalls of the first mask pattern.
a step of forming a second mask pattern by leaving the mask film of the substrate, and using the second mask pattern as a mask, injecting etching gas almost perpendicularly to the surface of the substrate to anisotropically dry the substrate. 1. A method of manufacturing a superconducting transistor, comprising the step of etching to form a channel portion.