KR100204424B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100204424B1 KR100204424B1 KR1019960026317A KR19960026317A KR100204424B1 KR 100204424 B1 KR100204424 B1 KR 100204424B1 KR 1019960026317 A KR1019960026317 A KR 1019960026317A KR 19960026317 A KR19960026317 A KR 19960026317A KR 100204424 B1 KR100204424 B1 KR 100204424B1
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- oxide film
- film
- gate electrode
- forming
- layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 14
- 150000003624 transition metals Chemical class 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 210000000056 organ Anatomy 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 제조방법이 개시된다. 개시된 본 발명은 필드 산화막 및 액티브 영역을 구비한 반도체 기판 상부에 제1산화막, 제1폴리실리콘막, 제2산화막, 제2폴리실리콘막을 순차적으로 형성하는 단계; 제2폴리실리콘막과 제2산화막을 액티브 영역의 소정 부분과 필드 산화막 상부의 소정 부분에 존재하도록 식각하여 제1게이트 전극 및 캐패시터 상부 전극을 형성하는 단계; 제1게이트 전극 양측의 액티브 영역에 저농도 불순물층을 형성하는 단계; 필드 산화막 영역상의 구조물 전면에 제3산화막을 형성하는 단계; 제3산화막이 형성되지 않은 액티브 영역상에만 전이 금속막을 형성하는 단계; 제1게이트의 전극 및 캐패시터 상부 전극을 감싸도록 전이금속막과, 제3산화막 및 제1폴리실리콘막을 패터닝하여 게이트 전극 및 캐패시터를 형성하는 단계를 포함하며, 게이트 전극은 양측의 저농도 불순물층과 일정폭만큼 오버랩되는 것을 특징으로 한다.The present invention discloses a method for manufacturing a semiconductor device. The present invention includes sequentially forming a first oxide film, a first polysilicon film, a second oxide film, and a second polysilicon film on a semiconductor substrate having a field oxide film and an active region; Etching the second polysilicon film and the second oxide film so as to exist on the predetermined portion of the active region and the upper portion of the field oxide layer to form a first gate electrode and a capacitor upper electrode; Forming a low concentration impurity layer in active regions on both sides of the first gate electrode; Forming a third oxide film over the entire structure on the field oxide region; Forming a transition metal film only on an active region in which the third oxide film is not formed; Patterning the transition metal film, the third oxide film, and the first polysilicon film so as to surround the electrode of the first gate and the capacitor upper electrode to form a gate electrode and a capacitor, wherein the gate electrode is fixed with a low concentration impurity layer on both sides. It is characterized by overlapping by the width.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보아 구체적으로는 아날로그 회로에 이용되는 모스 트랜지스터와 캐패시터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS transistor and a capacitor used in an analog circuit.
종래의 아날로그 회로에 이용되는 모스 트랜지스터 및 캐패시터의 제조방법은 제1도에 도시된 바와 같이, 반도체 기판(1)의 소자 분리 예정 영역 상부에 공지된 선택적 산화 방식에 의하여, 필드 산화막(2)이 형성된다.In the method of manufacturing a MOS transistor and a capacitor used in a conventional analog circuit, as shown in FIG. 1, the field oxide film 2 is formed by a known selective oxidation method on the device isolation region of the semiconductor substrate 1. Is formed.
이어서, 전체 구조물 상부에 게이트 산화막(3)과, 게이트 전극 및 캐패시터의 하부 전극을 형성하기 위한 폴리실리콘막이 순차적으로 형성되고, 그 후에, 캐패시터 영역만이 패턴 형성되도록 마스크 패턴(도시되지 않음)이 형성되고, 노출된 캐패시터 영역에 유전체 산화막(5), 상부 전극용 폴리실리콘막이 순차적으로 형성된 후, 유전체 산화막(5)과 상부 전극용 폴리실리콘막은 캐패시터의 하부 전극상의 소정부분에 존재하도록 패터닝되어, 캐패시터의 상부 전극(6)이 형성된다. 그리고, 적층된 폴리실리콘막과 게이트 산화막(1)은, 반도체 기판(1)의 소정 영역 및 필드 산화막(2)의 소정 영역에 위치하도록 패터닝되어, 게이트 전극(4A)과 캐패시터의 하부 전극(4B)이 형성된다. 그리고나서, 마스크 패턴이 공지의 방법에 의하여 제거되고, LDD 구조를 갖는 모스 트랜지스터를 형성하기 위하여, 노출된 반도체 기판(1)에 저농도 불순물층(5)이 형성된다. 이어서, 결과물 전면에 산화막이 형성되고, 이방성블랭킷 식각을 진행하여 게이트 전극(4A)과, 하부 전극(4B) 및 상부 전극(6)의 양측벽에 스페이서(8)가 형성된다. 그리고나서, 게이트 전극(4A)과 스페이서(8)로 노출된 반도체 기판에 고농도 불순물을 이온 주입하여 소오스, 드레인 영역(9)이 형성된다.Subsequently, the gate oxide film 3 and the polysilicon film for forming the gate electrode and the lower electrode of the capacitor are sequentially formed on the entire structure, and then a mask pattern (not shown) is formed so that only the capacitor region is patterned. After the dielectric oxide film 5 and the polysilicon film for the upper electrode are sequentially formed in the exposed capacitor region, the dielectric oxide film 5 and the polysilicon film for the upper electrode are patterned so as to exist in a predetermined portion on the lower electrode of the capacitor. The upper electrode 6 of the capacitor is formed. The stacked polysilicon film and the gate oxide film 1 are patterned so as to be located in the predetermined region of the semiconductor substrate 1 and the predetermined region of the field oxide film 2, and the gate electrode 4A and the lower electrode 4B of the capacitor are patterned. ) Is formed. Then, the mask pattern is removed by a known method, and a low concentration impurity layer 5 is formed on the exposed semiconductor substrate 1 to form a MOS transistor having an LDD structure. Subsequently, an oxide film is formed on the entire surface of the resultant, and anisotropic blanket etching is performed to form spacers 8 on both side walls of the gate electrode 4A, the lower electrode 4B, and the upper electrode 6. Then, the source and drain regions 9 are formed by ion implanting high concentration impurities into the semiconductor substrate exposed by the gate electrode 4A and the spacer 8.
그러나, 상기와 같은 종래의 방법에 의하면, 게이트 전극의 폭이 미세해짐에 따라, 강한 에너지를 갖는 핫 캐리어가 발생하게 되어 모스 트랜지스터의 특성을 열화시키고, 더구나, 소자의 집적밀도가 증가될수록 저농도 불순물 영역이 게이트 전극과 오버랩 되는 폭이 적어지므로 인하여, 핫 캐리어 현상이 더욱더 증폭되게 되어, 소자의 특성을 유지하는데 많은 어려움이 존재하였다.However, according to the conventional method as described above, as the width of the gate electrode becomes smaller, hot carriers having strong energy are generated to deteriorate the characteristics of the MOS transistor. Moreover, as the integrated density of the device increases, low concentration impurities Since the width of the region overlaps with the gate electrode is reduced, the hot carrier phenomenon is further amplified, and there are many difficulties in maintaining the characteristics of the device.
따라서, 본 발명은, 상기한 종래의 문제점을 해결하기 위한 것으로, 반도체 소자의 제조방법에 있어서, 게이트 전극과 저농도 불순물의 오버랩되는 폭을 늘리어, 핫 캐리어 현상을 방지하고, 더불어 게이트 전극의 전도 특성을 개선하여, 모스 트랜지스터의 특성 및 동작 속도를 향상시킬 수 있는 반도체 소자의 제조방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention is to solve the above-described conventional problems, and in the method of manufacturing a semiconductor device, the overlapping width of the gate electrode and the low concentration impurity is increased to prevent hot carrier phenomenon and at the same time conduction of the gate electrode. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the characteristics and improving the characteristics and operating speed of the MOS transistor.
제1도는 종래의 반도체 소자의 제조방법에 따라 형성된 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device formed according to a conventional method for manufacturing a semiconductor device.
제2a도 내지 제2g도는 본 발명에 따른 반도체 소자의 제조방법을 각 공정 순서별로 나타낸 단면도.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention for each process sequence.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 반도체 기관 11 : 필드 산화막10 semiconductor organ 11: field oxide film
12 : 제1산화막 13 : 제1폴리실리콘막12: first oxide film 13: first polysilicon film
14 : 제2산화막 15 : 제2폴리실리콘막14 second oxide film 15 second polysilicon film
16, 19 : 마스크 패턴 17 : 저농도 불순물층16, 19: mask pattern 17: low concentration impurity layer
18 : 제3산화막 20 : 텅스텐막18: third oxide film 20: tungsten film
21 : 게이트 전극 22 : 캐패시터21 gate electrode 22 capacitor
23 : 소오스, 드레인23: source, drain
상기한 본 발명의 목적을 달성하기 위한 것으로, 본 발명은, 필드 산화막 및 액티브 영역을 구비한 반도체 기판 상부에 제1산화막, 제1폴리실리콘막, 제2산화막, 제2폴리실리콘막을 순차적으로 형성하는 단계; 상기 제2폴리실리콘막과 제2산화막을 액티브 영역의 소정 부분과 필드 산화막 상부의 소정 부분에 존재하도록 식각하여 제1게이트 전극 및 캐패시터 상부 전극을 형성하는 단계; 제1게이트 전극 양측의 액티브 영역에 저농도 불순물층을 형성하는 단계; 상기 필드 산화막 영역상의 구조물 전면에 제3산화막을 형성하는 단계; 제3산화막이 형성되지 않은 액티브 영역상에만 전이 금속막을 형성하는 단계; 제1게이트의 전극 및 캐패시터 상부 전극을 감싸도록 전이금속막과, 제3산화막 및 제1폴리실리콘막을 패터닝하여 게이트 전극 및 캐패시터를 형성하는 단계를 포함하며, 상기 게이트 전극은 양측의 저농도 불순물층과 일정폭만큼 오버랩되는 것을 특징으로 한다.SUMMARY OF THE INVENTION In order to achieve the above object of the present invention, the present invention sequentially forms a first oxide film, a first polysilicon film, a second oxide film, and a second polysilicon film on a semiconductor substrate having a field oxide film and an active region. Doing; Etching the second polysilicon layer and the second oxide layer so as to exist on a predetermined portion of the active region and a predetermined portion of the field oxide layer to form a first gate electrode and a capacitor upper electrode; Forming a low concentration impurity layer in active regions on both sides of the first gate electrode; Forming a third oxide film on the entire structure of the field oxide film region; Forming a transition metal film only on an active region in which the third oxide film is not formed; Patterning the transition metal film, the third oxide film, and the first polysilicon film to surround the electrode of the first gate and the capacitor upper electrode to form a gate electrode and a capacitor, wherein the gate electrode comprises a low concentration impurity layer on both sides; It overlaps by a predetermined width.
본 발명에 의하면, 게이트 전극과 저농도 불순물의 오버랩되는 폭을 늘리어, 핫 캐리어 현상을 방지하고, 게이트 전극 상부에 선택적 텅스텐을 형성하여, 게이트 전극의 동작 속도를 증대시키므로써, 반도체 소자의 특성 및 동작 속도가 개선된다.According to the present invention, the width of overlapping gate electrode with low concentration of impurities is increased to prevent hot carrier phenomenon, and selective tungsten is formed on the gate electrode to increase the operation speed of the gate electrode, thereby improving the characteristics of the semiconductor device and Operation speed is improved.
[실시예]EXAMPLE
이하 첨부한 도면에 의거하면 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 제2a도 내지 제2g도는 본 발명에 따른 반도체 소자의 제조방법을 각 공정 순서별로 나타낸 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention for each process order.
먼저, 제2a도에 도시된 바와 같이, 반도체 기판(10) 예를 들어, N 또는 P형의 불순물 타입을 갖는 실리콘 기판의 소자 분리 예정 영역에 공지된 선택적 산화 방식에 의하여 필드 산화막(11)이 형성되어, 액티브 영역이 한정된다. 이어서, 결과물 상부에 게이트 산화막용 제1산화막(12) 제1폴리실리콘막(13), 캐패시터용 제2산화막(14) 및 캐패시터의 상부 전극용 제2폴리실리콘막(14)이 순간적으로 적층된다.First, as shown in FIG. 2A, the field oxide film 11 is formed by a selective oxidation method known in the semiconductor substrate 10, for example, an element isolation region of a silicon substrate having an N or P type impurity type. The active region is defined. Subsequently, the first oxide film 12 for the gate oxide film 12, the first polysilicon film 13 for the gate oxide film, the second oxide film 14 for the capacitor, and the second polysilicon film 14 for the upper electrode of the capacitor are stacked on top of the resultant product. .
이어서, 제2산화막(14) 및 캐패시터의 상부 전극용 제2폴리실리콘막(14)은 제2B도에 도시된 바와 같이, 액티브 영역의 게이트 전극 예정 위치 및 필드 산화막 부분에 존재하도록 패터닝되어 제1게이트 전극(A)과 캐패시터의 상부 전극(B)이 형성된다.Subsequently, as shown in FIG. 2B, the second oxide film 14 and the second polysilicon film 14 for the upper electrode of the capacitor are patterned so as to be present in the gate electrode predetermined position and the field oxide film portion of the active region. The gate electrode A and the upper electrode B of the capacitor are formed.
이어서, 전체 구조물 상부에 감광막이 도포되고, 제2c도에 도시된 바와 같이, 액티브 영역이 노출되도록 노광 및 현상되어, 제1마스크 패턴(16)이 형성된 후, 노출된 액티브 영역에 저농도 불순물이 이온 주입되고, 확산되어 저농도 불순물층(17)이 형성된다. 이때 저농도 불순물은 제1폴리실리콘막 및 게이트 산화막을 통과하여 반도체 기판내에 형성될 수 있을만큼의 에너지 투사 범위로 이온 주입됨이 바람직하다.Subsequently, a photoresist is applied over the entire structure, and exposed and developed so as to expose the active region as shown in FIG. 2C. After the first mask pattern 16 is formed, low concentration impurities are ionized in the exposed active region. It is implanted and diffused, and the low concentration impurity layer 17 is formed. At this time, the low concentration impurity is preferably implanted into the energy projection range enough to be formed in the semiconductor substrate through the first polysilicon film and the gate oxide film.
그 후에, 제1마스크 패턴(16)이 제거되고, 결과물 상부에는 선택적 금속 증착을 위한 제3산화막(18)이 결과물 상부에 고르게 증착된후, 제2D 도에 도시된 바와 같이, 제3산화막 상부에 제2마스크 패턴(19)을 형성하는데, 이 패턴은 아날로그 캐패시터 형성 부분이 가려지도록 형성된다.Thereafter, the first mask pattern 16 is removed, and a third oxide film 18 for selective metal deposition is evenly deposited on the resultant, and then, as shown in FIG. A second mask pattern 19 is formed in the pattern, which is formed so that the analog capacitor forming portion is covered.
그런다음, 제2e도에서와 같이, 제2마스크 패턴(19)으로부터 노출된 액티브 영역상부의 산화막(18)이 습식 식각 방식에 의하여 제거된 다음, 산화막(18)이 제거된 액티브 영역에 선택적 증착 방식에 따라 전이 금속막 바람직하게는 텅스텐막(20)이 형성된다. 이때, 액티브 영역상부의 산화막(18)을 제거하는 것은, 액티브 영역 상부에만 전이 금속만을 선택적 증착시키기 위함이다. 부가하자면, 텅스텐은 산화막이 형성된 영역에서는 선택적 증착이 이루어지지 않으므로, 이러한 성질을 이용하여 액티브 영역상부에만 증착하기 위함이다. 그 후, 제2마스크 패턴(19)이 제거된다. 그러면, 상기 전이 금속막(20)과 제3산화막(18)은 거의 동일선상에 위치하게 된다.Then, as shown in FIG. 2E, the oxide film 18 on the active region exposed from the second mask pattern 19 is removed by a wet etching method, and then the selective deposition on the active region where the oxide film 18 is removed. According to the method, a transition metal film, preferably a tungsten film 20 is formed. At this time, the removal of the oxide film 18 over the active region is to selectively deposit only the transition metal only on the active region. In addition, since tungsten is not selectively deposited in the region where the oxide film is formed, this is to deposit only on the active region using this property. Thereafter, the second mask pattern 19 is removed. As a result, the transition metal film 20 and the third oxide film 18 are almost in the same line.
제2f도에 도시된 바와 같이, 상기 텅스텐막 및 산화막 상부에 게이트 전극 및 캐패시터를 형성하기 위한 제3마스크 패턴(도시되지 않음)이 형성되고, 이 마스크 패턴의 형태로 전이 금속막(20), 산화막(18), 제1폴리실리콘막(13)이 식각되어, 게이트 전극(21)과 캐패시터(22)가 형성된다. 이때, 제3마스크 패턴(도시되지 않음)의 폭은, 제1게이트 전극의 폭 및 캐패시터의 상부 전극 폭보다 크도록 형성되고, 특히, 제3마스크 패턴은, 기관하부에 형성된 저농도 불순물층(17)이 소정 크기 만큼 오버랩 될 수 있도록 형성됨이 바람직하며, 텅스텐막(19)과 산화막(18)은 동일한 식각 속도를 갖도록하여 조절하여 식각한다.As shown in FIG. 2F, a third mask pattern (not shown) for forming a gate electrode and a capacitor is formed on the tungsten film and the oxide film, and the transition metal film 20 in the form of this mask pattern, The oxide film 18 and the first polysilicon film 13 are etched to form the gate electrode 21 and the capacitor 22. At this time, the width of the third mask pattern (not shown) is formed to be larger than the width of the first gate electrode and the width of the upper electrode of the capacitor. In particular, the third mask pattern is a low concentration impurity layer 17 formed in the lower part of the engine. ) Is preferably formed so as to overlap by a predetermined size, and the tungsten film 19 and the oxide film 18 are etched by adjusting to have the same etching rate.
이에 따라, 반도체 기판 영역에서의 게이트 전극(21)은 텅스텐막 및 제1폴리실리콘막에 의하여 둘려싸여 있으므로, 게이트 전극의 전도 특성이 개선될 뿐만 아니라, 스페이서 형성공정이 배제되어, 공정이 단순화되고, 무엇보다도 다층의 게이트 전극의 형성에 의하여, 게이트 전극 하부에 충분한 폭의 저농도 불순물이 형성되므로, 단채널로 인한 핫 캐리어 현상을 방지 할 수 있다.Accordingly, since the gate electrode 21 in the semiconductor substrate region is surrounded by the tungsten film and the first polysilicon film, not only the conduction characteristics of the gate electrode are improved, but also the spacer forming process is excluded, thereby simplifying the process. First of all, since a low concentration impurity having a sufficient width is formed under the gate electrode by forming a multilayer gate electrode, hot carrier phenomenon due to a short channel can be prevented.
그후, 제2g도에 도시된 바와 같이, 모스 트랜지스터 부위가 노출되도록 제4마스크 패턴(도시되지 않음)이 형성되고, 노출된 반도체 기판(10)에 고농도 불순물이 이은 주입된 후, 소정의 열공정이 의하여 소오스/드레인(23)이 형성된 다음 제4마스크 패턴이 제거된다.Thereafter, as shown in FIG. 2G, a fourth mask pattern (not shown) is formed to expose the MOS transistor portions, and a high concentration of impurities are subsequently injected into the exposed semiconductor substrate 10, and then a predetermined thermal process is performed. As a result, the source / drain 23 is formed and then the fourth mask pattern is removed.
이상에서 자세히 설명한 바와 같이 본 발명에 의하면, 캐패시터 형성공정과 더불어, 게이트 전극을 폭이 다른 이중층으로 형성한 다음, 텅스텐막을 감싸도록 형성하여, 접합 영역의 저농도 불순물의 오버랩되는 폭을 늘리어, 핫 캐리어 현상을 방지하고, 텅스텐막에 의하여 게이트 전극의 동작 속도가 향상되어, 반도체 소자의 특성 및 동작 속도가 개선된다.As described in detail above, according to the present invention, in addition to the capacitor forming step, the gate electrode is formed of a double layer having a different width, and then formed to surround the tungsten film, thereby increasing the overlapping width of the low concentration impurities in the junction region, The carrier phenomenon is prevented, and the operation speed of the gate electrode is improved by the tungsten film, so that the characteristics and the operation speed of the semiconductor element are improved.
또한, 본 발명은 별도의 스페이서 공정없이, LDD 구조의 트랜지스터를 형성할 수 있으므로, 제조 공정 시간이 감소된다.In addition, the present invention can form the transistor of the LDD structure without a separate spacer process, the manufacturing process time is reduced.
Claims (5)
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| KR1019960026317A KR100204424B1 (en) | 1996-06-29 | 1996-06-29 | Method for manufacturing semiconductor device |
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| KR1019960026317A KR100204424B1 (en) | 1996-06-29 | 1996-06-29 | Method for manufacturing semiconductor device |
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