JPH02118747A - Message transmission network, bus network and broadcasting of message to multiple processor - Google Patents

Abstract

PURPOSE: To mutually connect plural different processors which simultaneously transmit messages through individual terminals by providing plural nodes being plural active system sub-units. CONSTITUTION: An active logic network constitution body 50 is constituted by the plural bi-directional active logic nodes 54 making ascending hierarchies converting the plural outputs of the plural micro-processors by climbing the hierarchy. The nodes 54 are constituted of bi-directional circuits provided with three ports. The bi-directional circuits can form a tree network and they are connected to the micro-processors 14, 16 and 18-23 at the parts of the base of tree structure. The plural hierarchies are converged to an apex node 54a and the apex node 54a functions as a means for convergence/rotation for inverting the direction of the flow of the message to an up stream and making it face the direction of a down stream.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to message transmission networks, bus networks, and methods for broadcasting messages to multiple processors.

(Prior Art) Ever since the emergence of a highly reliable type of electronic computing II (electronic computer), a system that uses multiple computers has been considered by those engaged in this technical field. By operating these computers while maintaining mutual relationships,
There are systems that allow a given task to be executed in its entirety. In some such multiprocessor systems, one large computer
It takes advantage of its own superior speed and capacity to run the rough parts of a program, while offloading less complex or less urgent tasks to smaller, slower satellite processors. There is a system that reduces the burden on this large computer and the amount of requests to this large computer. In this case, the large computer is responsible for allocating subtasks, for keeping the small processors (--the above-mentioned satellite processors) always active, for ensuring the availability and operating efficiency of these small processors, and for unifying them. The organization shall be responsible for ensuring that the results obtained are achieved.

Another type of multiprocessor system that uses a different approach is one that uses a large number of processors and a common bus system, where the processors are There are systems that have this functionality. These types of systems often use a control computer or control system that is independent of the rest of the system to monitor the availability and processing power of individual processors for a given subtask, and to The task and information transfer route are controlled. Additionally, the configuration and operation of each processor may not be configured such that the processor itself can monitor the status and availability of other processors and determine the routes for forwarding messages and programs. be. A significant drawback common to the various systems described above is that software is required and operating time is consumed to perform overhead and maintenance functions, thereby preventing the performance of the intended purpose. will be affected. The amount of work involved in determining and monitoring forwarding paths increases quadratically with the total number of processors involved in those tasks, until an inappropriate amount of effort is expended on overhead functions. There is also.

The following several patent publications are illustrative of prior art.

U.S. Patent Publication No. 3,962.685 - Belle 15le No. 3,96
No. 2,706 - Dennis Chima No. 4,0
9 [i, No. 586 - Borie ground floor No. 4
,098,567'--Millard
Chima No. 4,130,885 - Heart
Chima No. 4,136.388 1 Annunziata Chima No. 4
, 145,739 - Dunning ground floor No. 4,151,592 - Suzuki
Since the early days of the early ``Binac'' (using 72 processors connected in parallel) and various similar systems, multiprocessor systems have been known to provide redundant execution capabilities. It was recognized that this could significantly improve the overall reliability of the operating system. To date, there are considerable constraints, but these constraints are mainly due to the fact that the software becomes enormous.
be. Nevertheless, multiprocessor operation is particularly advantageous in various situations where system downtime is unacceptable, such as in real-time applications. Various multi-Brosé Lisa systems have been developed so far, but
However, although these systems operate well,
Overhead required a significant amount of software and operating time. Such conventional systems are disclosed in U.S. Patent Publication No. 3,445,8
No. 22, No. 3.566.363, and No. 3.59
A specific example is given in No. 3.300. These patent publications all relate to systems in which multiple computers have access to a single main system that is shared among them, in which C further distributes tasks to individual processors. In order to appropriately allocate the processing capacity to the processing demand, the processing capacity is compared with the processing demand.

Yet another example of the prior art is U.S. Pat.
There is No. 99,233. In the system disclosed in this publication, multiple processors share one bus, and a control unit 1-1 having a built-in buffer register is used to connect the transmitting side miniprocessor and the receiving side miniprocessor. A transfer of data blocks is performed. The system's outlets are used in Europe for decentralized mail sorting systems.

U.S. Pat. No. 4,228,496 relates to a commercially successful multiprocessor system,
In this system, multiple buses provided between multiple processors are connected to a bus controller, and this bus controller monitors the data transmission status and prioritizes multiple data transfers between processors. Ranking is being determined. Furthermore, each processor can be connected to control one of the plurality of peripheral devices.

``Ethernet'' system jointly promoted by Xerox, Hewlett-Paracard, and Intel (U.S. Pat. Nos. 4,083,220 and 4,099)
, 024) present yet another approach to addressing the problem of intercommunication between multiple processors as well as peripheral devices. All units (-processors, peripherals, etc.) are connected to a multiple access network that is shared among them, and the units will compete with each other for priority. Collision detection is performed in a time-first manner, which makes global processing power difficult to control, coordinate, and articulate.

In order to fully understand the various systems described above in their details, it is necessary to analyze in detail the patent publications mentioned above and other related references. However, when task sharing is used, these systems all require a significant amount of intercommunication and administrative control to determine priority and select processors for data transfers. This can be understood from a simple overview. The problems encountered when expanding a system to include more processors vary from system to system, but all of the above systems Such expansions add complexity to the system software, application programming, hardware, or all three. Also, as will be appreciated with some consideration, the use of one or two logically passive ohmic buses imposes inherent limitations on the size and power of multiprocessor systems. is imposed on. There are a variety of techniques that can be employed to facilitate intercommunication, such as those illustrated in recently issued U.S. Pat. No. 4,240,143. However, there are techniques such as grouping subsystems into global resources, but of course there is a limit to the amount of traffic that can be used when a large number of processors are used. , and the fact that the delay time takes on various values creates a problem that is difficult to overcome. Situations may occur where one or more processors become locked out or deadlocked, and in order to handle this situation, additional circuits and circuits are required to solve the problem. software is required. From the above, it is clear that conventionally it was not practical to significantly expand the number of processors to, for example, 1024 processors.

In many different applications, it is desirable to escape the limitations of existing rusting techniques described above and take full advantage of modern techniques. The lowest cost techniques currently available are those based on mass-produced microprocessors and two large-capacity rotating disk storage devices; as,
There is a device made by Winchiesta Technology that has a very small gap between the head and the disk inside a closed case. When expanding a multiprocessor system, it is desirable to be able to expand the system without unduly complicating the software, and furthermore, to ensure that the software does not become complicated at all as the expansion occurs. There are even demands for it to be able to be expanded in this way. Furthermore, there is a need for the ability to process computer problems characterized by a distributed structure in which the overall functionality can be dynamically subdivided into multiple processing tasks that are executed in a limited or iterative manner. . Almost all database machines belong to such problem areas, and this problem area also includes sorting, pattern recognition and correlation calculations, digital filtering, and large matrix calculations. , simulation of physical systems, and other typical problem examples are also included. In any situation where any of these processes is performed, it is necessary to keep the multiple tasks to be processed individually relatively simple and to distribute these tasks over a wide range, which results in a large instantaneous task load. Become something. Such situations have been very difficult for traditional multiprocessor systems because they increase the time spent on overhead and the amount of software for overhead. This is due to the fact that it has a tendency to cause problems, and that it causes practical problems in configuring the system. For example, when a passive shared bus is employed, the speed of propagation as well as the time required to transfer data constitute an absolute barrier to the possible processing speed of processing transactions.

Database machines are therefore a good example of the need for improvements in multiprocessor systems.

Three basic methods for configuring large-scale database machines have been proposed so far: a hierarchical method, a network method, and a relational method. Among these, relational database machines allow users to easily access given data in a complex system by using tables that indicate relationships. The system machine is recognized as having powerful potential. Representative publications describing this prior art include, for example, IEEE Computer Magazine, March 1979 issue, page 28, by D.C.P. Smith and J.M. Smith, entitled ``Relational Database Machines''
e1ationalData Ba5e Machine
e, published by D,C,PSIQ
ith and J, M, Sm1th, in th
e March 1979 issue of IEEE
Computer magazine, p. 28
), U.S. Patent Publication No. 4,221,003, and various papers cited therein.

Additionally, sorting machines are
This is a great example of the need for architectural improvements. An overview of sorting machine theory can be found in D., E.
"Searching and Sorting" by Knuth, pages 220-246.
and Sorting” by D,E,
Knuth.

pp, 220-246. published (
1973) by Addison-Wesley
Publishing Co., Reading,
Massachusetts-setts).

This document discloses various networks and algorithms, which must be considered in detail in order to understand the constraints associated with each of them.
However, what can be said about them - boat fishing - is that they are all characteristically complex methods that are oriented only to the specific purpose of sorting. As yet another example, L, A, Mo1la
There is one presented by ar), which is
rI EEE Transactions on Computers J, Volume C-28, No. 6 (June 1979), No. 406
The article entitled "Structure of a wrist marching network" published on pages 413 to 413
entitled”A Design for a
Li5t Merging Network”, 1n
the IEEE Transactions on
Coll1puters, Vol.

C-28No, 6. June 1979 at p
p., 406-413). The network proposed in this paper uses a method in which the merge elements of the network are controlled externally, and the network requires programming to perform special functions.

Functions that a general-purpose multiprocessor system must be able to perform include the ability to distribute subtasks in various ways, the ability to determine the status of processors executing subtasks, and the ability to merge and sort messages. functions to perform, correct and change data;
Additionally, there is the ability to see when and how responsibility changes (e.g., when a processor goes off-line and comes back on-line). In order to perform the functions described above, it has been necessary to use excessive software and hardware for overhead.

- For example, in a multiprocessor system such as a database machine, when specifying a message transfer route between processors, a specific
Rather than selecting one processor as the transfer destination, or selecting multiple processors belonging to one class, or even specifying the processor itself, parts of the database that are distributed to the processors by hashing etc. It is often necessary to select a destination processor by specifying the destination processor. Some known systems utilize pre-communication sequences to establish a linkage between a transmitting processor and one or more particular receiving processors. Establishing this linkage requires sending multiple iterations of requests and acknowledgments, and additional hardware and software must be used to overcome possible deadlock conditions. . In systems that do not utilize prefix communication sequences, control is performed by a single processor or by a bus controller, which controls whether the transmitting processor is ready to transmit, the receiving processor This is to ensure that the processors are ready to receive, that other processors are locked out of the linkage between them, and that no extraneous transmissions are occurring. In this case, too, the dependence on overhead and the complexity required to avoid deadlocks make it difficult to maintain maintenance functions as the system scales (e.g., beyond 16 processors). is expanded to an inappropriate extent.

Yet another example of the requirements placed on modern multiprocessor systems concerns how the system reliably determines the status of subtasks being executed by one or more processors. be. The basic requirement is that it must be possible to query a given processor about its status, and that its status must be affected by the In other words, the inquiry must be conducted in such a way that there is no ambiguity in the content of the response. The term semaphore is currently used in the industry to characterize the ability to test and set status displays as an uninterrupted series of operations. Although it is desirable to have this semaphore feature, it must be incorporated without reducing execution efficiency or increasing overhead. Determination of such status requires further multiprocessor processing.
It is extremely important when performing sort/merge operations in a system that multiple subtasks within a larger task must be properly combined to combine their respective processing results. This is because they cannot be combined into one until the processing is completed. A further requirement is that the processor must be able to report its "current"status;
In some cases, a subtask must be executed only once, even if the multiprocessor's operating sequence is repeatedly interrupted and modified.

Most existing systems present a significant problem in this regard because the processor's execution routines are interruptible. In other words, as is easily understood, when multiple processors are executing multiple subtasks that are related to each other, the degree of readiness (=what kind of operation) of each processor is The sequence of operations involved in making adjustments and responding to them (the extent to which the As a result, it grows to an inappropriate level.

(Problems to be Solved by the Invention) A typical shortcoming in conventional multiprocessor systems, such as those described in section 2 above, is related to the so-called "distributed update" problem. That is,
This means that information, a copy of which is stored on each of the plurality of processing devices, needs to be updated. The information referred to herein may be information consisting of data records or may be information used to control the operation of the system. Controlling the operation of this system means, for example, that processes are started, stopped, restarted, and interrupted, such that necessary steps are not inadvertently repeated or not performed at all. It also refers to control such as rolling back or rolling forward. In conventional systems, the various solutions to the distributed update problem all have significant limitations. Some of these solutions are only 1°, targeting only two processors at a time. Still other solutions have been developed using intercommunication protocols, but these protocols are so complex that even today their suitability cannot be tested using mathematical rigor. It is extremely difficult to prove this.

The complexity of these protocols is due to the uninterrupted
It is necessary to provide a control bit that has the external property of being "tested and set" in all processors by one operation. Because such control bits are located within multiple separate processors, and because of the varying delay times associated with communication between those processors, noise is introduced by the communication channel, which can inevitably be imperfect. will be generated, and the error rate will also increase. Therefore, “
The characteristic of "a single uninterrupted operation" means that the multiple parts that make up one operation are diverse and can be interrupted, and that they can be performed at the same time. It will be readily understood by those skilled in the art that this can be difficult if the source cannot be accessed, and furthermore, if the source is prone to problems between accesses. Good morning.

SUMMARY OF THE INVENTION The present invention, in summary, provides a bidirectional network that interconnects a plurality of different processors through individual terminals that intentionally send messages to each other simultaneously. be. The network includes nodes, which are active system subunits, that respond to data contained in received messages to send a top priority message. Select. These subunits are arranged in multiple hierarchies in a tree structure that converges toward an apex (vertex), where one or a common top-priority message is obtained. This @borrower message is directed downward through multiple subunits forming a hierarchy.
The first one is sent back to multiple terminals.

(Operation) In the above configuration, the plurality of subunits perform sorting or merging in the convergence direction (upstream direction),
In addition, in the diffusion direction (downstream direction), the sea urchin is directed to the broad dregs 1, and each direction has a different function. Furthermore, during operation, control signals are sent back from the subunit to the terminal.

(Margin below) (Example) Embodiments of the present invention will be described below with reference to the drawings.

(Database Management System) The system generally shown in FIG. 1 is a concrete example of the application of the concept of the present invention to database management. More specifically, the system includes one or more host computer systems 10.
．． For the purposes of this example, the host computer system may be a computer system belonging to the 18M370 family or the DEC-FDP-11 family, for example. It is designed to run on existing common operating systems and application software. According to IBM's nomenclature, the main intercommunication network between a host computer and a database computer is called a channel, and the same is called a DE.
According to the nomenclature of C, it is called a "unibus" or "mass bus" or a slightly modified version of these terms.

Regardless of whether any of the above computer systems are used, or other manufacturers' mainframes
Regardless of the computer used, this channel or bus is an ohmic or logically passive transfer path to which database tasks and subtasks are sent.

The example of FIG. 1 shows a backend processor complex associated with a host system 10.12. The system in this figure accepts tasks and subtasks from a host system, refers to the appropriate portions of a vast database of stored information, and returns appropriate processed or response messages. Regardless of the configuration of this back-end processor complex, the target system is designed to run in a manner that requires no other than less sophisticated software management from the host system. Therefore, it is possible to configure a user's database as a new type of multiprocessor system, in which data is stored in relational database files that can greatly expand capacity. can be organized as,
Moreover, this expansion can be done 71 without the need to change the operating system or existing application software contained within the user's host system. A specific example configured as an independent system (stand-alone system) will be described below with reference to FIG. 20.

As will be understood by those skilled in the art, operational functions related to relational database management can be divided into multiple processing tasks that can be processed independently, at least temporarily. It is an operational function that allows you to The reason for this is that in a relational database, multiple stored data entries are not interdependently linked by 71-res pointers. Furthermore, as will be understood by those skilled in the art, there are many other applications in addition to relational database management that can be used to dynamically subdivide limited or recurring tasks into smaller pieces for independent processing. Many data processing environments exist. Accordingly, the detailed description of the present invention will be described in relation to processing problems in database management, which are particularly desired and frequently heard, but the novel methods and configurations disclosed herein will be discussed in detail. has a wide range of other uses as well.

Large data management systems will have both the potential benefits and the inevitable attendant difficulties when using multiple processors. A huge number of entries (descriptions) reaching hundreds of millions,
It must be kept in storage and easily and quickly accessible. On the other hand, a relational database format allows a wide range of data entry and information retrieval operations to be performed concurrently.

However, in the overwhelming majority of database systems, maintaining the integrity of the database is just as important as processing transactional data quickly. Data integrity is
It must be maintained before and after hardware failures, power outages, and other disasters related to system operation. Furthermore, the database system
The ability to restore the database to a previous known state must be provided to clean up user errors, including bugs in application software code. Furthermore, data must not be accidentally lost or manipulated, and whether the event relates to new data or correction of past errors. Or, depending on whether it is related to the calibration of a part of the data base, all parts of the database related to a particular entry must be changed.

Therefore, for integrity, in addition to the operations of data rollpacking and recovery, the operations of error detection and correction, and the detection and compensation of changes in the status of individual parts of the system, in addition to Redundancy is also necessary for database systems. To achieve these goals, the system may have to be used in many different specialized modes.

Furthermore, in recent systems, the format of arbitrary content tends to be complex.
nary queries) and the ability to respond in an interactive manner if necessary. People attempting to access the system should not be required to be experts in the system, even if the query is complex.

Examples of arbitrary inquiries that may arise in connection with large-scale production operations include:

A8: The manager in charge of production management not only requests a list of one item in inventory, but also requests a list of items whose production exceeds the monthly production of parts whose production has decreased by at least 10% compared to the same month of the previous year. You may request an inventory list specifying all parts in stock.

B. A marketing manager not only determines whether a particular account is 90 days past due, but also for customers who have a history of exceeding 120 days, especially those located in depressed areas. - The law may require 90 days of receivables.

Not only does the C0 human resources executive require a list of all employees who have taken more than two weeks of sick leave in a given year, but also for two or more of the immediately preceding five years.
You may be asked to list all long-term employees with 10 years or more of sick leave during the fishing season for one week or more.

In each of the above examples, the user attempts to determine the real problem facing the business by relating information stored on the computer in a way that has not been done before. A database system that allows experts without computer training to process complex queries, provided that the user has experience in the field in question, and therefore has intuition and imagination. can be used freely.

Modern multiprocessor systems address these multiple and often conflicting requirements by using specifically designed overhead and maintenance software systems. However, I am trying to
These software systems are wooden and prevent easy expansion of the system. However, the concept of scalability is a highly sought-after concept because as a business grows, it becomes desirable to extend and continue using an existing database management system. In this case, they don't want to be forced to adopt new systems and software.

Multiprocessor Array Referring to FIG. 1, a typical embodiment system of the present invention includes a number of microprocessors, of which there are two important types. will be referred to herein as an interface processor (IFP) and an access module processor (AMP), respectively. Two IFPs 14.16 are shown in the figure, each connected to a separate host computer io to 12 input/output devices. A number of access module processors 18-23 are also included in this multiprocessor array. The term "array" herein refers to a set of processor units, a group of processor units, or a plurality of processor units arranged in a generally ordered linear or matrix configuration. ``array processor,'' and therefore does not refer to what has recently come to be called an ``array processor.''

Although only eight microprocessors are shown in the diagram to provide a simplified conceptual example of this system, it is possible and typically not It will be done.

IFP14.16 and AMP18-23 are Intel 8086 processors with internal memory and main memory that provides direct memory access to peripheral controllers.
It has a built-in 16-bit microprocessor. Any of a wide variety of microprocessor and microprocessor system products from a variety of manufacturers are available.

The "microprocessor" is just one specific example of one type of computer or processor that can be used in the array, since the system concept is
This is because if the computing power required for the application is that of a minicomputer or a large computer, it can be used to advantage. This 16-bit microprocessor provides significant data processing power and is a low cost, standard replaceable configuration that can be replaced with a wide variety of available hardware and software options. This is an advantageous example of a device.

IFPs and AMPs employ similar circuitry including active logic and control logic and interfaces, microprocessors, memory, and internal buses, which are described in FIGS. 1 and 8, respectively. I will explain later. However, these two processor types differ in the nature of the peripherals associated with each processor type and in the control logic for those peripherals.

As will be readily understood by those skilled in the art, other processor types with different peripheral controllers and assigned different functional tasks may easily be incorporated into the present invention.

Each microprocessor is equipped with a high speed random access memory 26 (described in connection with FIG. 8) which, in addition to buffering input and output messages, It performs message management by collaborating in unique ways with other parts of the system. Briefly, the high speed random access memory 26 serves as a circular buffer for variable length human messages (this input is referred to as "receive") and for sequential output of messages ( This output serves as a memory (referred to as ``send''), incorporates a table index portion for use in hash mapping mode and other modes, and serves as a receiver (referred to as ``send'') memory for use in hash mapping mode and other modes, and a Stores control information.Memory 26 is also used to serve a unique role in multiprocessor mode selection and in handling data, status, control, and response message traffic, as will be described in detail below. The memories are further configured such that local and global status determination and control functions are processed and communicated in a highly efficient manner based on the transaction identity in the message. IFP14.16 and AMP
Control logic 28 (
(described below in connection with FIG. 13) are used to transfer data and perform overhead functions within the module.

IFP14, 16 are each interface control circuit 30
This interface control circuit 30 is equipped with an I
The FP is connected to a channel or bus of a host computer 10-12 associated with the IFP. On the other hand, in AMPs 18 to 23, the device corresponding to this interface control circuit is the disk controller 32;
may have a general structure, and AMP18-2
3, and the magnetic disks individually combined with them.
These are used to interface with the drives 38-43, respectively.

Magnetic disk drives 38-43 provide secondary or mass storage for the database management system. In this embodiment, the magnetic disk drives are constructed from proven commercially available products, such as those manufactured by Winchester Technology, which provide very low cost per byte and high capacity. This makes it possible to obtain a highly reliable storage device.

These disk drives 38-43 store a relational database in a distributed storage manner, which is shown in simplified form in FIG. Each processor and its associated disk drive is assigned a plurality of records that form a subset of the database; this subset is a "-order" subset, and its The subsets are disjoint subsets and together constitute a complete database. Therefore, each of the 01H storage devices will hold - of this database. Each processor is further assigned a subset of data for backup, and the buffer wrap period subsets are also disjoint subsets, each forming a part of this database. As can be seen from Figure 22, each secondary file is duplicated by a backup file stored in a processor different from the processor in which the secondary file is stored; , two complete databases are obtained, each distributed in a different distribution manner.

In this way, the integrity of the database is protected by arranging secondary data subsets and backup data subsets with redundancy. This is because if a failure occurs, it is unlikely that it will have a practical impact on multiple data spanning several large-scale blocks or multiple relationships forming multiple groups.

Database distribution is also associated with hashing operations for various files, as also shown in FIG. 22, and with the incorporation of hash mapping data into messages. ing. The files contained in each processor are organized into simple hash packets, represented as groups of binary sequences.
h bucket). Therefore, based on the table of relationships specified by those packets, it is possible to determine where relations and tuples should be placed in the relational database system. A passing algorithm is used to determine packet assignments from keys within this relational database system, which allows for easy expansion and modification of this database system.

The storage capacity selected depends on database management needs, transaction volume, and processing power of the microprocessor associated with the storage device. Multiple disks
Although it is possible to connect a drive to one AMP or to connect one disk file device to multiple AMPs, such modifications would typically be limited to special applications. Database expansion is typically accomplished by expanding the number of processors (and the number of disk drives associated with the processors) in a multiprocessor array.

Active Logic Network The purpose of providing an orderly flow of message packets and facilitating the execution of tasks requires a unique system architecture centered around a novel active logic network construct 50 and This is achieved by employing a message structure. The active logic network structure 50 includes a plurality of bidirectional active logic nodes in an ascending hierarchy that converges the outputs of the plurality of microprocessors while climbing the hierarchy.
active logic node) 54. These nodes 54 consist of bidirectional circuits with three ports, which are arranged in a tree network.
: a network with a dendritic structure), in which case the microprocessors 14.16 and 18-23 can be formed at the base of the tree structure.
connected to.

As will be understood by those skilled in the art, a node can be configured when the number of logic sources exceeds two, for example four or eight, in which case it also simultaneously increases the number of source inputs. The problem of adding more combinatorial logic can also be transformed into the problem of adding more combinatorial logic.

To make it easier to refer to the diagram, notes (N) that belong to the first hierarchy are represented by a bfix "■", and notes that belong to the second hierarchy are represented by a bfix "■". It is represented by the brifix r II J, and the same applies hereinafter. Individual nodes belonging to the same hierarchy are denoted by the subscript “11.
If it is the fourth node in the hierarchy, it can be expressed as 'lN4J. On the up-tree side (i.e., upstream side) of the node is “
There is one port named ``C port'' that is connected to one of the two down tree ports of an adjacent node belonging to a higher hierarchy, and that - Tree - Ports are named "A port" and "B port" respectively. These multiple hierarchies have a top node, that is, a vertex node 54a.
This vertex note 54a reverses the flow direction of the upstream message (up tree message) and moves downstream (down tree direction).
It functions as a means of convergence and turning toward the future. Two sets of tree networks 50a, 50b are used, and the nodes and interconnections in the two sets of networks are arranged in parallel with each other, thereby achieving the desired results for large-scale systems. You're getting redundancy. Since the nodes 54 and their networks are identical to each other, it is sufficient to describe only one of the networks.

For the sake of clarity, it must first be understood that a large number of message packets in the form of a serial signal train are connected to an active logic network 50 by the connection of many microprocessors. This means that they are simultaneously transmitted to, or can be transmitted simultaneously. A plurality of active logic nodes 54 each operate on a binary basis and interact with each other. Priority is determined between ili-specific message packets, and this priority determination is performed using the data contents of the message packets themselves. Furthermore, all nodes 54 in a network are under the control of one clock source 56, which synchronizes the stream of message packets toward the apex node 54a. These nodes 54 are combined in such a manner that they can be advanced. In this way, each successive byte etc. in the serial signal stream is advanced to the next level, and the progression of this byte is such that its corresponding byte in another message is This is done at the same time as a similar proceeding along another route within this network 50.

A sort is performed on message packets moving up the tree to give priority between competing signal sequences, which ultimately results in
A single message string is selected to be redirected downstream from vertex node 54a. Because the system is configured as described above, it is no longer necessary to make a final priority determination at one specific point within a message packet, and therefore the two Message forwarding can continue without requiring anything more than a binary-based determination between two colliding packets. As a result, the system selects messages and transfers data spatially and temporally, but does not gain control of the bus or identify the sending or receiving processor. There is no delay in message transmission for the purpose of processing or performing handshaking operations between processors.

Additionally, it is important to be aware that if several processors send identical packets at the same time, if the transmission is successful, it is the same as if all of the sending processors were successful. That means it will happen. This property saves time and overhead and is extremely useful in providing effective control of large multiprocessor complexes.

Node 54 also operates in a bidirectional manner, thereby allowing unimpeded downstream distribution of message packets. For a given node 54, a downstream message received at port C on its up-tree side is distributed to both port A and port B on its down-tree side;
Furthermore, it is transferred to both of two nodes connected to this node that belong to adjacent lower hierarchies. Under the control of common clock circuit 56, message packets are synchronously advanced down the tree and broadcast to all microprocessors simultaneously.
(st knee broadcast), thereby enabling one or more processors to perform a desired processing task or accept a response.

Network 50 has a data transfer rate that is faster than that of a microprocessor, typically more than twice as fast. In this embodiment, network 50 has a byte clock interval of 120 nanoseconds, and its data transfer rate is five times faster than a microprocessor. Each of the three ports of each node 54 is either a port of a node belonging to an adjacent hierarchy connected to the node, or
Alternatively, the connection is connected to a microprocessor through a set of data lines (10 in this example).
and control lines (two in this embodiment), and the two control lines are respectively assigned to a clock signal and a collision signal. The data line and the clock line are wired in pairs, with separate lines in the up-tree direction and the down-tree direction. Collision lines only propagate down the tree.

The above connection structure forms a full-duplex data path such that no delay is required to "reverse" the drive direction of any line.

Referring now to Figure 3, the 10 data lines contain 8-bit bytes, represented by bits 0 through 7, which fill 8 trees of the 10 data lines. is occupying.

Another line, designated C, is a control line, which carries control sequences used to specify different parts of the message packet in a particular way. , the 10th bit is used for odd parity in this embodiment. As will be understood by those skilled in the art, the system may have more or less bits in the above data path and can easily operate with such changes.

A sequence of bytes is arranged to form a series of fields, essentially divided into a command field, a key field, a destination selection field, and a data field. . As explained in more detail below, a message may use only one field and may also have a detectable
It ends with the "End of Message" code. “Idols” intervening between messages
The 1dle field is represented by an unbroken series of 1's on the C line and on lines 0-7, and is transmitted whenever no message packets are available. There is. Parity lines are also used to convey changes in the status of individual processors in a unique manner.

The "idle state" (id165tate) is a state that exists between messages and is not part of a message packet. Message packets typically begin with a 2-byte command word containing a tag, which indicates whether the message is data
If it is a message, the transaction number (TN)
If the message is a response message, it is in the form of an originating processor ID (OPID). Transaction numbers have various levels of significance within the system and serve as the basis for many types of functional communication and control. This command word is followed by a variable-length key field and a fixed-length destination selection word (destination 5 select).
ion word: DSW), or both, and these are variable-length data files.
It forms the first part of the field. The key field serves the purpose of providing a criterion for sorting messages when the messages are identical except for the key field. DSW provides the basis for a number of special functions and also:
It deserves special attention along with TN.

The system is designed to work with a word-synchronized interface, so that all processors attempting to send packets
The first byte of the word is sent to the network 50 simultaneously with each other.
It is designed to be sent to. The network uses the data contents of the following fields to sort on a binary basis at each node, with the sorting being done in such a way that priority is given to the lowest numerical value. In the continuous data bit.../t,
If we consider bit C to be the largest quantity and bit O to be the smallest quantity, then the sorting priority is as follows.

1. First sent to network 50; 2. Command code (command word) is the lowest value; 3. Key field is the lowest value; 4. Key field is the lowest value.
5, where the field is the shortest; 1, where the data field (including the destination selection word) is the minimum value; 6. The one with the shortest data field.

In view of the purpose of explaining the overview here, it is particularly important to note that once the priority is determined at the node 54, a collision indication (=collision indication, hereinafter referred to as A cot or B cot) ) is returned to the route of the party that received the transmission that lost in this priority determination. This collision display indicates that the microprocessor that is transmitting
It may recognize that its transmission has been aborted because the network 50 is being used for higher priority transmissions, and that it should therefore attempt to transmit again at a later time.

Examples of reduced purity are shown in various diagrams in FIG. In this embodiment, network 50 operates in conjunction with high-speed random access memory arranged in a tree structure using four separate microprocessors. To explain in more detail, the microprocessors include an IFP14 and three AMPs.
18, 19 and 20. Total of 10 side causes 2A, 2
B,...2J each correspond to one of ten consecutive time samples from 1=0 to t=9, and the the distribution of different simplified (four character) serial messages sent by each of the microprocessors of the port and the communication between the ports and the microprocessors at their various times; It shows the status of. , 4L, the drawings labeled simply as FIG. 2 show the state of the system before the start of signal transmission. In each of the above figures, the null state (nu
ll5tate: zero state) In other words, in order to be in the idle state, transmission indicated by "mouth" must be occurring. Since there is an agreement that the data content having the smallest value has priority, the message packet r sent from AMP+9 in FIG. 2A
EDDV will be the first message packet transmitted through the system. Each message in the figure is associated with a high speed random access memory (H5, RA
(sometimes referred to as M). H
, S, RAM 26 has an input area and an output area shown schematically in FIG.
At the time of 1=0, there is a FIFO in this output area.
They are arranged vertically on a first-in, first-out basis.
As a result, when transferring, H, S, RAM2 in the figure
It can be taken out as directed by the cursor arrow written in 6. At this point, all transmissions within network 50 are in a null or idle state (b).

On the other hand, at time t-16 shown in FIG. 2B, the first bytes to each message bucket 1 are sent to the network 5o at the same time as node 54 is still returning an idle status indication, and all transmission status above the first layer is also idle. During the first clock interval, the first byte of each message is set inside the lowest nodes IN and IN2, the contention is resolved at t=2 (Figure 2C), and C, J: Both transmission in the flow direction and transmission in the downstream direction are executed consecutively. Node I N + receives rE,1 on both its human ports and forwards it upstream to the next layer, and downstream to both send I3 processors. The state is displayed as undetermined. However, node IN2, which belongs to the same IPJ layer, receives "
In the case of a conflict between "R E" and "Pj" from the processor 20, it is determined that "r E" has priority, and port A is connected to port C on the up-tree side. while coupled to the microprocessor 20
The B cot signal is returned to the B cot signal. When the B_cal signal is returned to microprocessor 20, the IN2 node has effectively locked its six-input port to the C output port, thereby allowing the serial signal stream from microprocessor 19 to be routed to apex node II. N! will be transmitted to.

1N, the first two characters in the node are both r
EDJ, and therefore, as shown in FIG. 2C, it is impossible for this node to make a decision at time t=2. Furthermore, three microprocessors 14.
The common leading letter "E" sent from 15 and 19 reaches the II N 1 vertex node at time t=3 (Fig. 2D), and this letter "E" is also sent to all those messages. The second common character "When DJ is transferred to this vertex node II N!, the direction of the transfer is reversed and directed downstream. At this point, the node IN, cannot yet make a decision. However, at this time, a series of microprocessors 14.
3rd letter "F", "E" from 18 and 19 respectively
” and “D” are being sent to this node IN.

The fact that microprocessor 20 receives the B_cal signal means that this processor 2o has been defeated in the competition for priority, so if this processor 20 receives the B_eol signal, it will display an idle indication ( (b) is transmitted, and from then on, only this idle display (b) is transmitted. Each cursor arrow written to each output buffer is
o indicates that it has been returned to its initial state, but the other microprocessors continue to send successive sequences of characters. Therefore, the important events at time t-4 (Figure 2E) are that a decision is made regarding the port of node IN, and that the first character ('EJ) is passed through all lines to the first layer. This means that the data is inverted and transmitted to the node hierarchy.

A second collision appears at time t=5 (FIG. 2F), in which case the B port of node II N wins the contention and Acol is generated.

During the next several clock times, the serial signal train continues to be broadcast downstream, and t
At time =6 (FIG. 2G), the first character of the message is set in all the H, S, and input areas of the RAM 26. Another thing to note here is that the priority determination previously made in note IN is invalidated at this point, and the reason for this is that the priority determination made earlier in note IN is invalidated at this point. When the third character ('EJ) sent from the microprocessor 19 loses the competition with the third character ('DJ) sent from the microprocessor 19, the nodes II N 1 to A c of the higher hierarchy
This is because ol is displayed. As indicated by the cursor arrow in FIG. Already completed on time. As can be seen from Figures 2H, 2■, and 2J, priority messages r E D D are sent into all input buffers one after another.
VJ is loaded. At t=8 (Fig. 2), this message has already flowed out from the first floor of the cabinet, and the vertex node 11 N r has already been reset at t=7, but this is because
This is because by the time the last downstream character is transferred to the microprocessor, only the idle signals are already competing with each other. At time t=9 (FIG. 2J), the nodes IN and IN2 belonging to the first hierarchy have been reset, and the defeated microprocessor 14
．． All of 18 and 20 will once again compete for priority on the network by sending out the first characters of the message once the network is again indicating idle. In practice, as will be explained later, an acknowledgment signal is transmitted to the winning microprocessor, but this is not essential for the fullest generalization of the invention.

After a message has been broadcast to all microprocessors in this manner, it may be utilized by any or all of the microprocessors as needed. How many microprocessors are used depends on the mode of operation and the functions performed, and there are many variations in these modes of operation and functions.

(Global Intercommunication and Control) The example described above of how a network can give priority to one message in a group of competing messages concerns the transfer of a primary data message. be. However, complex multiprocessor systems must utilize many other types of communications and commands in order to provide the efficiency and versatility currently required. The main functions that must be provided include, in addition to primary data transfer, what can broadly be called a multiprocessor mode, acknowledgment of messages, status indication, and control signals. There is. The following sections explain how the various modes and messages are used for sorting, communication, and sorting for prioritization.
It presents an overview of working with networks from a global perspective, ie from the perspective of a multiprocessor system. For a more detailed understanding, reference is made to FIGS. 8 and 13 and the description thereof below.

In the broadcast mode, messages are delivered simultaneously to all processors without specifying a particular receiving processor or processors. This mode is typically used for response, status coordination, command, and control functions, to name a few.

If the receiving processor needs to be specified,
Destination selection information contained within the message packet itself now provides criteria for determining whether to accept or reject the packet locally (at each individual processor). There is. For example, interface logic within a receiving processor module may, according to map information stored in high speed RAM 26, route the data in the packet to a range that is relevant to the particular processor in which the interface logic is embedded. Identify whether something is included or not. By setting the map bits in the high-speed RAM in different ways, the criteria for various selection schemes can be easily established, including, for example, the selection of a particular receive processor ("passing"), etc. by selecting a portion of a database stored in a logical process
There is a selection of types ("classes"), etc.

Using broadcast in conjunction with local access control (= access control performed on individual processors) is particularly beneficial for database management systems, which can be distributed over a wide area while requiring only a small amount of overhead software. distributed local copies of any part of a logical relational database or any of a plurality of globally known logical processes can be accessed. Therefore, this system is capable of specifying and selecting one destination processor to transfer a message to, and also specifying and selecting a plurality of resources belonging to one class. Level database reconciliation often requires cross-references between separate parts of the database and consistent references for a given task.

Transaction number (T
N) has various characteristics, among other things, it provides the identity and reference of such global transactions. A large number of tasks can be processed in parallel by local processor modules that operate asynchronously with each other, and each task or subtask has an appropriate TN. It is designed to have. TN and DSW (
By using various combinations of destination selection words) and commands, virtually unlimited flexibility is achieved. Extensive sort/merge operations are required for a large number of tasks whose allocation and processing are done asynchronously.
ion) can now be applied. T
N can be allocated and abandoned, and a merge operation can be started and stopped. some kind of message,
For example, a continuation message or the like can be given priority over transmission of other messages. The use of a TN and a local processor that updates the status for that TN allows a single query to determine the status of global resources for a given TH. Distributed updates can also be accomplished with a single communication. The system of the present invention has all the above functions.
This is done without extending the software or significantly increasing the overhead burden.

The result of using the present invention is that multiprocessor systems with a number of microprocessors far greater than those typically found in the prior art can operate very effectively on problem tasks. becomes possible. Today's low cost microprocessors make it possible to create systems that deliver high performance in problem areas, and not just ``low'' power. can do.

A consistent priority protocol that encompasses all message types and various subtypes is defined to encompass all of the different types of messages that are fed into the network. Although response messages, status messages, and control messages are different types of messages than primary data messages, they are similarly subject to network conflict/merge behavior (
content/merge operation
n) and thereby receive priority while being transferred. The response message in this system is an acknowledgment (ACK) or a negative acknowledgment (NAK).
or an indication that the processor does not have the resources to perform meaningful processing on the message (“not appli”).
cable processor) J-NAP
). NAK response indicates lock (1ock) state,
error condition or overrun
) may be any of several different types indicating status 0 There may be only one or multiple source processors, but the source processor has finished sending the message. Response messages are given higher priority than primary data messages because such responses are required later.

The system also sends a 5ACK message (status acknowledged message: 5tatus acknowledged).
g-ment message) is used, and this 5
The ACK message indicates the readiness state of a local processor for a particular task or transaction.
readiness 5tate). The contents of this 5ACK response are updated locally (=in each processor, ie, in the local processor) and maintained in a state where it can be accessed from the network. These 5 ACK responses are combined with the network's merge operation to provide a single, consistent global status report for a given task or transaction. Status responses follow a priority protocol, so one
The response with the least data content among the responses for the two transaction numbers will receive priority for automatic fishing, thereby establishing the lowest readiness state as the global system state, which will be aborted. It is performed in one motion without any Furthermore, such a 5ACK indication may be used in conjunction with a primary message of a god, thereby setting various protocols, such as system initialization and lockout operations.

The priority protocols for the various message types are first defined in terms of command codes, which are the first command words that precede each message and response, as shown in Figure 11. 6 bits are used. This makes it possible to make a sufficient distinction between message types and subtypes, but it is also possible to make a more multi-level distinction.

As can be seen from FIG. 11, in this embodiment, the 5ACK responses are used to distinguish between seven different status levels (and also provide criteria for determining priority). ing.

In the case of a response message, after the above 6 bits, 1
A tag in the form of 0-bit 0PID follows (see Figure 3). Both TN and 0PID can serve as criteria for further sorting, since they have different data content inside the tag area.

After each primary message is transmitted over the network, all processor interfaces, even if it is a NAP, generate a response message. Those response messages also compete with each other on the network, whereby a single or common winning response message is broadcast to all processors. The lost message packets will be attempted to be synchronized again at a later time, but this retransmission will occur after a very short delay, thereby ensuring that the network is in virtually continuous use. . If multiple processors send ACK responses, the ACK responses will be sorted based on 0PID.

Using the present invention, the result is that starting, stopping, and controlling tasks, as well as interrogating tasks, can be performed by a very large number of physical processors, and with an overhead of only a few iX. This means that
The raw power of many processors
) can be used effectively to handle problem situations, because out of this low power, the system's coordination
) and the amount devoted to control can be extremely small.

Co-operation and control overhead constitute a fundamental constraint on the efficiency of any distributed processing system.

For purposes of global control (ie, network control), various types of control communications are used.

Therefore, "Stop Merge", "Request Status", and "
Messages for ``start merge'', messages for assigning a task, and messages for abandoning a task are in the same format as data messages, and therefore these messages are also treated as primary messages here.・We will call it Message.

Those control messages also contain TNs and are placed in their proper place in the priority protocol. This will be discussed later in Figure 10 and 1.
Let us explain with reference to Figure 1.

The term "global semaphore buffer system" was originally used because the high speed random access memory 26 and control logic 28 shown in FIG. This is due to the fact that it plays an important role in both two-way communication of instructions. This global semaphore buffer system provides access duality in that both the fast-running network structure 50 and the slower-running microprocessor can access the memory 26. messages, responses, controls, or status indications within the microprocessor can be viewed without delay and without the need for direct communication between the network and the microprocessor. To accomplish this, control logic 28 connects memory 26 to an
interleaved cycle
time multiplexing to the network 50 and the microprocessor, thereby creating separate ports that can commonly access memory 26. The same thing is happening. Global resources, ie, network 50 and multiple microprocessors, utilize the transaction number as an address locator to locate the portion of memory 26 that is allocated to store the status of the transaction. be able to. At a local level (=level of an individual processor), the status of subtasks for a given transaction, including all kinds of available states, is updated within the memory 26 under the control of the microprocessor and the control A lock on the buffer system is provided by logic 28. By using one of seven different readiness states, entries can advantageously be retrieved from different dedicated portions of memory 26. Once an inquiry is received from the network, communication of processor status (i.e., a "semaphore") is performed.
is read), and a determination of priority is made in the network, with the least complete readiness state receiving priority. With the above configuration, a quick hardware response from all processors to one arrangement can be obtained. Therefore, it is possible to know without delay and without using software whether or not all of the distributed subtasks related to a given task have been completed. Furthermore, in this system, any of the communicating processor modules
Transaction number assignment allows transaction numbers to be used for use in messages or within each global semaphore buffer system. This is the action of assigning.

Preferred embodiments of the integrated use of transaction identity and status display include that each of the plurality of processors sends out all messages related to a given criterion in an orderly manner. There is a complex merge operation that requires .

In a prior art system, each processor would first receive and complete its own tasks, and then transfer the results to some kind of "master" that would perform the final merging operation. You will have to use a method of transferring it to the processor. Therefore, the master processor becomes a serious bottleneck to the efficiency of the system.

Once the global readiness state has established that all of the affected processors are in a ready state, the messages with the highest priority in the memory 26 provided in each processor are sent to the network at the same time as each other. and priority determinations are made for those messages during merging, as described above. Attempts are made to retransmit several groups of messages one after another, resulting in the messages being ordered from highest to lowest priority with respect to the transaction number, and finally the lowest priority message. A serial message sequence is generated as if something were coming. Depending on special command messages, the system is capable of stopping and restarting merge operations mid-way, so that multiple merge operations that are in the middle of execution at the same time can , a state in which this network 50 is shared can exist, thereby making it possible to use the resources of this system extremely effectively.

Therefore, at any time, this network 5
All of the active processors connected to 0 are enabled to perform operations on multiple messages related to various transaction numbers asynchronously with each other.

If a single status alignment references the same transaction number, ie, the "current" transaction number, all processors respond synchronously to each other with one of the available status levels. Let's do it.

For example, START MERGE
) J Message is a transaction
Test of global semaphore specified by number (=
If the global state resulting from this test is a "ready" state (i.e. "SEND READY" or "RECEIVE READY") current transaction number (pr
esent transaction number
: P T N ) is set equal to the value of TH transmitted in this "Merge Start" message. (If the global state obtained as a result of the test is not the "ready" state, the value of PTN is rTNo (which means that the transaction number (TN) is "o"). value).

Furthermore, the "STOP MERGE" J message also resets the current transaction number to "0". In this way, rTNOJ sends messages (
It is used as the ``default'' value transaction number used for point-to-point messages. In other words, this rT
By NOJ, “non-merge”
) J mode operation is specified.

This global intercommunication system includes those shown in FIGS. 3A, 3B, 3C, and 11 for the message configuration and FIG. 8 for the high speed random access memory 26 configuration. and those shown in FIG. 10 are adopted. A more detailed explanation will be given later in the fifth section.
This will be done in conjunction with FIGS. 7, 9, and 13.

As can be seen from Figures 3A to 3C and Figure 11, the command codes used for responses range from Oo to 0F (hexadecimal), and the command codes used for primary messages are 10 (16 (base numbers) to larger values. Therefore, the response is given priority over the primary message, and in the sorting order shown in FIG. 11, the smallest value comes first.

One dedicated storage area (the area written as "transaction number" in the figure) inside the high-speed RAM memory 26'' (Figure 8) stores data in the word format of Figure 12 (the seven types of readiness described above). TN status, TN assigned status, and TN unassigned status). .

Among other dedicated portions of this memory 26'' are a circular buffer for input (received messages) and a storage space for output messages. A separate area is used as the message completion vector area, which allows a pointer to be placed on the output message that has been sent, thereby making efficient use of the output message storage space. It has become.

As understood from the above, regarding the memory 2 days and the control logic 28, their queuing
ng ) functions and data buffering functions are certainly important, but with them comes the unique importance of multiple collaborative operations in which global transactions are distributed and processed with respect to individual processors. ing.

(Active Logic Node) In both of the two networks arranged with redundancy, the plurality of active logic nodes 54 in FIG. 1 have the same configuration as each other, with the exception of the following: Only the direction reversal node 54 at the top of each network does not have an upstream port; instead,
A simple signal direction reversal path is provided for direction reversal in the downstream direction. As shown in FIG.
can be broadly divided into two groups based on functionality. One of these functional groups is concerned with the transmission of messages as well as collision signals (collision numbers), the other with the generation and retransmission of common lock signals. The clock signals are synchronized such that there is no skew between the respective clock signals at different nodes, ie, zero skew. The above two functional groups are not independent of each other, and the reason is that zero and
This is because skew clock circuits form an important part of signal transmission systems. Both a word clock (consisting of two serial bytes) and a byte clock are used. It is noted here that, both when setting or resetting the state of this active logic node 54 and when setting different modes of operation,
No external control of this active logic node 54 is required, and no such control is actually provided. Furthermore, because each node 54 is of identical construction to each other, it is possible to mass-produce the nodes using modern IC technology, thereby reducing significant cost while improving reliability. It is possible to achieve a reduction in

Each of the A, B and C "ports" mentioned above each have 10 input data lines and 10 output data lines.

For example, in the A port, the input line is represented by AI and the output line is represented by AO. For each port,
Along with an upstream clock line and a downstream clock line, there is one "collision" line (i.e.
line) is used (for example, the A port has an Aco line).
l is used). The data lines of each of the A and B ports are connected to a multiplexer 60 which selects which of the two conflicting words has priority, or if the conflicting words are identical to each other. ) that common word,
As the data signal CO, it is switched and connected to the up register 62 connected to the upstream port <C port). At the same time, downstream data sent from a higher hierarchy node and received at the C port is shifted into the down register 64 and shifted out from there to the A and B ports. occurs as output in both.

One of the serial upstream streams of bytes may be blocked, however, without any additional upstream or downstream delay, and the words may be blocked. UP register 62 and DOWN register in a continuous line under the control of the word clock and byte clock.

It will proceed through 64.

The mutually conflicting bytes supplied simultaneously to the A and B ports are detected by the first and second parity detectors 66.
．． 67 and also to a comparator 70, which prioritizes the data content based on the eight data bits and one control bit in such a way that the data content with the lowest value gets priority. Determine rights. In this priority determination protocol, the ``idle'' signal, ie, the signal when no message is present, is an uninterrupted string of ``1''s. Parity error is
This can occur due to typical causes such as the presence of excessive noise, or any other factor that affects signal transmission or circuit operation. However, in the system of this embodiment, the parity error indication is also used for another important purpose. That is, each time a microprocessor transitions to an inoperable state, the transition is marked;
This is done by causing all output lines, including the parity line, to go high (ie, their value is ``1''), thereby causing an odd parity error condition. This parity error display indicates that if one error occurs, the network
marker J, which allows the system to identify that a change has occurred in a global resource and to initiate a procedure to determine what that change is. It has become.

A pair of parity detectors 66,67 and a comparator 70 provide signals to a control circuit 72 which includes a priority message switching circuit 74 and which also performs priority determination. If so, the multiplexer 60 is configured to lock into one of two states in response to the output of the comparator 70, and further configured to generate and propagate a collision signal in the downstream direction. It is configured. The transitional parity error propagation circuit 76 is so named because it forces into the network the previously described parity error condition in which all lines are ``1'' at the same time. The reset circuit 78 is for returning this node to its initial state, and sends an end conflict message (end conflict message).
of message (EOM) detector 80.

In order to perform the functions described above, as well as those described below, a microprocessor chip may be used in each active logic node to perform those functions. However, by having those functions performed according to the state diagram of FIG. 5 and the logical expressions described below, they can be performed more easily. In the state diagram of FIG. 5, state SO represents an idle state, and also a state in which conflicting messages are the same and a decision has not been made to give priority to one port over the other port. It represents. S1 state and S
The two states are a state where the A port is given priority and a state where the B port is given priority, respectively. Therefore, if the data content of Bl is larger than the data content of AI and there is no parity error in AI, or if there is a parity error in BI (if there is a parity error in these AIs), The condition that there is no parity error and the condition that there is a parity error in Bl are, respectively.
(denoted AlPE and BIPE and represented by the state of the flip-flops) have priority over the A port.

Logical state (logical condition) opposite to the above regarding AI and BI
exists as a state (condition) that this device should move 8 lines to the 52 state. From a node in a higher hierarchy,
If an indication that a collision has occurred at that level is issued, that indication is included in the downstream signal and C
It is sent back as 0LIN. The device transitions to the S3 state wherever it is in the SO, S1, and S2 states, and sends this collision signal downstream to A col and B c
Transfer as al. When in the S1 state or S2 state, this node has already made a decision, so
In a similar manner, a collision signal is sent downstream to (two) nodes in a lower hierarchy, and at this time, the priority message switching circuit 74 is locked to port A or port B depending on the situation. ing.

Reset circuit 78 includes an EOM detector 80, which is used to reset the node from S3 to SO (FIG. 5).

The first reset mode utilizes the End of Message (EOM) field, which terminates the data field in the primary message, as shown in FIG.

Using a group of flip-flops and gates, the following logic state is created:

URINC-IJRC-URCDLY where tJRc represents the control bit in the up register, URfNC represents the value of the control bit in the input signal input to this up register, and
RCD_LY represents the C value (=value of control bit) in the up register delay flip-flop.

As shown in Figure 6, a bit pair (bit bear), which is a set of two consecutive bits in a string of control bits, specifies a certain type of field and also This is to make the transition to the field explicit. For example, from the control bit state followed by only "1" used during idle, the bit sequence (=bit pair) of "Oll". This sequence of "0.1" is used to identify the start of a data field. A string of control bits of "1.0" that follows this indicates an internal field or subfield, and also indicates an end of message (EOM).
) are identified by a control bit pair of "0.0". r
The condition in which a string of bit pairs 1, OJ is followed by a bit pair 10.0'' is unique and can be easily identified. The URINC signal, URC (No. 3, and υRCDLY signal) are ANDed together, and each of these signals is delayed by one byte clock from each other.The result of these ANDs is The resulting signal waveform is high until the message packet starts, turns low at this point, and remains low for the duration of this data (=message packet). .

This waveform returns to a high level two byte clocks after the ROM is generated. EOM is detected by this transition in which the waveform tJRINc-URC-tJRCDLY turns positive. As noted in FIG. 5, this positive transition triggers a return operation from Sl or S2 to SO.

When a higher hierarchy node is reset, it enters the C0LIN state, which indicates that the conflict condition has disappeared. This logic state initiates a return operation from S3 to the base state SO. What I would like V to live in is that this C0LIN state is such that the End of Message "runs through" the layers of the network 50 one after another.
As the situation progresses, it will propagate downward to those hierarchies. As described above, each node can reset itself regardless of the length of the message. Additionally, I would like to point out that regardless of the initial state of the network, all nodes will be reset to the SO state once Idle No. 13 is supplied.

Collision signals are routed back to multiple processor modules. The modules memorize this collision state information and return to sending idle sequences while the winning processor continues to send. There is. The processor is C0LIN to C0L
As soon as a transition to IN is detected, a new transmission can be started. Furthermore, in addition to this, the processor has 2
It is arranged that a new transmission can be started if the idle signal continues to be received for a period of N byte clocks, since this situation is also similar to the former situation. This is because it indicates that the previous transmission does not remain within this network. According to the latter of these schemes for enabling new transmissions, a processor joining the network for the first time can enter a message synchronization state with the network as long as the traffic is small; Participating processors do not have to wait for polls from other processors to initiate intercommunication with other processors on the network.

The parity error state, shown in the state diagram of FIG. 5, is set according to the following logical equation.

PE5IG-AlPE-AIPEDLY+
BIPE-BIPEDLY If the logic state of this PE5IG is true, the human power signal U R to the UP register
I N Ha, (URIN O...URIN 7, C%
p=i...1.1.1). In order to satisfy the above logical formula, the transition parity error propagation circuit 76
For PE, i.e. eight-power parity error flip-flop and delay flip-flop (AIPEDLY)
Contains. The latter flip-flop is AIP
According to the setting state of H, the state is set one byte clock later. Therefore, when the flip-flop for AlPE is set due to a parity error, the PES I G value goes high for one byte clock, so this PES I The G signal is propagated only once at the first indication of a parity error. This same condition occurs when multiple data bits, control bits, and parity bits all have a value of ``1'', but the transition described above for the state of the global resource occurs. This is the state that occurs when As a result, all lines turn to high level,
A state of all 1's is forced and a total even state (odd parity state) is established, resulting in the AlPE flip-flop and AIPED
The LY flip-flop is set to indicate a parity error. The above arrangement operates in a similar manner if the message bucket received at the B port contains a forced parity indication to indicate a parity error or change in status.

Parity errors caused by noise effects and other variables usually do not affect processor operation because of the use of a redundant dual network. It is. For monitoring and maintenance purposes, an indicator light (not shown) is used to indicate the occurrence of a parity error. However, for a one-time propagating parity error that indicates a change in status, it initiates a routine to evaluate the significance of the change.

The clocking system used in this node 54, as shown in FIG. ) is zero, that is, to maintain a zero-no-queue state. Clock circuit 86 includes first and second exclusive OR gates 8
8.89, and the outputs of those exclusive OR gates, denoted A and B, respectively, are such that a subtraction (i.e., an operation of rB-AJ) is performed between them by an adder circuit 92. The output of the summing circuit 92 controls the phase of the output from a phase locked loop oscillator (PLO) 96 after being passed through a low pass filter 94. First exclusive OR gate 88
The human power for the PLO 96 is the output of the PLO 96 and a downstream clock supplied from an adjacent node element of a higher hierarchy via an isolated drive circuit 97. This clock line is labeled "Word Clock," and this word clock is obtained after a known delay from an adjacent higher hierarchy, and this same clock signal is no longer available. It is returned via one isolated drive circuit 98 to that node in an adjacent higher hierarchy. Power to the second exclusive-OR gate 89 consists of this word clock and clock feedback from an adjacent lower hierarchy, which also receives signals from this PLO 96. .

The above word clock line is connected to the third exclusive OR
It is connected to two inputs of the gate 100, both of whose inputs are connected directly and via a τC delay line 101. This provides a byte clock signal that has twice the frequency of the word clock and is timed with respect to the word clock.

The operation of the clock circuit 86 described above can be better understood by referring to the timing diagram of FIG. The clock out signal (clock output signal) is the PLO9
This is the output of 6. Naturally, since the primary goal of this clocking system is to maintain zero time skew between the clock output signals for all nodes in the network,
The clock output signals must also have the same nominal frequency. The delay due to the transmission line between nodes is set to be approximately constant, but
The value of this delay itself can also be set to a long time. If the method disclosed herein is adopted, the byte clock speed of the network and nodes will be set to the speed adopted in the actual system (nominally 120 ns
), it can be as long as 28 feet (8.53 m). As will be readily understood by those skilled in the art, networks that are not packed with the maximum possible number of processor modules at the same time can be built with additional layers that are integer multiples of this 28-foot length. can be easily obtained. In that case, the latency, ie the transmission time of the transmission carried out over the network, increases correspondingly.

As shown by the waveform immediately below the clock out signal in Figure 7, the word clock derived from an adjacent higher hierarchy has a similar waveform to the clock out signal, except that Only late. Although this word clock forms the fundamental timing reference common to all nodes, it is possible to do so by controlling the leading edge of each clock out signal internally within the circuit. , and by leading their leading edges to the word clock, all nodes can be kept in sync. As can be seen with reference to waveforms A and B, pulse A generated by the first OR gate 88 ends at the leading edge of the word clock, while the second
Pulse B generated by OR gate 89 has its leading edge coincident with the leading edge of the word clock. The trailing edge of this B-pulse is positioned at the start of the feedback pulse from the adjacent lower hierarchy module, and this feedback pulse is delayed by a certain amount, so that the B-pulse remains constant in duration. It becomes. The clock circuit 86 acts to keep the duration of pulse A the same as the duration of pulse B, but the reason it does so is to advance the phase of PLO 9B so that synchronization is established. As the output signal of the adder circuit 92 (subtraction r
This is because the signal after B-AJ approaches zero. In practice, adjustments are made to the leading edge of the A signal, which may lead or lag the preferred position, as shown by the dashed line, so that the leading edge of the A signal It should be placed in a position that precedes the leading edge of the clock by the amount of time. Once the leading edge of the clock out signal is in this preferred nominal position at all nodes,
There is a zero skew condition between the word clocks, so each processor connected to the network is free from constraints on the total length of the path from one processor to another. However, this is due to the fact that delays do not accumulate and that there is no difference in propagation time.

To generate a double frequency byte clock, a word signal delayed by a delay time τC is provided by delay line 101.
The clock is duplicated and this delay line 101 also feeds the gate 100. Therefore, as can be seen from the waveform labeled Byte Clock in Figure 7, both the leading and trailing edges of the word clock have a duration τ
A byte clock pulse with C is generated. This pulse occurs twice during each word clock interval, and occurs synchronously with the word clock at all nodes. In the above description, the delay introduced by the transmission lines between nodes is almost the same regardless of the direction of transmission from layer to layer, so that virtually all delays in this system The obvious assumption is that the word clock as well as the byte clock are kept in a stable phase relationship with each other. Therefore, locally (=
A byte clock (generated internally in each node) provides the clocking function for each byte of a 2-byte word of a message in each node. are doing.

These active logic nodes have potential advantages whenever they are intended to resolve conflicts between simultaneously transmitted message packets based on their data content. On the other hand, for example, 1
U.S. Patent No. 4251, issued February 17, 981.
No. 879 “Speed Independent Arbiter Switch for Digital Communication Networks (5peed Indep
endentArbiter 5w1tch for
Digital CommunicationNbiw
The majority of known systems, including those shown in J. Orks), aim to determine which signal was received first in time, and rely on external processing. circuit or control circuit.

Processor Modules The individual processors illustrated in the overall system schematic of FIG. 1 are interface processors (IFPs) 14 and 16, and access module processors (AMPs) 18- 23, and these processors are broadly subdivided into several major elements. A more detailed example of the configuration of these processor modules (IFP and AMP) will correspond to, but is not limited to, the general functional subdivision of FIG. , which also represents a number of further subdivisions.

As used herein, the term "processor module" refers to the entire assembly illustrated in FIG. 8, which includes the optional elements described below. , IFP or AMP. Additionally, the term "microprocessor system" refers to a system 1 that includes a microprocessor 105.
03, where microprocessor 10
5 is, for example, an Intel 8086 type (Intel 80
86) 16-bit microprocessor, etc. The address bus and data bus of microprocessor 105 are connected within microprocessor system 103 to general peripheral systems, such as main RAM 107, and to peripheral controller 109. Peripheral controller 109 is shown as an example of one that may be used when the processor module is an AMP and the peripheral is disk drive 111. On the other hand, if the processor module were to function as an IFP, the controller or interface could be replaced by, for example, a channel interface, as shown in the dashed rectangle. The IFP in such an embodiment would be responsible for communicating with a host system channel or bus.

Since microprocessor system 103 can use conventional 111J controllers and interfaces, there is no need to describe them in further detail.

It should be noted that using one disk drive per microprocessor can prove advantageous in both cost and performance. Although such an approach is advantageous in general for databases, it is sometimes useful to configure microprocessors so that a single microprocessor can access multiple secondary storage devices. may be beneficial. In the schematic diagram, other commonly used subsystems are not shown to simplify the diagram.

This omitted subsystem is, for example, an interrupt controller, which is supplied by semiconductor manufacturers for use in combination with their own systems. Those skilled in the art will also appreciate the importance of taking appropriate measures to provide power to the processor module to maximize the redundancy and reliability that the present invention can provide. be understood.

Peripheral controller 109 and channel interface, shown as optional elements in microprocessor system 103, correspond to the IFP interface and disk controller in FIG. On the other hand, the high-speed RAM 26 shown in FIG.
S, RAM26'', each of which is
By time multiplexing,
From a functional point of view, it is effectively a 3-port device, and one of its ports (the port marked "C" in the diagram) connects to the microprocessor's bus system. It is connected. H, S, RAM26'
. (not shown), communication is performed through the human power (receiving) port A and the output (transmitting) port B. In this way, the two systems have redundancy with each other. , second network, interface 120
It is only necessary to explain in detail the second H, S, and RAM 26'. Network interface 120.1
The 20 degrees are shown and explained in more detail in connection with FIG. 13, but they can be broadly subdivided into four main parts:

A human power register array/control circuit connecting ten human power lines from the second network 50b to the A port of the H, S, RAM 26'' via an interface data bus as well as an interface address bus. 122° An output register connecting the output line to the second network 50b to the interface data bus and the interface address bus and to the B port of the second H, S, RAM 26''. From the microprocessor bus interface/control circuit 126° network connected to the array/control circuit 124° interface address bus and interface data bus and to the A and B ports of the H, S, RAM 26” Receive the word clock and
A clock generation circuit 128° that generates a plurality of clocks synchronous with each other and in proper phase relationship for controlling the interface 120° and the second network interface 120°;
S, RAM 26'' cooperates with the microprocessor system 103 to coordinate data transfer between a network operating at high speed and a processor operating at a slower speed in comparison; It also performs the function of queuing messages exchanged between these different systems (= network system and processor system). It can be said that this microprocessor system (at least if it is an Intel 8086
type)) has the ability to directly write data to the H, S, RAM 26'' and the ability to receive data from the H, S, RAM 26''.

The structure of IFP and the structure of AMP are similar to each other in terms of their functions, however, H, S,
Regarding the size of the input message storage area and the size of the output message storage area inside the RAM 26,
There may be considerable differences between P and AMP.

In relational database systems,
The IFP uses the H,S,
RAM 26" has a large manual message storage space for receiving new messages from the high-speed network. The opposite is true for AMP, which stores processed messages sent to the high-speed network. This is because more storage space must be available for packets.H
2S, RAM26” is microprocessor system 1
It also operates in conjunction with main RAM 107 in 03, which contains message buffer sections for each network.

The manner in which the system address space within main RAM 107 is allocated for microprocessor system 103 is illustrated in FIG. 9 and will be briefly described. - addresses assigned to the system random access function and the I10 address space in accordance with a numerical scheme, leaving space for expansion to be used if the storage capacity for random access is increased; , ROM, and address space allocated for the functions of FROM (including EPROM). Furthermore, some portions of the system address space are allocated to the first and second high speed RAMs 26°, 2, respectively.
6" and for those message packets sent to high-speed RAM. This provides great flexibility in the operation of the system; This is because even if the main RAM 105 can address the H, S, RAM 26'', the function of the main RAM 107 allows the main RAM 107 to be hardly constrained by the interdependence between software and hardware.

Referring to Figure 8 again, as already mentioned, 2
H, S, RAM that can be accessed from two directions
26" is configured to perform core functions in controlling multiprocessor modes, distributed updates, and managing the flow of message packets. To achieve these and further objectives For, H, S, R
AM26" is partitioned into a number of different internal sectors. The relative placement of the various sectors shown in FIG. The specific addresses specifying the boundaries of these sectors are the addresses actually used in a certain system.Please note that: The size of these memory sectors and their relative placement can vary widely depending on the particular system circumstances; the illustrated example employs 16-bit memory words.

The selection map and response directory are dedicated lookup tables of the kind that only need to be written once during initialization, whereas the transaction number section is dynamically revisable. It provides a lookup table (which allows you to change its contents as many times as you like).

Although the selection map memory section starts at location 0, in this example there are essentially four different maps being used within this memory section, and those maps are interoperable. It is used in methods related to. The destination selection word (dest) included in the message packet
ination selection word: D
S W ) is used in conjunction with a dedicated selection map in the H,S, RAM 26''. This destination selection word consists of a total of 16 bits, of which 12 bit positions are It contains a map address that occupies 4 bits and map selection data that occupies the other 4 bits.
024 16-bit memory words, each containing four map address values. A single memory access to H, S, RAM according to the address value specified in the DSW provides the map bits for all four maps, while
A map selection bit included in SW determines which map is to be used.

FIG. 15 shows the conceptual structure of the map section described above, and in the figure, each map is illustrated as if it were composed of physically separate 4096x1-bit RAMs. ing. Taking into account the convenience of implementation, as shown in Figure 8,
It is convenient to have all map data stored in a single portion of H,S,RAM. A DSW management section 190 (FIG. 13) performs multiplexing operations on the four bits from each of the four maps of FIG. 15 derived from one 16-bit word of H, S, RAM. It's in control. As will be appreciated by those skilled in the art, the advantage of this scheme is that it allows the processor to initialize the map using the same means used to access other parts of the H,S, RAM. be.

Furthermore, three different classes of destination selection words are used, and correspondingly the storage locations of the selection map are divided into a hash selection portion, a class selection portion, and a destination processor identification information.
on processor identity
on:DPID) is divided into selected parts. This DP
The ID specifies whether the processor 105 is the specific processor to which the message packet is intended. In contrast, the class selection part indicates whether the processor in question is one of a plurality of processors belonging to a particular processing class that should receive the message packet, i.e., is a member of the processor group. It clearly indicates whether or not. The hash value is stored according to the distribution method used when the database is distributed within the relational database system. This also follows the distributed storage method. The hash value in this specific example is that when specifying a processor, the processor can be specified as having either primary responsibility or backup responsibility for the data. ing. Therefore, with the above multiple selection maps, H, S,
RAM 26'' can be directly addressed to determine whether the processor is the destination for the transfer. It is a complementary feature that complements the broadcasting method, and it also allows local access to the status of the microprocessor 105 without interrupting.

One section of the RAM 26, independent of the rest, serves as a central means for checking and controlling globally distributed activities. As mentioned and as shown in FIG. 3, each of the various operations sent to and received from network 50b is assigned a transaction number (TN). ing. TN is included in the message because
This is to provide a global transaction identity (transaction identification information) when each processor system 103 independently executes subtasks accepted by itself. A dedicated block in the RAM 26 for storing the addresses of multiple available transaction numbers is used by the microprocessor system +03 in executing those subtasks.
It contains status entries (=status descriptions) that are locally controlled and updated by the . TNs are used in a variety of different applications, both locally and globally, when intercommunication functions are performed.

Transaction numbers are used to identify subtasks, call data, issue commands, control message flow, and identify the type of global processing dynamics. Transaction numbers can be assigned, relinquished, or changed during the execution of global communications. These features will be explained in more detail in the following description.

The most complex, but perhaps most effective, feature of TH is that, by working with a sorting network, local processors (= Its ability to enable distributed updates of the status of individual processor modules). Each control process (i.e. task or multiprocessor activity)
has its own TN.

The value of the readiness state (the state in which the processor is ready for what kind of operation) is H4S, RAM26
”, and this readiness state value is changed locally (-within an individual processor module) under the control of the microprocessor system 103. Microprocessor system 103 selects the appropriate entry (e.g., 5A) in the response directory of FIG.
cK/Busy) (address is r050D (hexadecimal)
of this S ACK/Busy status by transferring the image as it was replicated.
H, S, input to RAM 26'. The entry manually entered at a certain TN address (= storage location corresponding to the transaction number) is H, S, A of RAM 26".
It is accessible from network 50b via the port and B port and via interface 120'. The timing is based on the status
This is done using a "status request" message that includes a request (status request) command code (see FIG. 11) and a TN. Interface 12
0° refers to the response directory containing the response message written in the appropriate format using the contents stored at the TN address of the specified TN. A second global status query for a given T, N
network interface 120', it elicits a direct response that is only under hardware control. No preemptive communication is required and the microprocessor system 103 is not interrupted or otherwise affected.

However, if the status is set by transferring the ``1ock'' indication to the interface 120, the microprocessor
System 103 disables interrupts and interface 120° continues to communicate the lock word obtained from address r0501 (hex) until its removal occurs at a later time.

The word format for the readiness state is from "busy: it1 work in progress" to "busy" in Figure 12.
Seven types of states are shown up to 1 initial (initial state), and FIG. 12 illustrates a useful specific example employed in an actual system. It is possible to change the readiness state into more types or fewer types, but by using the seven types of states shown in the figure, it is suitable for many uses. Extensive control can be exercised. The status level of each individual TN in the ``H, S, RAM 26'' (= one novel of readiness status represented by the entry stored in the individual TN address) is
It is the responsibility of the microprocessor system to continually update 7 to reflect the availability of subtasks and the progress of subtask processing. Such an update is performed using the format shown in FIG.
By writing N 'J' address 1ζ,
It can be easily executed.

In Figure 10, each status response (state response)
For all numbers from "05" to rODJ (hexadecimal), the first part is the status acknowledge command code (statusacknowle).
dgment command code: SA
CK). Those 5ACK responses sent to the network actually consist of the command code in Figure 10, the numeric part of the word format 1- in Figure 12, and the originating processor 10 (OPID). This is shown in FIG. 11. Therefore, those 5 ACK responses are the 11th
Within the comprehensive priority order convention shown in the figure, a group of (summer order rankings) is formed.

The reason why 0PID has meaning in terms of priority conventions is that, for example, if you are working on a single TN with multiple brokers →), but none of them are in the "busy" state, then 0PID11 with a 6- priority message judgment:! This is because it will be carried out accordingly. Transfers and system co-operation also use this data (OPID).
Each row ′) can be created based on .

Priority conventions are defined for SACK messages (=SACK responses), responses are sent simultaneously from multiple microprocessor systems 103, and dynamic ( = Priority determination is made while the transmission is in progress).
Determining the status of global resources for a given task is now performed in a greatly improved manner. The resulting response is structural, never exhibits unspecified conditions, and, furthermore, does not require any software and is locally sourced (=individual processor 1,000 joules). There's no need to waste your time. Thus, for example, deadlocks are never caused by frequent status requests that prevent the execution of a task. At various status levels, 60-cal processors can continue to operate independently of each other, with many optional operations available for multi-bromo processors, and yet a single query can It has never happened before that two answers have been drawn, ``Target/Male, give priority.''

It may be helpful to explain the series of conditions shown in FIG. 12 in some detail here. "
``Busy'' and ``waiting'' states are states in which an assigned or delegated subtask is in a state of deafness and waiting as it progresses to a progressively more complete stage. ” state represents a state in which further communication or event is required. These 1 Bizui” and “
The "Waiting" state is a state in which the TN's status is higher and rises to Nov. This is an example.

On the other hand, when transmitting or receiving message packets, the ability of the rN in message control, which is another feature of the TN, is demonstrated. When the microprocessor system 103 has a message to send, the status display changes to ``sendready''. In addition to updating the status display, the microprocessor system 103 Then, using the word format shown in Figure 12, set the value of “Next Message Vector” to H3,RA.
This manually entered entry specifies from which location in the H, S, or RAM 26" the corresponding output message should be retrieved. This vector connects multiple output messages related to a particular TN into one tree (= chain
) for network interface 1
It is used internally in 20°.

Functions related to the above functions are
eive ready ) is executed during the J state.

In this "ready to receive" state, the microprocessor is stored at the TH storage location (=TN address).
A manual message count value obtained from system 103 is maintained, the input message count value being a value related to the number of messages that can be received in association with a given TN. . This count value is decremented as the manual messages are transferred one after another, and may eventually reach zero. Once it reaches zero, no more messages can be received and an overrun condition will be displayed. As described above, the speed of transmission between the network 50b and the microprocessor system 103 can be adjusted using the TN.

To explain the local (=individual processor) aspect, while processing is being executed in an individual processor, TN is a constant and unchanging standard that applies throughout the system in transmitted messages and received messages. is maintained as. The rTNOJ state, the default state, also serves as a local command to indicate the fact that the message should be used in non-merge mode.

To explain from a more global perspective, rTNOJ and rT
By distinguishing various values where N>OJ as having different properties, one command function among a plurality of command functions using TN is defined. In other words, by distinguishing TNs in this way, a characteristic description (characterization) representing either "merging" or "non-merging" can be applied to each message.
This provides a powerful system operating method for prioritizing and sorting multiple messages. Similarly, "Assigned F (Assigned+assigned state)" and "Unassigned (Una
ss igned: unassigned state)
, “Non-Part, 1cipa
nt ) J and the status "initial" are used to perform global intercommunication and control functions. The "unassigned" state is a state where the processor previously abandoned the TN, and therefore it is a state where it is necessary to receive a new primary message that reactivates the TN. If the status display should be "assigned" and the processor is
If the message "Unassigned" is displayed, this indicates that the TN was not entered properly and corrective action must be taken. If T
If N is ``assigned'' when it should be ``unassigned,'' this means either an incomplete transfer is occurring or there is contention between two processors for a new TN. It may be an expression of what is being done. Both "assigned" and "unassigned" are not treated as readiness states, and the reason is that at the stage when they are displayed,
This is because the processor has not yet started working on the TH.

Furthermore, the "initial" state and the "non-participating processor" state are also important in terms of global resources.

A processor that is about to come online, that is, a processor that must go through the process of joining the system, is in an "initial" state, which means that administrative steps must be taken to bring it online. This indicates that you need to step on the A processor in the "uninvolved processor" state with respect to a given task does not need to perform any processing locally; however, by tracking and monitoring this TN, it is possible to prevent this TN from being inadvertently used inappropriately. It is necessary to make sure that this does not happen.

Referring again to FIG. 10, H, S, RAM26
In addition to the types described above, the dedicated directory or reference section of `` also contains a number of other types of messages, given priority, that are used to generate responses in hardware. .NA
The entry (not assigned) is prepared for future use and is maintained in a usable state. The three different types of NAKIZ responses (Overrun, TN Error Locked NAK responses) have the lowest data content and therefore the highest priority; This is because the NAK response indicates an error condition. A plurality of 5 ACK responses are followed by ACK responses, followed by NAP responses (non-applicable processor responses), and the 5 ACK responses are arranged in descending order of priority. In the configuration of this specific example, two response command codes are not assigned a function (that is, they are set to NA) and are kept available for future use. The directories described above can be initialized by software and utilized by hardware, allowing for rapid and flexible generation of any of a wide variety of response message texts. Can be done.

Use one independent part of the above directories that is independent of the other parts to perform TOP, GET, P
The respective addresses of UT, as well as BOTTOM, ie a pointer to the function of the circular buffer for manual messages and a pointer to the completed output message, are stored therein. These pointers are used to manage input messages and output messages, respectively.
, S, and dedicated sectors of the RAM 25''. A circular buffer scheme is used for input messages; in this case, H, S,
, rTo PJ stored in the directory section of RAM 26'' is a variable address that specifies the upper limit address position for manual messages.The PUT address stored for each signer in the same directory section is as follows. This designates the address location where the circuit should store the message received.

The GET address is set and continually updated by the software so that the hardware knows the address location where the software is blanking the buffer.

Manual message buffer management is done by setting PUT to the bottom address of the buffer and starting with the GET address equal to TOP. The operational rule established by the software is that GET must not be set equal to PUT;
If so set, an ambiguous condition will occur. When an input message is input into the input message buffer in RAM 26, the message length value contained within the message itself determines the starting point of the next input message. , then a change is made to the PUT address stored in the directory to indicate the storage location in the buffer that should accept the next manually incoming message. 103
are capable of retrieving messages manually when their own work capacity allows.

The data stored in the output message storage space in the H,S, RAM 26'' includes the output message completion vector, which is held inside a circular buffer independent of other parts, as well as the output message storage space in the H,S, RAM 26''. Cannot be used with Next Message Vector. Individual messages can be edited (assembled) and stored at any location, and multiple messages that are related to each other can be chained together to send them over the network. It is now possible to do so. H,S.

In the RAM26° directory section, TOP
, BOTTOM, PUT, and GET are manually populated and updated as previously described, thereby maintaining a dynamic current indication of their location in the output message completion buffer. The message completion vector is an index address that points to a message that is stored in the output message storage space and that has already been properly transferred as indicated by the received response. It consists of As will be explained later, this system facilitates the input of output messages to microprocessor system 103 while allowing microprocessor system 103 to process complex concatenated vector sequences in an orderly manner. This ensures that output message storage space is used efficiently and that message chains can be forwarded.

The protocol of FIG. 11 described above in connection with the response is as follows:
Following the response, a primary message is also specified. A plurality of types of response messages are arranged one after the other, and the hexadecimal command codes are illustrated in ascending order. Among the group of primary messages, the merge stop message (this message is also a non-merge control message, which is a basic control message) has the smallest data content.
Therefore it is of the highest priority. This message constitutes a control communication that terminates the merge mode in the network as well as in the processor module.

A large number of different types of primary data messages are available with ascending priorities, and they can be assigned priorities based on application and system requirements. You can add classification. As mentioned earlier, a continuation message that follows another message is given a high priority to ensure continuity from its predecessor message bucket 1. t).

The bottom group in Figure 11, consisting of four types of primary messages, from highest to lowest priority, is the only type of status message that requires a status response. and a respective control message requesting a status request message ``rTN relinquishment'' and an rTN allocation J, and
Furthermore, it includes priority level 11 (merge start) control menu.

The above configuration enables operations that can be used for many purposes, as will be clear from more detailed examples described later. The processor module has a current transaction number (presenttransaction).
n number : P T N ), and in this case, even if the PTN is externally specified by the network, the continuous operation The same is true even if it is generated internally during execution. When a merge operation is being performed, the processor
A module executes its operations using a global reference, that is, a transaction identity (=information for identifying a transaction), and this transaction identity is defined by the TN. Starting, stopping, and restarting a merge operation is accomplished using simple message changes. When a subtask does not need to merge messages, or when message packets are generated that have no particular relationship with other messages, these messages are output to rTNOJ. are arranged in a queue, and the transfer is performed while the basic or default state (0) currently defined by the transaction number remains true. This rTNOJ state allows messages to be queued for forwarding when merge mode is not used.

(Network Interface System) Reference will now be made to FIG. 13, which shows in more detail one specific example of an interface circuit suitable for use in the system of the present invention. This “network”
The description in the "Interface System" chapter contains a number of detailed features that are not necessarily necessary to understand the invention, but which are incorporated into the actual system. , therefore, it has been included in the description to clarify the position of various specific examples with respect to the gist of the invention. Regarding specific configurations and detailed structures for gating, which are not the subject matter of the present invention and are related to well-known means, a wide variety of alternative configurations can be adopted, so explanations will be omitted. Or I decided to simplify it. FIG. 13 shows the second network interface 1 shown in FIG.
20°, H, S, and RAM 26''.2
12 interfaces for each network
0,120° function in a similar manner to each other, so it is sufficient to discuss only one.

In FIG. 13A, power from the active logic network 50 connected to the interface shown is provided to the network message management circuit 140 via a parity check circuit 144, such as a multiplexer 142. ing. multiplexer 142
is further connected to a data bus of the microprocessor system, thereby allowing access to message management circuitry 140 via the data bus. This feature allows the microprocessor system to operate the interface in step-by-step test mode, and to test the interface as if it were connected online to the network. Data transfer is performed in this way. Input from the network is provided to the receive network data register 146 via the byte data input directly to the first section of the register 146 and the receive byte buffer 148. There is byte data manually input to this register 146, and the pie for receiver 3! - Buffer 148 inputs its byte data into another section of this register 146 after the first input of the byte data into the first section. This causes both of the two bytes that make up each received word to be input to the receiving network data register 146, where:
It will remain available.

The output message to be transmitted is input to a transmitting network data register 150, and a parity bit is added within a conventional parity generation circuit 132. Messages are sent from the network message line 140 to a network connected to it, or (if test mode is used) to the microprocessor system.
Sent onto the data bus. For the purpose of message management within this interface, the format of transmitted messages stored in random access memory 168 is intended to include identification data as well as message data. As can be seen in Figure 21A, commands, tags, keys, and DSWs can all be combined with the primary data transmitted from the scare.

The configuration shown in FIG. 13A is essentially the same as the configuration shown in FIG. 8, except that in FIG. The microprocessor system 103's address bus and data bus are shown connected to an independent C port. However, in reality, the 13th A
As can be seen from the figure, such mutually independent access from two directions is achieved by time-division multiplexing of the manual address function and the output address function in the H, S, RAM 26'', which is performed inside this interface. The data bus and address bus of the microprocessor are connected to gates 145 and 14, respectively.
9 to the respective buses of the interface, thereby allowing the microprocessor to operate asynchronously and based on its own internal clock.

The timing scheme employed is based on clock pulses, phase control waveforms, and phase subdivision waveforms, which are generated by interface clock circuit 156 (FIG. 13). , and has the timing relationship shown in FIG. 14 (FIG. 14 will also be explained later). Interface clock circuit 156 receives the network word clock from the nearest node, and phase lock clock source 157 provides zero time skew as described above in connection with FIG. Contains means for maintaining.

The nominal network word clock rate in the network of 240 ns is subdivided in time within the interface clock circuit 156, which is done by a frequency multiplier (detailed ), but the duration is 40ns
A high-speed clock (PLCL in Figure 14) that determines the reference period of
(denoted as K). The basic word period is determined by the total period of 240n.
This is a periodic signal labeled CLKSRA in the figure that is inverted every half cycle at s. There are two other signals with the same frequency and duration as this CLKSRA, PLCL
These signals are generated at times delayed from CLKSRA by one and two PLCLK cycles, respectively, and are designated CLKSRB and CLKSRC, respectively. is given.

Based on the above various signals, the control logic 159
It generates timing waveforms (hereinafter also referred to as gate signals) called rI OGATEJ, rRECV GATEJ, and rsEND GATEJ.
These timing waveforms represent each successive third interval of the word period. These intervals are given appropriate names: "IO Phase", "Receive Phase", "Transmit Phase". These phases defined by the above gate signals are each further defined by the "■OCLKJ signal, rRECV CLKJ signal, and rsEND
The CLKJ signal is subdivided into two equal half-intervals, which define the second half of each phase. Byte clocking functionality is provided by rBYTE CTRLJ and rBYTE
CLK" signal.

During the above IO phase, RECV phase (reception phase), and 5END phase (transmission phase), the random access memory 168 and the microprocessor system bus are time-multiplexed (time multiplexing). ) in order to be able to perform the specified actions.
It provides the basics. The interface can only receive or transmit one word per word period to or from the high speed network, and obviously it never receives and transmits at the same time.

The transfer rate to and from the microprocessor system is considerably lower than the transfer rate to and from this network, but even if they were equal, it would be too much for the capabilities of the interface circuitry. It will not be a burden. The system configuration of this interface is such that most operations are performed by direct access to random access memory 168, so that little internal processing or software is required. It has become.

Thus, as the system cycles through successive phases within each word period, the words successively pass through each other without colliding with each other.
The words are routed along predetermined signal paths to perform various functions. For example, sending messages to the bus may occur in between receiving messages from the microprocessor, each of which may be performed in an alternating manner using different portions of memory 168. Can be done.

Intercommunication between the microprocessor system's data bus and the network interface is provided by a 10 management circuit 160 (this IO is referred to as read/write (Re)).
ad/Write)). A write gate 162 for gating words coming from the microprocessor system and a system read register 164 for sending words out to the microprocessor system connect the microprocessor bus and the bus to the network interface. -Connected to the interface.

Also included in the network interface subsystem are a memory address register 165 and a parity generator/check circuit 166. In this specific example, the high speed memory (=H, S: RAM) consists of 4 words x 17 bits random access memory 16
8, how this memory is internally repartitioned,
The usage of the plurality of dedicated memory areas provided inside this memory has already been described. The size (=capacity) of this random access memory can be easily reduced or expanded according to the needs of specific individual applications.

A receive message buffer management circuit 170 is connected to the microprocessor data bus and also to the memory 168 address bus. "Received messages"
The term J is sometimes used to refer to a message that comes in from the network and is manually input to a storage location called rPUTJ in a circular buffer; It is sometimes used to refer to the transfer of human-generated messages to a microprocessor. When this transfer to the microprocessor occurs, the value of rGETJ specifies from which location the system should perform successive retrieval operations in performing retrievals of received messages to be transferred to the microprocessor system. A plurality of address values used for accessing the random access memory 168 are stored in the GET register 172 and the TOP register 17.
4, PUT counter 175 and 8077M register 1
76 are manned by each of them. The PUT counter 175 is
It is updated by incrementing by one from the initial position specified by the 80770M register 176. TOP.

Register 174 provides an index of the other side boundary. Both the TOP and BOTTM values can be manipulated by software control, thereby adjusting the size of the receive message buffer and H,S.
, and the absolute storage location in RAM. Once the contents of the PUT register are equal to the contents of the TOP register, the PUT register is reset to equal the contents of the BOTTOM register, thereby allowing this buffer to be used as a circular buffer.

GET register, TOP register, BOTTO
M+/Register and PUT counter are human camera...
It is used to manage both the nosage circular buffer and the output message completion circular buffer.

Manual input to the GET register 172 is performed under software control, which determines the next address depending on the length of the message currently being handled in the buffer. It is from. GET register 172, PUT counter 175,
and comparator circuits 178 and 179 connected to the respective outputs of TOP resistor 174 are used to detect and indicate overrun conditions.
This condition occurs when the values of E and T and the value of PtJT are set to equal values, or when an attempt is made to set the value of GET to a value greater than the value of TOP. In either of these cases, an overrun status indication will be sent and will continue to be sent until the overrun condition is corrected.

This continuous method of configuring and operating the ``receive message'' circular buffer allows for mutual checking to avoid conflicts, which is a method particularly suited to this system. By rP
It is now possible to manage UTJ with hardware and dynamically manage rGETJ. However, it is also possible to employ other types of buffer systems. However, this would probably add some extra burden in terms of circuitry and software. Referring now to FIG. 218, the format of the received message stored within memory 168 further includes identification data in the form of a map result, data length, and -'C-length. ,
How these data are obtained will be explained later.

DSW management section 1 inside this interface
90 includes a destination selection word register 192, into which the destination selection word (
DSW) is input. Drying clothes using DSW 168
When addressing the dedicated DSW section of the memory 168, the output from this memory 168 on the data bus returns data based on which the DSW management section 19
0 can determine whether the message packet is destined for the processor in question. As can be seen from Figure 13A, the destination selection word is a map nibble (nyb) address of 2 bits], a map word address of 1 o beat, and a map word address for ma...lb selection. It consists of 4 bits.

Among these, "nibble" attono or memory 168
used to describe subsections of words from. Four bits for map selection are provided to map result comparators 194.\ and four comparators 194 are associated and receive the map result comparators 194 from memory 168 via multiplexers 196+. multiplexer 19
6 receives 16 bits of data, and these 16 bits 1- are the four different bits stored at the address specified by the 10 bits of the map word address contained in the DSW. represents a map data nibble. The memory 168 is configured in a manner that makes the dedicated map section particularly suitable for the comparisons to be made. A DSW is supplied to the multiplexer 196 for its control.
The remaining two bits in 2 select the corresponding one of the four map nibbles.

A comparison is made and the resulting map code is entered into the map result register 197 and inserted into the input message being entered into memory 168.

If, as a result of this comparison, it is found that the "!" bit does not exist in any of the selected maps, a "rejection j" signal is generated and the processor
It is indicated that the module is not intended to receive the message packet.

Referring to FIG. 15, the memory 168 is shown in FIG.
A preferred method for subdividing a dedicated destination selection section and for performing a comparison of map results is schematically illustrated. Each map has 4
It consists of 096 words x 1 bit, and is further subdivided into an individual processor ID sector, a class ID sector, and a hashing sector (see FIG. 8).

A common map address is selected using 12 address bits (10 bits of map address and 2 bits of nibble), thereby allowing
Bit output is obtained.

(The multiplexer and its nibble of FIG. 13 are not shown in FIG. 15 for clarity).

These four parallel bit outputs can be compared with the four bits for map selection in an ANDN-gate group 8 consisting of four AND gates, so that one or more matches are detected. If so, the output of OR gate 199 will be in the "true" state. This map result can be entered into the map result register 197 of FIG. 13A, thereby causing the message to be accepted into memory 168. Otherwise, the message will be rejected and a NAK will be sent.

Command word management section 200 includes command word management section 200.
It includes a command register 202 that receives words. The TN field of the command word can be used to access the address bus, which examines the indicated received TN and determines the appropriate response message (see Figure 18). ), furthermore, when the "Start Merge" command is executed, a data transfer path from the TN field to the PTNR (current transaction number register) 206 is secured; This is also to enable the value of p''rN (current transaction number) to be changed.

A human message entered into memory 168, as described with reference to FIG. It also includes values. These length values are calculated by the received data length counter 210 and the received key length counter 21.
1, and each of these counters can be calculated by inputting the field corresponding to each counter from a human source to 1.
When shared, the number of consecutive words contained in those fields is counted.

In addition, a forwarding section 220 is used which has an accepting function for storing processed packets in memory 168 and for transmitting those stored packets to the network at a later time. This section 220 includes a transmit transaction vector counter 222, a transmit data length counter 224, and a transmit key length counter 226, which are connected to the data bus. , are bidirectionally connected.The transmit transaction vector counter 222 is connected to the address bus;
Meanwhile, the transmit data length counter 224 is connected to an address generator 228, which is further connected to the address bus. Output buffer
Message transmission is accomplished using both the section and the circular buffer that constitutes the output message completion vector section of FIG. However, in this particular example, after the message packets have been manually input one after the other, they are now retrieved in the order determined by the vector.

Within this interface, each independent operation phase is executed at mutually exclusive times, and by employing this time-sharing scheme, memory 168 is configured to operate at mutually exclusive times. a microprocessor system running asynchronously at its own slow clock speed, receiving and distributing message packets from a network, and performing internal operations at an efficient high speed. It is possible to communicate between To control the gating of messages to the various counters and registers, a phase control circuit operates in response to control bits that control the command, DSW,
It generates data as well as other signals indicating the individual fields within the message. Transmit state control circuit 250, receive state control circuit 260, and R/W (read/write) state control circuit 270 receive clock pulses, identify fields within the data, and perform transmission, reception, and processor processing. It controls the sequencing of data flow during clock operations.

Control of this interface is controlled by three finite state machines (
FSM), each of which has a transmit phase, a receive phase, and a processor (R/
W) It is for the phase. Those FSMs are
It is constructed in a simple manner using a programmable logic array (PLA), state registers, and action ROM. Each FSM is advanced to the next state for each network clock cycle. Due to the large number of control signals to be generated, the output of the PLA is further encoded by the action ROM.

As will be readily understood by those skilled in the art, the translation of control sequences written for FSM mode, but with general detailed structure and operation, is necessary for the operation of the network. , is a simple task, although it requires a lot of work.

The inclusion of the state diagrams of FIGS. 17 and 19 and the matrix diagram of FIG. 18 in the accompanying drawings provides a comprehensive overview of internal structural design features that can be employed in fairly complex systems. This is to present the details.

Figure 17 is a diagram relating to the reception phase, and Figure 19 is a diagram relating to the transmission phase, and the notation used in these figures corresponds to the notation used elsewhere in this specification and the drawings. are doing. For example, the following terms are:

RKLC= Receive Key Length
th Counter (Receive Key Length Counter) RDLA = Receive Data Lengt
h Counter (Receive data length counter) RNDR= Receive Network Dat
a Word Register (receiving network
Data word register) PIJTC=Put, (:counter (PUT counter) GETR= G6t Register (GET register) Therefore, if you refer to the deaf diadem in comparison with FIG. 13 and the specification, there is almost no explanation. The state diagrams detail the various sequences and conditionals involved in complex message management and interprocessor communication. In Figure 17 (Figure 17A), [ The states labeled "Generate response J" and "Decode response" are written, as well as the respective conditional statements indicated by dashed rectangles.

The specified responses and actions as described in the matrix diagram of FIG. 18 are followed. FIG. 18 illustrates both the responses generated and the actions taken for any given combination of primary message and readiness state for a given TH. Of course, during normal system operation there will be some message rejection, but error conditions will occur infrequently.

In both Fig. 17 and Fig. 19, most of the conditional judgments allow multiple judgments to be executed at the same time, but in contrast, the state step It is gradually being changed. In either case, the sending and receiving operations are operations that proceed at a predetermined speed without requiring external control, and this is because the message structure and network operation method have already been explained. This is because it has become like that.

Many features employed in typical processor and multiprocessor systems are not germane to the present invention and therefore will not be specifically described. Among those characteristics are
There are parity error circuits, interrupt circuits, and various means for monitoring activity such as watchdog timers and a wide variety of test functions.

(Specific example of system operation) What will be described below is a system that integrates Figures 1, 8, and 13.
These are some specific examples showing how it works internally in various modes of operation in conjunction with. Specific examples of these are:
Demonstrates how the interrelationship between priority specification, the addressing scheme employed here, and transaction identity provides the functionality of both local control and global intercommunication. It is.

In addition to the other figures, Figure 16 will also be explained here.
FIG. 16 is a simplified state diagram of the open state involved in the final acceptance of the primary message. Even if the message is received in a buffer or memory,
Acceptance is not achieved until the illustrated logical conditions are met. Although it is shown as a serial sequence of events in the diagram,
Originally, multiple judgments were to be made in parallel, that is, at the same time, and this was because the respective conditions were not related to each other, or because the circuit needed to skip intermediate steps to reach a certain operating step. This is because it is carried out by

Messages on the network of FIG. 1 pass through the receiving network data register 146 of FIG. 13A.
It is passed through until an EOM condition is identified, at which point the message is recognized as complete. If the ``LOCK'' condition exists, the system
/LOCK to NA by referring to the response directory in
Send a rejection message.

If this is not the case, i.e. if a "lock" condition does not exist, the system reverts to a map comparison check, which is performed within the DSW management section 190 in the interface shown in Figure 13A. . If a suitable comparison result exists, indicated by ``map output = 1'', the system can continue to receive the message. If no such comparison exists, the message is rejected and a NAP is sent.

Once the appropriate map has been determined, the system is then ready to check the TN status, which is done by referencing the TN directory shown in Figure 8. (here, TN status strictly refers to the status of the processor with respect to a given TN, so H, S
, the readiness state represented by the entry stored at the TN address in RAM).

To explain in more detail, this TN status check is as follows:
This is done to determine whether the local status (=status of each processor module) is "ready to receive."

Here, it is assumed that the TH has already been allocated by a certain preceding primary message.

As a result of this check, the TN is in the "done" state, the "non-participating processor" state, or the "initial" state.
If the status is found to be one of the following, an rNAPJ rejection message is sent (here, TN is strictly speaking H, S, and T in RAM).
This refers to the entry stored at the N address.
Hereinafter, unless there is a risk of confusion, this entry will also be simply referred to as TN.) If this found status was any other non-standard condition, the rejection message sent would be rNAK/TNNAK/, and the above two types of rejection messages would also be included in the response directory of Figure 8. taken out. If the status is "ready to receive", yet another determination will be made.

This other determination is related to "manual overrun", and as described above, this determination is made when the GET address and PUT address are This is done by comparing the Additionally, the transaction number is also checked to see if the value of the received message count is non-zero; if this count value is zero, it is also indicative of an input overrun. If an overrun condition exists, r
NAK/Incoming call overrun and the message is rejected.

If all the above conditions are satisfied, H, S,
rAC from the response directory in RAM 26”
The KJ message (acknowledgement message) will be picked up and sent out on the network, competing for priority with other processor modules. Some of those other processor modules may also have sent acknowledgments to received messages.

At this point, if the common response message received from the network (where ``common'' means merged) is an rACKl message, and therefore the ``all'' processor module selected as the receiving processor module If it is specified that the module can accept the previously received message, then the received message is accepted. If this response is rA
If it is in any form other than CKJ, the previously received message will be rejected by ALL processors.

In this specific example of reception and response, after a primary message is received, all processors are focused on generating one of an ACK response, a NAK response, and a NAP response. If desired, the processor may attempt to transmit the primary message immediately after receiving any one of these response messages. (The processor may also make this transmission attempt after a delay equal to or greater than the total latency to traverse the network, which was already discussed under Active Logic Nodes. (as I did). Another point I would like you to notice is that if several processors send the same message to each other, all of those messages will eventually survive the competition on the network. It is also possible that ``all'' of those sending processors will receive an ACK response. This will be explained in detail in the specific example below.
(broadcast) and global semaphore mode operation.

Implementations of the invention in actual use include many more types of responses and perform a variety of operations in addition to those described above. FIG. 18 shows these responses and operations for the separate states of LOCK, TN error, and overrun, nine different pre-identified status levels, and acknowledgment (A).
CK) and non-applicable processor responses:
.

Each item is shown in a vertical column.

When a processor module is ready to send a message, the PTN value stored in the PTN register 206 of FIG. 13 is ready for use.
Therefore, all that is required is confirmation that the TN status is in the "ready to send" state. As can be seen from Figure 12, the entry (description) for ``Ready to send'' is
Contains the next message vector address for the output message. The output message that has been assembled is sent out onto the network, and if the contention is lost, this sending operation is repeated until the transmission is successful, and if the response is received, unless the PTN is changed midway through. become. If the transmission is successful and an acknowledgment is received, the address vector is modified. The next message vector is taken from the second word in the current message (FIG. 21A) and this word is transferred from transmit transaction vector counter 222 to random access memory 168. If the output message section is not in overrun, the PUT counter 175 is incremented by one, and this overrun condition is indicated by PUT equaling GET. Note that the next transaction transferred from the transmission transaction vector counter 222
The message vector is input to the transaction number address currently specified by transaction number register 206 in H,S,RAM. If this new TN is in the "Ready to Send" state, the value of this human-entered vector is again the storage location of the next message related to this transaction identity. pointing to. See FIG. 21 for the format of the output message stored in the H, S, RAM.

However, message management when sending messages can include many different types of actions, including changes internal to the PTN or external to the PTN. An error condition, overrun condition, or lock condition causes the system to change the transaction number
TNOJ, which returns the system to non-merge mode and then checks the status at rTNOJ.
``Ready to Send'' status is identified or a new TH
This will continue until the allocation is made. Please refer to the flowchart of FIG. 19 (FIG. 19A) for an illustration of conditions and conditions that may be employed in a fairly complex implementation.

Example of Output Message Completion Buffer Once the completion of a message transmission is indicated by any other response message except LOCK, a pointer to the newly completed output message buffer is set to H,S. , is stored in the output message completion circular buffer section of RAM (see FIG. 8). This pointer is simply a 16 bit word representing the address of the output message buffer. (
The format of the output message buffer is shown in FIG. Note that the output message buffer contains a place to record response messages received from the network).

The output message completion circular buffer provides communication between the network interface hardware 120 and the supervisory program located on the microprocessor 105. A program included in this microprocessor stores messages to be output in the H, S, RAM. As will be explained in more detail in the following example, if you chain multiple output messages together (in a chain-like manner), then
The TN can be made to act as a pointer to the beginning of this chain, allowing complex sequences of operations to be formed. Other features include multiplexing or time-sharing the network between multiple THs.
(multiplexing) (also discussed in more detail below) allows messages to be output in different orders depending on various events occurring elsewhere in the network.

Furthermore, it is possible to quickly recover the storage space in the H,S,RAM occupied by the successfully transmitted packet, thereby reusing it for another output packet to be output. It is important to The output message completion circular buffer performs this function.7 Once the transmission of a data message has been successfully completed and a response other than a ``lock'' response is received, the network interface sends the H9S, r0510 in RAM.
(hexadecimal number)" PUT pointer (first
0) is advanced by 1, and the address of the first word of the output message that has just been sent is stored in the address in the PUT register. (When the value of the PUT pointer becomes larger than the value of the TOP pointer stored in r0512 (hexadecimal), the PUT pointer is stored in r0513 (hexadecimal).
If the PUT pointer becomes larger than the GET pointer (storage location r0511 (hexadecimal number)), the circular buffer is overrun. , so an "error interrupt" is generated to the microprocessor.

Software executing within the microprocessor asynchronously examines the output message buffer to which the GET pointer points. Once the processor has completed any processing it was asked to perform,
Advance the GET pointer by "1" (this GET value is reset to the BOT value when it becomes larger than the TOP value). If GET=PUT, there are no more output messages to process.

Otherwise, further output messages have been successfully transmitted and must be processed. This process includes H, S, R
This includes returning the storage space of the AM output buffer to free space so that this space can be reused for other packets.

An important thing to note here is that the output message completion circular buffer and the human message circular buffer are separate from each other, so these two circular buffers each handle separate PUT, GET%TOP, and B
This means that it is managed by each pointer of OT. In some configurations, both circular buffers can share circular buffer management hardware 170, as shown in FIG.
Such a configuration is not essential.

Each processor module has the ability to access the TN within its own high-speed random access memory 168 (FIG. 13), and this memory 168 includes: Multiple potentially available T
N, its directories are included. However, unallocated TNs are clearly indicated as unallocated by the transaction number value stored in the storage location associated with the TH. Therefore, microprocessor system 103:
identifying unassigned transaction numbers and selecting one of them for use in initiating communications with other processor modules regarding a given transaction identity; can.

Transaction numbers are assigned and updated locally under the control of the local microprocessor (= microprocessor in the processor module), but global control throughout the network is
This is done using the primary control messages ``TN Abandonment Command'' and ``rTN Assignment Command''. A deadlock condition never occurs between competing processor modules that may request the same TN, because the network This is because priority is given to Among the processors that tried to get the TN, the remaining processors that did not get priority are rNAK/T.
N Error" response indicating that those processors should try to reserve another TN. Therefore,
There is complete flexibility in securing and verifying these transaction identities within and locally within the system.

It should also be noted that repeated use of TN
This is done by shifting between the basic transmission mode, which is NOJ, and the merge mode, where TN is greater than zero. The system can therefore change not only the focus of its operation, but also the nature of its operation, by a single broadcast transmission of the TN.

Yet another, and particularly useful, scheme for communicating changes in global status is the forced parity error propagation described above with respect to FIG. This unique display method, when transmitted between other transmissions,
The aborted system resources will be investigated and appropriate action taken.

There are two special types of processor-to-processor communication: one is communication directed to one specific destination processor, and the other is communication directed to multiple processors belonging to one class. This is a communication performed as a forwarding destination. Both of these types of transmission utilize DSW, and both of these transmissions are non-merging
Performed by mode broadcast.

In particular, when communicating between one source processor and one destination processor, destination processor identification information (destination process) is stored in the DSW.
ssor 1dantification: DP
ID) and use it. Referring to FIG. 8, when the selection map portion of the H, S, RAM 26@ of each receiving processor module is addressed using this DPID value, the specific processor intended as the transfer destination is Only the module will generate a positive response and accept the message. An acknowledgment is sent and
And if it is finally successfully received, both processors will be ready to perform any future operations requested.

If one message is to be received by multiple processors belonging to one class related to one control process, the map nibble and map nibble in the DSW are
The address specifies the corresponding section in the selection map portion of the H9S RAM. All receiving processors then send respective acknowledgments that continue competing to reach the originating processor module until the round trip for this communication is finally completed. become.

A global broadcast mode of processor communication may be used to communicate primary data messages, status messages, control messages, and response messages. A priority protocol and a network with the ability to give priority.
The inherent capabilities of both allow such messages to be easily inserted into sequences of other types of messages.

Hashing mode processor selection is by far the most commonly used processor selection method when performing data processing tasks in relational database systems.

- Multiple disjoint data subsets (=not sharing the same elements) of secondary data (=main data not for backup) and disjoint multiple data subsets of backup data. , distributed among different secondary storage devices according to a suitable algorithm. If one processor is responsible for a subset of the primary data and another processor is responsible for a subset of the backup data, and the two processors respond simultaneously, the message for the secondary data Priority will be given to those who In order to compensate for this condition, a command code with a higher priority (see FIG. 12) may be selected.

Maintenance of database reliability and integrity is also achieved by utilizing the various multiprocessor modes described above, which are then applied in the most advantageous manner to the particular situation encountered. . For example, if a secondary storage device that is responsible for a certain subset of secondary data fails, special processor-to-processor communications can be utilized to update it. Correcting errors or rolling back portions of the database can also be done in a similar manner or by operating in class mode.

Transaction Number Example The concept of transaction numbers provides a new and powerful hardware mechanism for controlling multiprocessor systems.

In this system, the transaction number is
It constitutes a ``global semaphore'' and plays an important role in sending and receiving messages to and from the network and in checking the readiness status of a given task distributed among multiple processors. .

Transaction number (TN) is HoS, RAM
It is physically implemented as 16-bit words in 26 bits. This word can perform various functions,
T
Since N is stored in H, S, and RAM, the microprocessor 105 and network interface 120
It can be accessed from either.

Global Semaphore The term "semaphore" is used in the computer science literature to refer to a variable used to control multiple processes that are executed asynchronously to each other.
It is now used for boat fishing. A semaphore has the property that it can be "tested and set" in a single non-disruptive operation.

For example, "Unassigned (IINAssIGNED)"
: Unassigned state)" and "Assigned (ASSIGNED: Assigned state)"
Let us consider a semaphore variable that can take two states. In this case, the test-and-set operation is defined as follows: If the semaphore was in the "unassigned" state, set the semaphore to the "assigned" state and indicate success. Conversely, if the semaphore is already in the "assigned" state, leave the semaphore in the "assigned" state and
"Failure" shall be displayed. Therefore, with this semaphore, a process that successfully tests and sets the semaphore can continue its task, while a process that fails has the semaphore reset to the "unassigned" state. , or attempt to test and set another semaphore controlling another equivalent resource. It is easy to understand that if a test-and-set operation could be interrupted, it would be possible for two processes to access the same resource at the same time, which would cause There is a risk that unpredictable and erroneous results may occur.

Any multiprocessor system actually implements in hardware a concept that can be equated with a semaphore to control access to the system's resources. However, conventional systems can maintain only one copy of a semaphore (a semaphore with one copy, that is, a semaphore provided at only one location). Therefore, if a multi-copy semaphore (a semaphore with multiple copies, i.e., a semaphore provided in multiple locations) is provided and maintained in each processor, one copy will be maintained.
This is desirable both for the purpose of reducing the number of times contention occurs for semaphore accesses that are merely for testing purposes, and for the purpose of utilizing multi-valued semaphore variables for other uses described below. The problem is that operations must be performed on multiple copies of the semaphore in a completely synchronized manner, and if this is not followed, then the , the integrity of access to resources will be lost.

Multiple copy semaphores, or "global" semaphores, are provided by the system. The following table compares the behavior for global semaphores with the A1-semaphore (one copy semaphore).

(Left below) In the system of this embodiment, “TN allocation (ASSI)
GN TN ) J command and rTN abandonment (RELIN
-QUISHTN)J command has a test-and-set function and a reset function for a transaction number used as a global semaphore, respectively. To explain Fig. 12, rNAK/
TN error” response indicates failure, while rSACK/
"Assign" response shows success.

The characteristics of this network, including the synchronous clocking method used to clock multiple nodes synchronously and the broadcast operation that transmits the most recent packet to all processors simultaneously, are It forms the basis for actually embodying the concept of a semaphore. With this concept in place, the system controls the allocation, deallocation, and access of multiple copies of a desired system resource by simply attaching a TN to that resource. It can be done by doing. The important thing to note here is that the control of distributed resources is
This means that it can be implemented with approximately the same small software overhead as a single semaphore. This is a significant improvement over traditional systems, which either cannot manage distributed resources or require complex software protocols and create hardware bottlenecks. Because it's either going to be put away or not.

Readiness state “BIISY J rWaiting (WAITING) J,” Ready (READY)
J (preparations for sending and receiving completed), "Complete (D
ONE) J, and “Non-Participating Processor (NON-PA)
RTICIPANT ) A set of values consisting of J (12th
(see figure) provides the ability to quickly check the readiness status of a task assigned a certain TN. In this system, the meaning of each of the above states is shown in the table below.

Using the "rTN assignment" command, TH is dynamically assigned to a task. Success display (rT
"rSACK/assign to message"
response), all operational processors successfully T
Indicates that assignment to task N has been completed. It should be noted with respect to FIG.
20 detects a conflict regarding the use of TN, all processors will receive a failure response. Furthermore, the 0PI of this failure response transmitted over the network
The D (source processor ID) field will display the first processor (the one with the lowest assigned number) among the processors that have had a conflict. This fact is utilized in diagnostic routines.

Each processor processes tasks through the action of software, and marks the TN as ``busy'', ``quieting'', ``ready to send'', ``ready to receive'', and ``finished''.
or to the appropriate one of the "non-participating processors". At any time, any processor, including the processor that issued the "initial rTN assignment", can
By issuing the "Request" command or the "Start Merge" command, it is possible to easily check the status of how much the task (TN) has been completed.

A "status request" is equivalent to a single test of a multivalued global semaphore. As can be seen in Figure 11, the status response (SACK) message with the highest priority will win out the competition on the network, resulting in the lowest readiness status being displayed. Furthermore, the 0PID field will display the identity of the first (lowest numbered) processor among the processors in the lowest readiness state.

Using this latter characteristic, a form of "non-bysy J" has been defined for "waiting" for the completion of tasks distributed to multiple processors. The processor that issued the command is said to be the first-generation "weight mask." This processor then assigns any other processor to the new "weight mask" based on arbitrary criteria. This new “
Once the weight mask has reached its desired state of readiness, it can either issue a ``start merge'' or a ``status request.''
Query all processors. If all other processors were in the ready state, 5
ACK will indicate that. If some processors were still not ready, 5A
The 0PID field of the CK response will indicate the first of the least ready processors. The "weight mask" instructs the processor to become the new "weight mask."

Eventually, all processors will reach the ready state, but until then the system simply attempts to query the status each time it is notified that at least one processor has reached the ready state. It is.

The system is thus not burdened with periodic status reconciliations that consume resources without producing results. Furthermore, this method allows the system to know that all processors have completed their work at the exact time the last completed process finishes.

will know for sure. As will be understood by those skilled in the art, there are many other variations of "standby" within the scope of the inventive concept.
The following form can be adopted.

The "start merge" command is one special type of test-and-set instruction. If the status of the global semaphore is ``Ready to Send'' or ``Ready to Receive,'' then the current transaction number register (
PTNR) 206 (see FIG. 13) is set to the value of the transaction number in the "Merge Start" message (see FIG. 3), thereby setting the PTNR register. If any of the active processors are in a lower readiness state, the value of PTNR is unchanged.

The "stop merge" command is a reset operation that corresponds to the above operation, and is a reset operation that
This unconditionally resets NR to rTNOJ.

As explained below, the current global task specified by PTNR
sk) are the only messages related to
It is designed to be output from the interface 120. Therefore, the ``Start Merge'' and ``Stop Merge'' commands provide the ability to time multiplex the network between multiple tasks, thus allowing them to A plurality of tasks can be stopped and/or restarted at will.

An important detailed feature of the invention is that network interface 120 ensures that TH is never accessed by a command from the network and TN is accessed by microprocessor 105 at the same time. be. In this example,
This is accomplished by a signal being sent from the receive state control circuit 260 to the read/write state control circuit 270, which signals that commands from the network that may change the TN are being processed. When it is present, it is always in the "affirmative" state.

During the short time that this I= signal is in the "affirmative" state, the processor restricts access to the H, S, and RAM from the control circuit 2.
prohibited by 70. As will be appreciated by those skilled in the art, a wide variety of alternative configurations may be employed in lieu of the above configurations without departing from the scope of the present invention.

reception control Yet another function of the TN is the control of incoming messages.

By using the ``rTN Assign'' command, input message streams on multiple processors can be associated for a given task. When the TN assigned to a given task in a given processor is set to "ready to receive," the TN also includes a count value representing the number of packets that the processor is prepared to accept. Displaying (N12
figure). Network interface 120 decrements this count value each time it successfully receives an individual packet (the decrement is done by arithmetically subtracting "1" from the word of TN).
This decrement continues until this count value reaches zero. When the count value reaches zero, rNA
CK/Overrun" response is generated, thereby informing the processor sending the packet that this NACK
It is informed that it must wait until the processor issuing the response is ready to accept more human packets. Furthermore, as can be seen from Figure 18,
At this time, PTNR is also reset to rTNOJ.

The above operating mechanism allows direct control of the flow of packets flowing through the network. It also ensures that one processor is not loaded with too many unprocessed packets and that the processor does not become a bottleneck for the system.

To explain transmission control in Fig. 21A, as can be seen from the figure,
H,s; “Each message stored in RAM contains a field to accommodate the value of a new TN vector (=Next Message Vector). If received in
The new TN included in this message just sent
A vector is stored (transferred from PTNR) to the address in H, S, RAM to store the current transaction number. Therefore, the TN is updated each time an individual message is sent, and it is possible to automatically set the TN to the desired state when a message is successfully transmitted. .

To explain Fig. 12, the TN of “Ready to send”
The format of contains a 14-bit HlS, address in RAM, which is the address for a given task (
This is used to indicate the next packet to be output regarding the TN).

Therefore, the TN stored in the RAM, l(,S,
It also functions as a head pointer pointing to the head of the queue (IFO). Therefore, for a given task (TN), each processor will attempt to send packets in the order determined by the chain of new TN vectors.

In combination with the previously described mechanism for multiplexing networks among multiple TNs (tasks) at high speed, it is possible to create complex combinations distributed among many processors. It is clear that tasks can be managed with very little software overhead. The configuration provided by the network, interface, and processor collaboration allows copies to be distributed among hundreds of side processors, or even among dozens of processors. For resources and tasks that can be controlled, resource allocation and allocation is a convenient structure for deallocating, canceling tasks, and other controls.

Example of Ds', v (yyun, 3rd choice word) ↑yun 3. ′：
:, Kozo R2 1 ~ (Figure 3) is DSW logic 19
Figure 13) and H, S, RAM 265, 7)
By cooperating with the DSW section, y) ÷7.multiple modes are possible. That is, in these modes; the network interface 120 of each receiving processor indicates that messages being received are processed by the microprocessor 105 associated with the network interface 105 of each receiving processor; These are multiple modes that allow you to quickly make a decision as to whether or not it is intended to be done. As already explained, the D contained in the received message
The SW selects and compares the nibble stored in the DSW section of the H,S,RAM.

Processor Address As shown in Figure 8, H, S, RAM DSW
One portion of the section is devoted to storing processor address selection nibbles. In this system,
For each of the 1024 processors that can be installed, H
, S, is associated with one of the bit addresses contained in this portion of RAM. The bit associated with the ID (identity) of the processor
The address bit is set to ``1'', while
All other bits in this section are set to 'O'. Therefore, each processor has only one bit in this section set to "1".

Hash Maps H,S Another portion of the DSW section of the RAM is devoted to storing hash maps.

In this system, two of the map selection bits are applied to those hash maps, resulting in two complete sets containing all 4096 possible values. hashed mode (ha
shedllode), the keys for records stored in secondary storage are set according to a passing algorithm, whereby keys from 0 to 40
Up to 95 "packets" are allocated. The processor responsible for the records contained in a given "bucket 1-" will write "
1" bit is set. The other bits are
A given processor can be responsible for multiple packets by simply setting multiple map bits that are set to 0.

In the configuration of this embodiment, as is easily understood, the map bits can be set in the following manner. That is, for a given map selection bit, each bit address is set to ``1'' in only one processor, and any bit address is always set to ``1'' in one processor. This method is set to "1" at the time. A direct result of adopting this approach is that each processor (AMP) is responsible for a distinct and disjoint subset of the records in the database, yet the system as a whole is responsible for the complete There are now such sets.

Although the above examples are explained using relational database problems as an example, those skilled in the art will readily understand that disjoint subsets of the problem are The same method can be applied to any task area that can be assigned to a processor.

Yet another thing worth noting is that by having two complete maps, the scheme described above can be used to transfer packets that are assigned to a given processor according to one map to the other map. This means that it can be configured so that it can be assigned to a different processor. Here, one map is "-next"
If we assume that the other map is a ``backup'' one, then a direct consequence is that a record that is primary on one processor is guaranteed to be backed up on another. It can be made so that Furthermore, there are no restrictions on the number of processors that back up a given processor.

As will be understood by those skilled in the art, the number of distinct maps that can be implemented within the scope of the present invention can be greater than two, and the number of packets can be any number.

Class In both the processor address and hash map cases discussed above, if we examine a given bit address for all processors, we can find that bit address.
It can be seen that the address is set to ``1'' in only one processor, and the corresponding bit address in all other processors is set to ``0''.

However, a scheme in which corresponding bit addresses are set to "1" within multiple processors is also possible and useful. This method is called “class
This is a method called "address" mode.

A class address can be thought of as the name of a procedure or function, copies of which exist in multiple processors. All processors equipped with the corresponding processing procedure or function have a "1" bit set in the corresponding bit address.

To send a message to a class address, the appropriate class address in the DSW (FIG. 3) is set. All operational processors that are indicated as ``belonging'' to the class by having the bit in the appropriate location in the H,S,RAM set to ``1'' It will respond with rACKJ to the received message packet. Processors that do not belong to the class respond with a NAP.

DSW therefore allows the routing calculations necessary to control the flow of messages within a multiprocessor system to be performed by hardware. Also, the program can be made independent of knowledge of which processor contains the various functions of the system. Furthermore, the map is H, S, R
Being part of the AM and therefore accessible from the microprocessor 105, it is possible to dynamically relocate certain functionality from one processor to another.

UNIヱΩ1 In complex multiprocessor systems, a task may require the performance of a series of multiple interrelated operations. This is especially true for relational database systems that handle complex queries, where data is assembled to form files, and then stored in multiple formats in a specific way. References to multiple secondary storage devices may be required to create a file that can be redistributed to the processors of the computer. The following examples illustrate how the systems of Figures 1, 8, and 13 can easily perform such functions by operating on TNs, DSWs, and global semaphores. This is a brief explanation of what is happening.

First of all, a merge coordinator (typically, but not necessarily limited to, an IFP 14-16) will merge a single file to form ( A TN with no zero assignment is selected that identifies multiple AMPs belonging to one class (among AMPs 18-23), i.e., serves as a data source, and identifies the data source function. allocated for. The second major function of distributing or hashing this file to another set of AMPs (which may be processors of the original data source) has not been allocated until then. A different TN is assigned.

The coordinator for this merge function is the first TN
The DSW is used to identify a plurality of processors belonging to a class that will perform marring operations on files related to the file. The participating processors involved in this merging work increase the level of their TN's status to "busy" or "waiting" status, and then control of the merge operation is controlled by the participating processors involved in the merge operation. (i.e., the coordinator's job is delegated).

Each of the above plurality of participating processors (all other processor modules are non-participating processors with respect to their transaction numbers) receives and processes the message packet regarding the merge task thus defined. After sending an acknowledgment to the processor, the processor proceeds with execution of its own subtasks, updating its status level accordingly. Then, once the processor to which the merge coordinator job has been delegated has completed its own task, it sends a status message to inform all other participating processors of the status regarding that transaction number. It is possible to send a request and thereby receive a response indicating the processor with the lowest readiness state among the participating processors.

Control of the merge operation is passed to the processor with the lowest readiness state, which is then able to poll all other participating processors when it is finished with its work. The above process can continue, if necessary, until a response is received indicating that all participating processors are ready. The processor acting as a coordinator at the time such a response is received then uses the DSW to identify participating processors belonging to the class H,S.

Transfer of the message to the RAM 26 is started, and as the message is transferred, the status level is updated to "ready for transmission" based on the corresponding output message vector information. If the subsequent polling shows that all participating AMPs are ready to transmit, the coordinator issues a merge start command for that particular TN.

While a merge operation is being performed, processed data packets are directed and forwarded to multiple processor modules belonging to a class for distributing the results to secondary storage according to a relational database. It turns out. Regardless of whether or not these plurality of receiving processors are the same as the plurality of processors that are the source at this time, the participating processors (i.e., the above-mentioned receiving processors) belonging to the class involved in this distribution, D
SW and the transaction is identified by a new TN. All participating processors involved in this new transaction will be assigned this new TN, and those participating processors will also increase their readiness level to ``Ready to Receive.'' This DSW will become
may be a passing selection specification rather than a class specification, but in either case all participating processors must be able to receive the message being broadcast while the merge is being performed. It is placed. When "start merge" is issued, a plurality of message packets are sent out onto the network simultaneously from each of the sending processors that should be involved in the sending operation, and the message packets are Priority is determined dynamically (during transmission). Once each sending participating processor has completed sending its own set of messages, each sending participating processor must reach a defined "End of File"
le) Attempting to send a J message, this "end
Messages such as "Profile Files" have a lower priority than various data messages. This ``end of file'' message continues to lose competition with data messages until all participating processors send out ``end of file'' messages and Once the message is sent, the transfer of the "end of file" message is accomplished. Once this transfer has been accomplished, the coordinator will
a) Send J message and follow it with rT
A "rTN relinquishment" can be performed, which ends the transaction. Overrun, error, or lock conditions can be appropriately handled by restarting the merge or transmission from the beginning.

Once the merge operation regarding one TN is completed,
This system uses the next T in the sequence of TH.
It can be shifted to N.

Once each processor module has created a queue of message packets that correspond to this new TH, those processor modules restart their efforts with the network to perform the merge operation. becomes possible. In addition to the individually executed intra-processor merge operations, the efficient use of intra-network merge operations as described above provides this system with significant advantages over conventional systems.
It is now possible to perform extremely large-scale sort/merge tasks. When the present invention is adopted,
The time required to sort one file in the system can be expressed by the following equation, assuming that the number of records is n and the number of processors is m.

m m In this equation, C2 is a constant and for this example is estimated to be about 10 microseconds if a 100 byte message is used, and C1 is a typical 16-bit microprocessor. is used, a constant estimated to be approximately 1 millisecond. Approximate sort/merge times in seconds for various combinations of n and nails are shown in the following table and are based on 100-byte records. be.

(Left below) It is not easy to compare and evaluate the numbers of the specific examples shown in the table above with the conventional system. The reason for this is that two types of interrelated sorting processing sequences (sorting by processor and sorting by network) are involved, and in the first place, there are almost no systems with such capabilities. It is from. Furthermore, in this system, messages whose lengths are long and variable are sorted and merged, whereas -
Many sorting abilities in boat fishing are evaluated for several bytes or several words.

Another important factor is that this system is a multiprocessor itself and is not a dedicated system for sort/merge processing.

The system allows for complete flexibility in shifting between merge and non-merge operations, both locally and globally, without any software penalty ( , and can be done without any loss in system efficiency.

Regarding the cycle of task/1 quest in Figure 1, each of the processors 14, 16, or 18 to 23 connected to the network 50 is used to cause one or more other processors to execute a task. task requests in the appropriate format in the form of message packets. In relational database systems, most of these tasks are performed by the host computer 10.
．． 12 and enters the system via an interface processor 14.16, although this is not a requirement. This message packet, properly formatted, is entered into a race on the network with packets from other processors, and the priority level of other tasks as well as the operating state of this processor is determined. Depending on your level, you may sometimes get priority.

A task may have its contents specified by a single message bucket, or by multiple continuation packets; 11
(see figure) is assigned a relatively high priority level, thereby ensuring that the delay in receiving subsequent parts is as short as possible.

A message packet contains transaction identity (=transaction identification information) in the form of a transaction number. This transaction number is used for non-merge mode, that is, default mode (rTNOJ), which is a mode related to the method for extracting processing results, and merge mode (rTNOJ), which is a mode related to the method for extracting processing results.
All TNs other than TNOJ) are inherently distinguished from each other according to selection. Additionally, the message packet includes a DSW. This DSW is
In effect, it specifies the transfer destination processor and the mode of multiprocessor operation, and this specification is done by specifying a specific processor, a class consisting of multiple processors, or hashing. In the example, passing is hashing to a portion of a relational database. network 5
A message packet broadcast to a target processor (designated destination processor) through by itself), and authentication of receipt is performed by an acknowledgment (ACK).

Processors 14, 16 and 18-23 are all EOM
(End of Message) followed by sending responses simultaneously to the network 50, however, the ACK sent from the designated destination processor gets priority and is received by the originating processor. become.

Subsequently, the designated transfer destination processor stores the sent message in the local H, S, RAM (=H, S, RAM provided in each processor module).

RAM) and interface 120 (FIGS. 8 and 1)
When the request packet (= sent message) is transferred to the local microprocessor via without). When tasks involving relational databases are performed, the DSW typically specifies some disjoint subset of data that is stored on the disk drives for that subset. However, sometimes tasks are performed that do not require reference to a stored database. Specific operations or algorithms may be executed by individual processors, and if multiple processors are designated as the designated destination processor, each of those processors may perform a disjoint subset of the total task. can be made to carry out work. The variable length message packet is configured such that the request message specifies the operation to be performed and the file to be referenced in the database system. It should be noted here that there may be a large number of message packets related to a given task, in which case the discrimination criteria for sorting done within the network In order to provide appropriate characteristics such as

Task response packets generated by each processor attempting to respond are sent from the microprocessor to
Local H, S, RAM via control logic 28 of FIG.
26, where the task response packet is stored in the outgoing message format of FIG. 21A. If the task response is one that requires the use of continuation packets, such continuation packets follow the initial packet, but are given higher priority for 11 consecutive continuations. Sent out. If the system is operating in merge mode and each processor is generating a large number of packets related to one transaction number, the packets are first processed locally (=individual processors' (internally) and then merged on the network 50 to arrange them into a global sort.

The task result packet is sent to processors 14.16 and 18.
~ 23 to the network 50 in a group of simultaneous transmission packets, and one highest priority message
The packet is broadcast back to all processors after a predetermined network delay. Depending on the nature of the task, these task result packets may be transferred to the source processor that originally sent the request message, or to one or more other processors. Furthermore, the transfer can be performed in any of the plurality of multiprocessor modes described above. The most common case in relational database systems is to use hashing to select destinations and simultaneously perform merging and redistribution. Therefore, as can be understood from this, in the "task request/task response" cycle, each processor operates as a source processor, a coordinator processor, and a responding processor. It is now possible to operate as all three. many"
Processors 14, 16 and 18-23 and network 50 perform multiplexing (task request/task response) cycles between their tasks.
multiplexing), but this multiplexing
This is done not only based on time but also based on priority.

In the LL1ΔI relational database system,
Utilizing the host computer 10.12, the relational database is also installed on multiple disk drives 38 according to an algorithm that defines tuples and disjoint data subsets of secondary and backup data. Using a distribution method such that complex queries are distributed between host computers IO or 12,
input into the system via This input inquiry message packet is first analyzed in detail by the IFP 14 or 16, and this analysis is performed by the host
Messages from the computer to request AMPs 18 to 23 to execute tasks? This is done to convert the request into 32 task requests. An IFP 14-16 begins its operation by sending request packets to retrieve information from one or more specific AMPs, thereby providing information needed for detailed analysis of messages from the host computer. It may be necessary to obtain in-system data. Once the IFP 14-16 has obtained the data necessary to process the request from the host computer,
It can perform several "task request/task response" cycles with the MPs 18-23 and can actually process the data to satisfy requests from the host computer. . The above processing sequence uses the cycle of task requests and task responses listed above, and can continue for any length of time.

IFPs 14-16 then communicate with the host computer via the IFP interface. This response to the host computer may simply be to provide the data that the host computer IO or 12 needs to generate the next complex query.

(Independent Multiprocessor System) The basic embodiment of the system according to the invention described above in connection with FIG. 2 shows an example of a backend processor that can be used. However, as already mentioned, the present invention is useful in a wide variety of processing applications, and particularly in those types of processing applications where processing tasks can be easily subdivided and distributed without the need for large amounts of central processing power. , which has particular advantages. FIG. 20 illustrates an embodiment of a simple configuration of a stand-alone multiprocessor system according to the present invention. 20th
In the figure, a plurality of processors 300 are all connected via an interface 302 to an active logic network 304, which is a network similar to that previously described. An active logic network 304 with redundancy may be employed to enhance data integrity. In this embodiment, processor 300 may also be a 16-bit microprocessor chip;
A main RAM memory of sufficient capacity can be incorporated. This diagram shows nine processors 300
Only two processors are shown, and each of the processors has a different type of peripheral connected to it, to demonstrate the versatility of the system. In practice, the system becomes much more efficient by having more processors on the network; however, even with a relatively small number of processors, system reliability and data This provides particular advantages in terms of completeness.

In this embodiment, the plurality of processors 300 may be physically separated from each other by a sufficient distance without inconvenience that the nodes may The maximum interval between
A large array of processors (as large as 5.5 ml) can be installed on one floor of a building, or on several adjacent floors, without unnecessary crowding. This is because it can be used.

In a stand-alone system, much more peripheral controllers and peripherals themselves are used than in the post-processor embodiment described above. , the individual person output device is
Assume that each is connected to a separate processor.

For example, an input/output terminal device 310 including a keyboard 312 and a display 314 is connected to a terminal controller 320.
The processor 300 for the terminal device 310 via
It is connected to the. However, in the case of terminal devices operating at relatively slow speeds, it is not impossible to control a fairly large network of terminal devices with a single 16-bit processor. The illustrated input/output terminal device is merely one example of how a manually operated input processing device, such as a manually operated keyboard, may be connected to the system. This terminal device 310 can also be configured as a word processor by utilizing the processing power of the processor 300, and this word processor can be used to access databases, other word processors, etc. via the network 304.
Alternatively, a large capacity secondary storage device, such as a rigid disk drive 322, which may be capable of communicating with a variety of output devices, may be connected to the processor for that storage device via a disk controller 324. Can be done. It will also be readily appreciated that larger systems may include a larger number of disk drives or different forms of mass storage. Output devices such as printer 326 and block 330 interface to processor 300 for those output devices via printer controller 328 and plotter controller 332, respectively. Interaction with other systems (not shown) occurs via a communication controller 338 and via a communication system 336, which may include, for example:
Teletype Network (TTY) or one of the larger networks (e.g.
hernetl) etc. are used. processor 300
Some of them may simply be connected to network 304 without any peripherals attached (not shown).

Bidirectional data transfer may occur between tape drive 340 and tape drive 340.
If drive controller 342 is used,
Additionally, a floppy disk drive 344 to which a controller 346 is connected is used.

-M tape drives not only provide large storage capacity when used online, but can also be used to back up disk drives. For this backup purpose, tape is used to save data stored up to a certain point in a sealed rigid disk device. Such backup operations are typically performed during periods of low load (e.g. at night or on weekends).
The network 304 is used to create a long
"Streaming" transfer can be performed. Furthermore,
Since the floppy disk drive 344 may be used for program input during initial system setup, some of the network usage time should be devoted to this "streaming" mode. , can also transfer considerable amounts of data. optical character reader 3
50 serves as yet another source of input data, which input data is sent to the controller 352.
input into the system via.

Note that the peripheral devices simply referred to as "other devices 354" can be connected to the system via the controller 356 to provide other functions as necessary. .

Respective messages from separate processor modules
packets simultaneously with each other and a priority determination is made on the message packets so that one or a common highest priority message packet is sent simultaneously to all processor modules within a predetermined period of time. A broadcast scheme is used so that any individual processor that is online has equal access to other processor modules in the system. This global semaphore system, which uses prioritized transaction numbers and readiness status indicators and destination selection entries contained within messages, allows any processor to act as a controller. This allows the system to operate in a hierarchical or non-hierarchical manner.The system can be expanded or contracted without requiring software scrutiny or changes. It is also very important to be able to

Even if access is required to a message that is significantly longer than the message lengths already discussed, but which is still relatively limited in length, such access can be performed. For example, with respect to a complex computer graphics device (not shown), access to only a specific portion of a vast database is required to create elaborate two-dimensional and three-dimensional figures. There is. Also, with word processing systems, the operator speed may be such that only a small sequence of data is required from the database at a time. In these and similar situations, the system's ability to handle messages of variable length, as well as its ability to give priority to continuation messages, is beneficial. Situations that require intensive processing power or the transmission of extremely long messages limit the use of this system, but in other situations the system works to great advantage. do.

Dynamic situations involving manipulation of a variety of different data formats and associated sorting or merging functions are all situations in which the present invention would be advantageous. Business decision-making, which involves collecting, collating, and analyzing complex data, is an example of such a situation, as well as the creation and editing of video and graphical input for periodicals. This is an example.

(Conclusion) As will be apparent to those skilled in the art, the system of FIG. (up to a practical limit). Furthermore, as is also clear, the system shown in the figure is capable of determining the status of each processing device. The amount of management and overhead software required for ``i'' recognition, setting tasks and processor priorities, and ensuring efficient utilization of processor processing power is greatly reduced.

Obvious benefits are obtained for database systems and other systems where it is appropriate to subdivide a task into multiple subtasks that can be processed independently of each other. etc. For example, when it comes to relational databases, even if the capacity of secondary storage increases significantly, it is only necessary to appropriately integrate additional databases into a data structure consisting of primary and backup data. It is. In other words, it is possible to expand the network without limit;
Because the standardized nodal devices or nodes are connected in a binary evolving connection scheme, the functions performed at their individual nodes do not change with expansion. Furthermore, there is no need for a setting processing sequence or external control for the operation of the nodes. Therefore, the system according to the invention, as shown in FIG.
When connected to act as a back-end processor for one or more host computers, users of the system can freely modify the database without changing the operating system software or application software. It can be expanded (or reduced) to From the perspective of the host processor system (= host computer), this back-end processor is ``transparent'' regardless of its configuration.
This is because the configuration changes do not change the manner in which the back-end processor interacts with the host processor system. To switch this back-end processor to do the work of another host processor system, simply ensure that the IFP speaks appropriately to the new host processor system's channels or buses. Just that is fine.

The configuration of the network in one practical example shows that a single array can be configured without significant delays in message transfer within the network, or without unreasonable delays due to contention between processors. 10
It can contain and use up to 24 microprocessors. It will be apparent to those skilled in the art how the embodiments described herein may be extended to include more than 1024 processors. When using 1024 processors in a system, it is known that the maximum line length between active nodes is 28 feet in a practical example, and this line length is sufficient for configuring an array. No problems will arise. The delay time due to the network is a constant time 2tN for any message, where the byte clock interval and N is the number of layers in the hierarchical structure. Clearly, doubling the number of processors by adding one more layer only slightly increases the delay time. Data messages are almost inevitably long messages (about 200 bytes long), and determining priority among all competing messages requires the data to be transferred along the network. This makes the network much more efficient at transferring data messages than traditional systems.

Among the important economic and operational features of the system is the fact that standardized active logic circuits are used to replace software and even firmware in network systems. There are certain characteristics that have been achieved. That is, based on this fact, it is possible to use modern LSI and VLSI technology to incorporate a highly reliable circuit at a relatively low cost compared to the overall cost including the cost of the processor and the cost of peripheral devices. It is now possible to do this.

The amount of time and money that must be spent on software is limited to only the critical parts, such as those related to problem area tasks such as database management. For example, the configuration of this system allows all functions necessary to maintain the integrity of the database to be performed within the range of the message packet configuration as well as the network configuration. Polling,
Functions such as status changes and data recovery are performed within the system.

Yet another important consideration is that the network of the present invention is sufficiently superior in its high speed data transfer performance to conventional ohmic wired buses. Since multiple message packets are sent simultaneously and their priority is determined while they are being transmitted, conventional methods require a This is because the delays that would otherwise have occurred have been avoided.

Furthermore, even if the number of processors is enormous, it is possible to keep the length of the connection structure between nodes to a predetermined length or less, so the propagation time within the bus becomes a constraint on the data transfer rate. Never.

The present system has been found to be near optimal in terms of microprocessor and network usage efficiency. The important thing about these points is that
These are to ensure that all microprocessors are kept busy and that the network is fully utilized. rI FP-Network-A
The construction of MPJ makes this possible in effect, because a microprocessor whose message packets it has sent lose in the competition for priority will have to try again at the earliest possible time. It only needs to attempt to transmit, thus keeping the bus duty cycle at a high level. High speed random
Access memory also contributes to this effect, since high-speed random access memory stores both input message packets to be processed and output message packets to be sent out. This is because each processor can always obtain a backlog of work, and the network can also obtain a backlog of message packets. Once all the power buffers are full, the processor sends an indication over the network to indicate this fact.

Also, when the input buffer used by the IFP to receive messages from the host computer becomes full, an indication is sent out on the channel to notify this fact. The system is therefore self-paced both internally and externally.

By utilizing the architecture and message structure described above, the system is configured to perform many other functions required of a general-purpose multiprocessor system. For example, in the prior art, great attention has been paid to methods for evaluating and monitoring changes in the status of global resources.

In contrast, according to the present invention, only a parity channel is provided and used as a means for communicating both the occurrence of a parity error and the fact that processor availability has changed.

When one or more processors shuts down, the shutdown is propagated through the system at approximately the same time as it occurs, so that execution of the interrupt sequence can begin. There is.

Because the system uses a method that sorts multiple responses according to priority, it is much easier to understand the nature of changes in global capacity than before. The small circuit size and system overhead make it possible to specify.

The global response achieved through one-time priority determination, achieved by employing global semaphores and active logic networks, has very deep systemic implications. By broadcasting queries in this manner, unambiguous, unambiguous global results are obtained, eliminating the need for complex software and overhead. Status setting operations such as distributed updates can be performed even when multiple simultaneous operations are being performed on multiple different processors.

Furthermore, by using the network, transaction number, and transfer destination selection word as described above, this system exhibits excellent ability to distribute work and collect processing results in a multiprocessor system. Various multiprocessor modes and control messages are available, and various levels of priority can be easily set and changed simply by manipulating the priority protocol. . The ability to broadcast to all processors simultaneously, combined with the ability to sort messages across the network, makes it possible to target any group of processors or any individual processor. At the same time, it is also possible to extract processing results in an appropriate order. Thus, once a complex query is entered into a relational database system, it initiates any processing sequence necessary for database operation.

A further advantage of this system is that it can be used in multiprocessor systems such as relational database systems.
The reason is that redundancy can be easily introduced. Having dual networks and dual interfaces provides redundancy that allows the system to continue operating even if one network fails for any reason. By distributing the database into disjoint temporary and backup subsets, the probability of data loss is reduced to a minimum level. A variety of versatile control functions are available to maintain the integrity of the database in the event of failures or changes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system according to the invention, including a novel bidirectional network. 2 and 2A to 2J are a series of sequential sequences over time illustrating the manner in which data and control signals are transmitted in the network of the simple embodiment shown in FIG. FIG. 2 is a diagram showing the state before the start of signal transmission, and FIGS. 2A to 2J are diagrams showing continuous lO from 1=0 to t=9, respectively.
FIG. 4 is a diagram corresponding to one of the time samples at a point in time; FIG. 3 is an explanatory diagram illustrating the structure of a message packet employed in the system shown in FIG. 1. FIG. 4 is a block diagram illustrating further detailed structure of the novel bidirectional network shown in FIG. 1 with respect to the active logic nodes and clock circuits used. FIG. 5 is a state diagram illustrating various operating states within the active logic node. FIG. 6 is a timing diagram for explaining the end-of-message detection operation performed within the active logic node. FIG. 7 is a timing fluid diagram for explaining the operation of the clock circuit shown in FIG. 4. FIG. 8 is a block diagram of a processor module including high speed random access memory that may be used in the system shown in FIG. FIG. 9 is a diagram showing the internal address allocation status of the main RAM of the microprocessor system shown in FIG. 8. FIG. 10 is a block diagram of the arrangement of data within one reference portion of the high speed random access memory shown in FIG. 8. FIG. 11 is a chart showing the message priority protocol used in the system. FIG. 12 is an explanatory diagram illustrating the word format of a transaction number. 13 and 13A are block diagrams of interface circuits used in each processor module included in the system shown in FIGS. 1 and 8, and are shown on the right side of FIG. 13. This is a diagram that can be combined into one sheet by placing FIG. 13A on . FIG. 14 is a timing diagram illustrating the various lock and phase waveforms used in the interface circuit of FIG. 13. FIG. 15 is a block diagram illustrating further details of the memory configuration and one method of mapping for mapping based on destination selection words. FIG. 16 is a simplified flowchart showing the changes in status upon receiving an input data message. FIG. 17 and FIG. 17A are flowcharts showing changes in status when a message is being received. FIG. 17 is arranged in contact with the upper edge of FIG. 17A to form a single page. It is. FIG. 18 illustrates the relationship between various primary messages and the various responses generated to them, as well as the relationships between various primary messages and the actions performed in response to them. This is a table showing FIG. 19 and FIG. 19A are flowcharts showing changes in status when a message is being sent, and by arranging FIG. 19 in contact with the upper edge of FIG. 19A, the diagrams can be combined into one page. It is. FIG. 20 is a block diagram of a stand-alone system according to the present invention. FIG. 21, consisting of FIGS. 21A and 21B, is a diagram showing messages stored in the high speed random access memory. FIG. 22 is a simplified schematic diagram illustrating one possible distribution scheme for distributing respective portions of a database among a plurality of different processors within a database system. 10.12--Host computer, 18-23--
access module processor; 24--one microprocessor; 26--one high-speed random access memory; 28--one control rosic; 32--disk controller; 38-43--disk drive; 50--one active rosic. Network structure, 54--one node, 56--clock source, 120.120°--network interface, 103--one microprocessor system.

Claims (1)

[Scope of Claims] (1) A message transmission network having a plurality of terminals for receiving a plurality of messages that collide with each other, comprising a plurality of signal transmission means extending between the plurality of terminals, Each of the signal transmission means includes a plurality of bidirectional message switching nodes serially coupled by a plurality of transmission links, the plurality of message switching nodes connecting a common one to the plurality of terminals. The plurality of message switching nodes are connected to each other to form a convergent structure converging to one direction reversal node, and the plurality of message switching nodes transfer messages from any of the plurality of terminals to the common A message transmission network comprising means for sending back to all said terminals in a divergent direction (anti-convergence direction) via a direction reversal node. (2) means for each of the plurality of message switching nodes to determine priority among conflicting messages based on data content of those messages; 2. A message transmission network according to claim 1, further comprising means for transmitting only common messages. (3) the plurality of message switching nodes are comprised of active logic means arranged in a continuous hierarchical structure, the active logic means being responsive to the messages being transmitted; 3. The message transmission network according to claim 2, wherein the message transmission network is for merging messages flowing in a convergence direction according to a predetermined priority protocol when a message transmission network is being carried out. (4) the messages are in a plurality of serial trains, and the active logic means synchronizes the serial trains with each other during successive time frames to provide a direction of convergence along the plurality of nodes; 4. A message transmission network as claimed in claim 3, including means for advancing in both the direction of diffusion. (5) The plurality of message switching nodes and the plurality of transmission links include means for transmitting a collision indication along the transmission path of a transmission that does not receive priority. Message transmission network according to item 2. (6) Each of the plurality of message switching nodes includes one port on a convergence side and two ports on a divergence side, and each of the plurality of message switching nodes
nodes are arranged in a binary tree structure, and each of the plurality of message switching nodes includes a bidirectional data line and a unidirectional control line, and , the message is a serial sequence of variable length, and the length of the transmission link does not exceed a predetermined length. (7) The network includes two sets of a plurality of message switching nodes and interconnection structures thereof, the sets being connected to the plurality of terminals redundantly and in parallel with each other. 2. The message transmission network of claim 1. (8) The plurality of message switching nodes in each set are arranged in a hierarchical structure that converges as one ascends the hierarchy, and each of the message switching nodes has bidirectional active logic.・It is a node,
Furthermore, the hierarchical structure of the nodes includes means for determining priority between mutually conflicting messages at an initial hierarchical level as well as at intermediate hierarchical levels, thereby preventing 8. The message transmission network of claim 7, wherein communication of one highest priority message is effected by broadcasting a never-ending downstream message to all of said terminals. (9) said active logic node comprises upstream register means, comparator means and multiplexer means for upstream messages; control line transmission link means for indicating collisions and parity errors of upstream messages; downstream direction; 9. A message transmission network as claimed in claim 8, including register means and local clock means. (10) A bus network for connecting each of a plurality of terminals to all of the remainder of the terminals, wherein the plurality of terminals send out a plurality of information packets that collide with each other, the plurality of active nodes circuits, the active node circuits being connected to each other in a converging tree structure, and apex node means for directing information packets from any of said terminals back towards all of said terminals. merging/transmission means provided in each of the node circuits, the merging/transmission means merging information packets flowing in an up-tree direction, and merging information packets flowing in a down-tree direction; a bus network, wherein transmissions in a down tree direction from said apex node means are received by said plurality of terminals substantially simultaneously. (11) Each of the plurality of node circuits includes priority determining means for determining priority between competing packets based on the data contents of those packets, and the network further comprises: a transmission means for connecting said plurality of node circuits to each other in a binary expanding hierarchical structure, and for moving segments of information packets from layer to layer during successive time frames; 11. The bus network of claim 10, comprising means. (12) the information packet comprises a serial string of data, and means for indicating that the plurality of node circuits were unable to obtain priority among competing information packets; a unidirectional control line for transmitting an indication of failure to obtain privileges downstream from hierarchy to hierarchy, and a plurality of control lines connecting each of said plurality of node circuits to other node circuits or said terminal; 12. The bus network of claim 11, comprising: parallel data conductors. (13) The priority determining means provided in each of the node circuits includes means for determining minimum data content among mutually competing information packets, and
Claim 1, wherein the node circuit includes means for interrupting the circuit path of an information packet being received at a port that does not receive priority in response to a priority award.
The bus network described in 2. (14) A method for broadcasting one message or a common message among a group of mutually conflicting messages to a plurality of processors, the method comprising sorting the arbitration between mutually conflicting messages based on the data content of those messages. and broadcasting the highest priority message to all of the plurality of processors simultaneously. (15) A method for transmitting conflicting messages between different sources in a network, the messages advancing synchronously from layer to layer in a converging hierarchical structure, and , a synchronous forwarding step that merges messages by blocking lower priority messages during that forwarding, and an indication that a message from a particular source has been blocked via the hierarchy. obtaining one message or a common message at the top layer of the hierarchical structure; and transmitting the one message or common message through the layers of the hierarchical structure. broadcasting said message or common message by synchronously advancing in a return direction, thereby distributing said message or common message to all of said different sources; - A method including steps. (16) the synchronous forwarding step comprises a merging operation performed by performing a comparison between each pair of messages in each of the tiers of a plurality of pairs of messages that collide with each other during upstream flow; 16. The method of claim 15, wherein the broadcasting step comprises an unobstructed distribution operation in a downstream direction.