JP2555450B2 - Multiprocessor system - Google Patents

Description

The present invention relates to a multiprocessor system.

(Prior Art) Since the emergence of a highly reliable type of electronic computer (electronic computer), a system using a plurality of computers has been considered as a system that has been considered by those engaged in this technical field. By operating these computers while maintaining their relevance,
There are systems that allow the whole of a given task to be performed. In some such multiprocessor systems, one large computer is
Run complex parts of the program with its own great speed and capacity, and delegate less complex or less urgent tasks to smaller, slower satellite processors In some cases, the load on the large computer and the amount of requests for the large computer are reduced. In this case, the large computer assigns sub-tasks, keeps the small processors (= the above-mentioned satellite processors) always in operation, checks the availability and operating efficiency of those small processors, and unifies them. Responsible for ensuring the results obtained.

Among other multiprocessor systems employing other schemes, some use multiple processors and one common bus system, and the multiple processors are essentially equal to each other. There are systems to which functions are provided. Such systems often use a control computer or control system independent of the other parts to monitor the availability and processing power of the individual processors for a given subtask, and Tasks and information transfer paths are controlled. In some, the configuration and operation of each processor is set so that the processor itself can monitor the status and availability of other processors and determine the transfer path of messages and programs. . A significant drawback common to these various systems is that software is required and operating time is consumed to perform the overhead and maintenance functions, thereby performing the intended purpose. Will be affected. The amount of work involved in determining and monitoring the transfer path increases with a quadratic function of the total number of processors involved in those tasks, eventually leading to inadequate effort being spent for overhead functions. There is also.

The following several patent publications show examples of the prior art.

Since the early days of Binac (“Binac”: two processors connected in parallel to each other) and various similar systems, the multiprocessor approach already provided redundant execution capabilities. It has been recognized that such provisions can significantly improve the overall reliability of a working system. So far, there are considerable restrictions on the actual configuration of multiprocessor systems, but these restrictions are mainly due to the huge amount of software. is there. Nevertheless, for example in real-time applications,
Various multiprocessor systems have been developed so far, since multiprocessor operation is particularly advantageous in various situations where system downtime cannot be tolerated. These systems performed well on their own, but due to overhead they had to devote a significant amount of software and operating time. Such conventional systems are disclosed in U.S. Pat. Nos. 3,445,822 and 3,566,363.
And No. 3,593,300 show specific examples. Each of these patent publications relates to a system in which a plurality of computers are accessed by a single main memory shared among them, and further, in this system, tasks are suitable for individual processors. For allocation, the processing capacity and the processing demand are compared.

Yet another example of the prior art is US Pat.
There is 9,233 issue. In the system disclosed in this publication, a plurality of processors share one bus, and
Using a control unit with a built-in register, the data
Block transfer is performed. The concept of this system is used in Europe for distributed mail classification systems.

U.S. Pat.No. 4,228,496 relates to a commercially successful multiprocessor system in which a plurality of buses between a plurality of processors are connected to a bus controller. The controller monitors the data transmission status and determines the priority for a plurality of data transfers performed between the processors. Further, each processor is connectable so as to control a certain one of a plurality of peripheral devices.

An "Ethernet" system co-promoted by Xerox, Hewlett-Packard, and Intel (U.S. Pat. No. 4,063,220)
And US Pat. No. 4,099,024) provide yet another scheme for addressing the problem of intercommunication between multiple processors and peripheral devices. All units (= processors, peripherals, etc.) are connected to a multiple access network shared between them, and they will compete with each other for priority. The collision detection is performed in a time-priority manner, and therefore, controlling the global processing capacity,
Coordinating and clearly grasping,
It is no longer easy.

In order to fully understand the various systems described above in detail, it is necessary to analyze the above-mentioned patent publications and other related references in detail. However, when tasks are shared, all of these systems require a huge amount of intercommunication and management control to determine the priority of data transfer and to select processors. Only a brief overview will be understood. The problems that occur when a system is expanded to include more processors are not uniform because each system is different, but none of the above systems However, if such an extension is performed, system software, applied programming, hardware, or all three of them will be complicated. Also, as will be understood by some consideration, one pair or two
Due to the fact that a set of logically passive ohmic buses is employed, its inherent constraints are imposed on the size and capabilities of multiprocessor systems. There are a variety of techniques that can be employed to facilitate intercommunication, such as the subsystem shown in recently issued U.S. Pat.No. 4,240,143. There is a technique of grouping the resources into global resources. However, when a large number of processors are used, the amount of available traffic naturally reaches its limit, and the The fact that time takes various values raises an insurmountable problem. In some situations, one or more processors may be locked out or deadlocked, and additional circuitry and software to solve the problem require additional circuitry and software. Needed. From the above, it is apparent that it has not been practical in the past to significantly expand the number of processors to, for example, 1024.

In many different applications, it is desirable to escape from the limitations of the existing techniques described above and utilize the latest techniques as the greatest source. The lowest cost technique currently available is based on mass-produced microprocessors and large-capacity rotating disk storage devices, and as an example of such storage devices. Is a Winchester
There are devices made by technology. In expanding a multiprocessor system, it is required that the system can be expanded without unduly complicating the software, and furthermore, the software does not become complicated as it expands. There is even a demand for expansion. Still further, there is a need for the ability to deal with computer problems having features such as having a distributed structure in which the entire functionality can be dynamically subdivided into a plurality of limited or repetitively executed processing tasks. . Virtually all database machines belong to such problem areas, which also include sorting, pattern recognition and correlation calculations, digital filtering, large matrix calculations. Other typical examples of problems such as simulation of physical systems, etc. are also included. In any of these processing situations, it is necessary to make a plurality of individually processed tasks relatively simple, and to distribute the tasks over a wide range, so that the instantaneous task load is large. It will be. Such a situation made conventional multiprocessor systems extremely difficult.
The reason is that such situations tend to increase the time spent on overhead and the amount of software for overhead, as well as practical obstacles to configuring the system. Especially.
For example, when a passive shared bus is employed, the propagation speed and the time required for data transfer form an absolute barrier to the possible processing speed in processing a transaction.

Therefore, the database machine is a multiprocessor
This is a good example of the need for improved systems. Up to now, three types of methods have been proposed as basic methods for constructing a large-scale database machine, which are a hierarchical method, a network method, and a relational method. Among them, the relational database machine allows a user to easily access given data in a complex system by using a table showing relations. Machines are recognized as having strong potential. Representative publications describing this prior art include the "Relational Database Machine" by DCP Smith and JM Smith, for example, page 28 of the March 1979 issue of IEEE Computer Magazine. Paper titled (ar
ticle entitled “Relational Data Base Machine”, publ
ished by DCPSmith and JMSmith, in the March 19
79 issue of IEEE Computer magazine, p.28), U.S. Patent Publication No. 4,221,003, and various articles cited in the publication.

Sorting machines are also a good example of the need for improved computing architectures. For an overview of sorting machine theory, see "Searching and Sorting" by DEKnuth, "Searching and Sorting," pages 220-246, by DE Knuth.
th, pp. 220-246, published (1973) by AddisonWesley
Publishing Co., Reading, Massachusetts). A variety of networks and algorithms are disclosed in this document, and one must consider them in detail in order to understand the constraints associated with each of them, but generally speaking about them:
All of them are characteristically complicated methods aimed at only a specific purpose called sorting. Yet another example is presented by LA Mollaar, "IEEE Transaction on Computer", Volume C-28, No. 6, June 1979, No. 406. ~ Article entitled "A Design for a List Me" on page 413
rging Network ", in the IEEE Transactions on Compute
rs, Vol. C-28 No. 6, June 1979 at pp.406-413). In the network proposed in this paper, a method of externally controlling a merge element of the network is adopted, and the network requires programming to execute a special function.

Functions that a general-purpose multiprocessor system must be able to perform include the ability to distribute subtasks in various ways, the ability to check the status of the processor executing the subtask, and the merging and sorting of messages. Functions to perform, correct and change data, and when and how resources have changed (eg, when a processor goes off-line,
There is a function to confirm when you came back online. In order to perform the above functions,
Excessive software and hardware for overhead had to be used.

For example, in a multiprocessor system such as a database machine, when a message transfer path between processors is specified, one specific processor is selected as a transfer destination, or
Instead of selecting multiple processors belonging to one class, or even specifying the processors themselves,
It is often necessary to select a destination processor by specifying a portion of the database distributed to the processors by a hash method or the like.
Some known systems make use of a forward communication sequence, whereby the transmitting processor and one
The linkage with one or a plurality of specific receiving processors is established. Requests and acknowledgments must be sent repeatedly to establish this linkage, and additional hardware and software must be used to overcome possible deadlock conditions. I won't. In a system that does not use the pre-communication sequence, control is performed by one processor or by the bus controller. This control means that the transmitting processor is ready for transmission and the receiving processor receives It is to confirm that it is ready, that the other processors are locked out of the linkage between these processors, and that no extraneous transmissions are taking place. Again, maintenance functions as the system grows (eg, with more than 16 processors) by relying on overhead and having to be complicated to avoid deadlocks. Will expand to an inappropriate level.

As yet another example of the requirements placed on modern multiprocessor systems, the status of subtasks being executed by one or more processors can be
Some are related to how the system can reliably determine. Basically, what is required is that a given processor must be able to query the status of that processor, and that status is affected by the query. That is, the inquiry must be made so as not to cause any ambiguity in the content of the response. The term “semaphore” is currently used in the art to characterize the function of performing a test and a set of status indications as an uninterrupted series of operations. It is desirable to have this semaphore feature, but incorporation of this feature must not cause a decrease in execution efficiency or an increase in overhead load. Such a status determination is very important when performing a sort / merge operation in a multiprocessor system, and it is a result of processing of each of a plurality of subtasks included in a large task. This is because they cannot be combined into one only after those subtasks have been properly processed. Yet another requirement is that the processor be
It may be necessary to be able to report the status, and the execution of a subtask should be done only once, even with repeated interruptions and changes to the operating sequence of the multiprocessor. Most existing systems pose a significant problem in this regard because the execution routines of the processor are interruptible. That is, as will be easily understood, when a plurality of processors are executing a plurality of subtasks related to each other, the degree of the readiness state of each individual processor (= what operation is performed) The sequence of operations involved in querying and responding to the query can require enormous overhead, and the dedicated overhead therefor increases as the number of processors increases. It will eventually increase to an inappropriate level.

(Problems to be Solved by the Invention) A typical disadvantage in the conventional multiprocessor system showing the examples described above is related to a so-called “distributed update” problem. This means that the information stored in each of the individual processing units must be updated. The information referred to here may be information composed of data records or information used for controlling the operation of the system. Controlling the operation of this system means, for example, that the necessary steps are not accidentally executed in duplicate or not executed at all, and the processing is started, stopped, restarted, suspended, or It is control such as roll back or roll forward. In conventional systems, the various solutions to the distributed update problem have all come with considerable constraints. Some of those solutions are
Some are intended for only two processors at a time. Some further solutions use intercommunication protocols, but these protocols are so complex that even today they are mathematically rigorous to ensure that they are appropriate. It is very difficult to prove by using.

The complexity of these protocols is due to the fact that a single, uninterrupted operation of all processors constitutes a "global semaphore".
That is, it is necessary to provide a control bit having an external property of being "and set". Since such control bits are provided inside each of a plurality of separate processors, and the delay times associated with the communication between the processors are different, noise is inevitably caused by a communication channel which can inevitably be incomplete. Is generated,
Further, the error occurrence rate is further increased. Therefore, having the feature of "one operation that is not interrupted" means that the plurality of parts constituting one operation are various and can be interrupted, respectively. Are difficult to access if they are not accessible at the same time, and if they are prone to malfunction between accesses.
Those skilled in the art will readily understand.

SUMMARY OF THE INVENTION In summary, the present invention provides a multiprocessor system with a plurality of different types of processors. In this multiprocessor system, two or more kinds of processors are included in the plurality of processors, and they can access each other equally and simultaneously from the network, but handle the workload of the system. The above functions are different from each other. The ability for one type of processor (eg, an interface processor) to organize and distribute multiple subtasks, while the other type of processor (eg, an access module processor) performs the required operations under those subtasks. Fulfill. Both of these types of processors compete for equal conditions when sending messages to the network. The handling of subtasks in one type of processor differs from the behavior of the network, which distributes selected messages from all processors to all of them.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

(Database Management System) The system generally shown in FIG. 1 shows a specific example in which the concept of the present invention is applied to database management. More specifically, the system comprises one or more host computer systems1
0, 12, and their host computer systems are, for example, computer systems belonging to the IBM 370 family or the DEC-PDP-11 family, and serve the purpose of this embodiment. Thus, it is designed to run on existing general operating systems and application software. According to IBM terminology, the main intercommunication network between a host computer and a database computer is called a channel, and the same is according to DEC terminology as "unibus" or "mass bus". "Or some modified version of those terms. Whether any of the above computer systems are used or a mainframe computer from another manufacturer, this channel, or bus, is where the database tasks and subtasks are sent. , That is, a logically passive transfer path.

The embodiment of FIG. 1 illustrates a back-end processor complex associated with host systems 10,12. The system in this figure accepts tasks and subtasks from the host system, looks up the appropriate portion of the vast database storage information, and returns the appropriate processed or reply messages, and their actions. Irrespective of the configuration of this back-end processor complex, it is executed in a manner not required by the host system, except for less sophisticated software management. Therefore, it is possible to configure a user database as a new type of multiprocessor system. In this multiprocessor system, data is stored in a relational database file capable of greatly expanding the capacity. The extension can be made without changing the operating system or existing application software provided inside the user's host system. A specific example configured as an independent system (stand-alone system) will be described below with reference to FIG.

As will be appreciated by those skilled in the art, the operational functions associated with relational database management may divide an entire operational function into a plurality of processing tasks that can be processed independently of the other, at least temporarily. It is an operation function that can be performed. This is because in a relational database, stored data entries are not interconnected by address pointers. Further, as will be understood by those skilled in the art, other than relational database management, it is possible to use a method of dynamically subdividing limited or repetitively executed tasks and processing them independently. Many data processing environments exist. Accordingly, in describing embodiments of the present invention, a description will be given in relation to processing issues in database management, which are particularly strong and frequently asked, however, the novel methods and methods disclosed herein The arrangement has a wide range of other uses.

Large data management systems will have both potential benefits and unavoidable attendant difficulties when using multiple processors (multiple processors). Hundreds of millions of entries (entries)
Must be kept in a storage device for easy and quick access. On the other hand, if the relational database format is used, a wide range of data entry and information retrieval operations can be executed concurrently.

However, in the vast majority of database systems, maintaining the integrity of the database is as important as quickly processing transaction data. Data integrity must be maintained before and after hardware failures, power outages, and other system operation-related disasters. In addition, the database system must clean up user-side errors, including bugs in the application software code,
It must have the ability to restore the database to a previously known state. In addition, data must not be accidentally lost or entered,
Related to a particular entry, depending on whether the event relates to new data, correction of past errors, or calibration of a portion of the database. All of the database parts you are working on must be changed.

Thus, for completeness, in addition to data rollback and recovery operations, error detection and correction operations, and detection of changes in the status of individual parts of the system and their compensation, and to some extent, Is also necessary for a database system. To achieve these ends, it is possible that the system must be used in many different specialized modes.

In addition, modern systems have a discretionary query that can be complex in form.
It is required to have the ability to accept y) and, if necessary, to respond in an interactive manner. Even if the query is complex, it should not require that anyone attempting to access the system be an expert in the system.

Examples of arbitrary queries that may occur in connection with large-scale production operations include:

A. The manager who manages production not only requests a list for one of the stock items, but also the monthly production of parts whose production has decreased by at least 10% compared to the same month of the previous year. You may request an inventory list that clearly lists all parts in stock that are exceeded.

B. The marketing manager determines that a particular account
In addition to inquiring whether 90 days are overdue,
It may require a uniform 90-day receivable for customers who have been in excess of 120 days in the past, particularly in a recession.

C. Not only is the HR executive required to list all employees who have been sick for more than two weeks in a given year, but also for more than two of the last five years, You may want to list all long-term employees who have been sick for more than a week during the fishing season and who have been working for more than 10 years.

In each of the above examples, the user seeks to determine the real problem faced in the business by associating information stored on the computer in ways not previously possible. A database system that enables an untrained computer expert to handle complex queries if the user has experience in the area where the problem is occurring, and thus the user has intuition and imagination. Can be used freely.

Modern multiprocessor systems seek to address these many, and often conflicting, requirements by using carefully crafted overhead and maintenance software systems. In an effort to do so, those software systems are essentially a hindrance to easy system expansion. However, the concept of scalability is a strongly sought-after concept, as the business or business grows, as it is desired to extend and continue using existing database management systems. In this case, it is not desirable to be forced to adopt a new system and software.

Multiprocessor Array Referring to FIG. 1, an exemplary embodiment of the system of the present invention includes a number of microprocessors, of which there are two important types, Are referred to herein as an interface processor (IFP) and an access module processor (AMP), respectively. 2 in the figure
A number of IFPs 14, 16 are shown, each of which is connected to an input / output device of a separate host computer 10-12. Multiple access module processors 18
23 are also included in what may be referred to as this multiprocessor array. The term "array" is used herein to refer to a set of processor units, a group of processor units, or a plurality of processor units, generally arranged in an orderly linear or matrix fashion. Used in a meaning,
Therefore, it does not mean what has recently become known as an "array processor." Although only eight microprocessors are shown in the figure to illustrate a simplified example of the concept of this system, much more IF
P and AMP can be used and will normally be used.

The system shown in FIG. 1 will be described generally. The interface processor receives various tasks to be processed from the host computer, and identification information (transaction number: TN) unique to each task. Assign In addition, the interface processor creates a plurality of subtasks to be processed in a distributed manner in the access module processors for each individual task and sends it to the active logic network structure. Each subtask has the identification information. The network structure broadcasts the subtasks to all the processors with a predetermined time delay. Each access module processor processes the received subtask, if it requests updating or reading of the memory of the disk allocated to it, and processes the result.
It is sent to the network structure by a request from the processor based on the identification information.

The IFPs 14, 16 and AMPs 18-23 incorporate an Intel 8086 16-bit microprocessor having an internal bus and main memory for direct memory access to peripheral controllers. Any of a wide variety of microprocessors and microprocessor system products from various manufacturers are available. This "microprocessor" is only one specific example of one type of computer or processor that can be used in this array because the concept of this system is that the computing power required by the application is a minicomputer or If it is a large computer, it can be used successfully with them. This 16-bit microprocessor has considerable data processing power, yet is in a standard replaceable configuration that can replace a wide variety of available hardware and software options, low cost. Is an advantageous example of the device.

The IFP and AMP employ similar circuits, including active logic, control logic and interfaces, microprocessors, memories, and internal buses, which are described with reference to FIGS. 1 and 8, respectively. This will be described later. However, the two processor types differ in the nature of the peripheral devices associated with each processor type and the control logic for those peripheral devices. As will be readily appreciated by those skilled in the art, other processor types with different peripheral controllers and different functional tasks may be readily incorporated into the present invention.

High speed random access to each microprocessor
A memory 26 (described in connection with FIG. 8) is provided which, in addition to providing buffering of input and output messages, is unique to the rest of the system. Cooperate to manage messages. Briefly, this fast random access memory 26 acts as a circular buffer for variable length input messages (referred to as "receive" for this input) and for sequential message output (this output Functioning as a memory), incorporating a table-pulling part for use in hash mapping mode and other modes, and storing control information to handle incoming and outgoing messages in an orderly manner. To do. The memory 26 is further used to perform a unique role when selecting a multiprocessor mode and when handling data, status, control, and response message traffic.
As will be described in more detail below, these memories further store local and global status determination and control functions based on the transaction identity in the message in a very efficient manner. It has a configuration. The control logic 28 provided in each of the IFPs 14, 16 and AMPs 18-23 (discussed below in connection with FIG. 13) is used to transfer data and perform overhead functions within the module.

Each of the IFPs 14 and 16 has an interface control circuit 30, and the interface control circuit 30
10 or more host computers associated with the FP
Connected to 12 channels or buses. On the contrary
In the AMPs 18 to 23, a device corresponding to the interface control circuit is a disk controller 32, and the disk controller 32 may have a general structure. Used to interface with the respective magnetic disk drives 38-43.

The magnetic disk drives 38-43 provide secondary storage, or mass storage, for this database management system. In the present embodiment, the magnetic disk drives are composed of proven commercial products such as Winchester technology, so that the cost per byte is very low, large capacity and high reliability. Sex storage device.

In these disk drives 38 to 43, a relational database is stored in a distributed storage manner.
This is shown in simplified form in FIG.
Each processor and its associated disk drive is assigned a number of records that form a subset of the database, the subset being "primary".
Subsets, and their primary subsets are disjoint subsets and together constitute a complete database. Therefore, each of the n storage devices will hold 1 / n of this database. Each processor is further assigned a subset of backup data, and these backup subsets are also disjoint subsets, each of this database
It constitutes 1 / n. As can be seen from FIG. 22, each of the primary files is duplicated by a backup file contained in a processor different from the processor containing the primary file,
This allows the two to be distributed in different ways.
Each one has a complete database. As described above, the integrity of the database is protected by the redundancy of the primary data subset and the backup data subset. This is because of a single failure. If there is, it is impossible to have a substantial effect on a plurality of data over a large number of blocks or a plurality of relations forming a plurality of groups.

The distribution of the database is also related to the hashing operation of the various files, as also shown in FIG. 22, and also to the incorporation of hash mapping data into the message. ing. The files contained in each processor are represented by a simple hash bucket, shown as a group of binary sequences.
ucket). Thus, based on the relational tables specified by those buckets, the relational database
Relations in the system and table (pair: t
You can define where the uple) should be placed. Using the hashing algorithm, this relational
Within the database system, assignment of buckets is required from the key, so that the database system can be easily expanded and modified.

The size of the storage capacity to be selected depends on the database management needs, the amount of transactions, and the processing power of the microprocessor associated with the storage device. Multiple disks
Connect the drive to one AMP or one disk
It is possible to connect the file device to multiple AMPs, but such modifications would typically be limited to special applications. Database expansion is typically performed by expanding the number of processors (and the number of disk drives associated with the processors) in a multiprocessor array.

Active Logic Networks The purpose of providing an orderly flow of message packets and the purpose of facilitating the execution of tasks are:
It is achieved by employing a unique system architecture and message structure centered around the novel active logic network construct 50. The active logic network construct 50 comprises a plurality of bidirectional active logic nodes that form an ascending hierarchy for the outputs of the microprocessors, converging the outputs as they climb the hierarchy. logic n
ode) 54. Those nodes 54
Consists of a bidirectional circuit with three boats, which is a tree network.
work: a network having a tree-like structure), in which case it is connected to the microprocessors 14, 16 and 18-23 at the base part of the tree structure.

As will be appreciated by those skilled in the art, a node is a logic
It can be provided when the number of sources is more than two, for example four or eight, in which case the problem of increasing the number of source inputs at the same time also translates into a problem of adding additional combinational logic. You can do it.

All nodes (N) for easy reference
Among them, those belonging to the first hierarchy are represented by the prefix "I", those belonging to the second hierarchy are represented by the prefix "II", and so on. Individual nodes belonging to the same hierarchy are indicated by the subscript "
_{, 1} , _2, ... ", and therefore, for example, the fourth node of the first hierarchy can be expressed as" IN ₄ ". "C port" on the up tree side (that is, upstream side) of the node
It has one port named
The port is connected to one of two down tree ports of a node belonging to the adjacent higher hierarchy, and these down tree ports are named "A port" and "B port", respectively. ing. These hierarchies converge to a top node, or vertex node 54a, which reverses the flow direction of upstream directed messages (up-tree messages) to downstream ( It functions as a means for convergence and turning in the direction of the down tree. Two sets of tree networks 50a, 50b are used, the nodes in the two sets of networks and the interconnections being arranged in parallel with each other, thereby obtaining the desired redundancy for large systems. ing. Since the nodes 54 and their networks are identical to each other, it is sufficient to describe only one of these networks.

For the sake of simplicity, it should be first understood that a large number of message packets, in the form of a serial signal stream, are connected to the active logic network 50 by a number of microprocessor connections. Are transmitted at the same time or can be transmitted at the same time. Multiple active logic nodes
54 operates on a binary basis to determine the priority between two conflicting conflicting message packets, each of which uses the data content of the message packets themselves. It is done. Furthermore, all nodes 54 in a network are under the control of one clock source 56, which synchronizes the sequence of message packets towards the vertex node 54a. Combined with those nodes 54 in such a way that they can proceed. In this way, an incremental segment, such as each successive byte, in the serial signal sequence is advanced to the next layer, and the progress of this byte is determined by the byte corresponding to that byte in another message. This is done at the same time as following another route in the network 50.

Sorting to give priority between competing signal sequences is performed on message packets traveling in the up tree direction, and ultimately downstream from vertex node 54a. A single message sequence to be redirected is selected. Since the system is configured as described above, it is not necessary to determine the final priority at a certain specific point in the message packet. The transfer of the message can be continued without requiring anything other than a binary-based decision between two conflicting packets. As a result, the system spatially and temporally selects messages and transfers data, provided that it gains control of the bus and identifies the transmitting or receiving processor. Nor does it delay message transmission for the purpose of performing handshaking operations between processors.

It should also be noted that if several processors transmit the exact same bucket at the same time, if the transmission is successful, it is the same as if all of the transmitting processors were successful. That is to say. This property is extremely useful for effective control of large multiprocessor complexes, as it saves time and overhead.

Node 54 also operates in a bi-directional manner, allowing undisturbed distribution of message packets downstream. At a given node 54, downstream messages received on port C located on its up tree side are distributed to both port A and port B located on the down tree side of this node, and Is transferred to both of the two nodes belonging to the adjacent lower hierarchy connected to this node. Under the control of the common clock circuit 56, the message packets are synchronously advanced in the down tree direction, and are simultaneously broadcast to all microprocessors, whereby one or more The processor is enabled to perform the desired processing task or to accept a response.

The network 50 has a higher data transfer rate compared to the microprocessor data transfer rate, and is typically more than twice as fast. In this example, the network 50 has 120 nanosecond bytes
It has a clock interval, and its data rate is five times that of a microprocessor. Each node
Each of the three ports 54 is connected to a port of a node belonging to an adjacent layer connected to the node or to a microprocessor, and this connection is 1
A pair of data lines (ten in this embodiment) and control lines (two in this embodiment) are provided, and the two control lines are respectively a clock signal and a collision signal (collision signal). Assigned to data·
The line and the clock line are wired so as to form a pair, and are set as separate lines in the up tree direction and the down tree direction. The collision line propagates only in the down tree direction. The above connection configuration forms a full-duplex data path so that no delay is required to "invert" the driving direction of any line.

Referring now to FIG. 3, the ten data lines include an eight-bit byte represented by bits 0-7, which occupy eight of the ten data lines. is occupying. Another line, denoted C, is a control line, which carries a control sequence used to specify different parts of the message packet in a particular way. The tenth bit is used for odd parity in this embodiment. As will be appreciated by those skilled in the art, the system may increase or decrease the number of bits in the above data path, and may easily operate with such a change in the number of bits.

The byte sequence (sequence of bytes) is arranged to form a series of fields, and is basically divided into a command field, a key field, a destination selection field, and a data field. .
As will be described in more detail below, the message may use only one field and terminate with a detectable "end of message" code. The "idle field" between the messages is C
Represented by an uninterrupted series of "1" on the line as well as on lines 0-7, it is being transferred whenever no message packet is available. Parity lines are also used to uniquely communicate changes in the status of individual processors.

An "idle state" is an intervening state between messages and is not part of a message packet. A message packet usually starts with a 2-byte command word containing a tag, which is in the form of a transaction number (TN) if the message is a data message, and the message is a response. If it is a message, it is in the form of the originating processor ID (OPID). Transaction numbers have different levels of significance in the system and serve as the basis for many types of functional communication and control. After the command word, the packet may contain either or both of a variable length key field and a fixed length destination selection word (DSW), which may contain variable length data. -It is the first part of the field. The key field serves the purpose of providing a criterion for mating between messages when the messages are otherwise identical to each other in other parts of the key field. The DSW provides the basis for a number of special features and deserves special attention along with the TN.

The system operates using a word-synchronized interface, in which all processors attempting to transmit a packet send the first byte of the command word to the network simultaneously.
It is designed to be sent to. The network uses the data content of the fields that follow to sort at each node on a binary basis, with the lowest numerical values being given priority. Of the consecutive data bits, if bit C is considered to be the largest quantity and bit 0 is considered to be the smallest quantity, the sorting priority is as follows:

1. First sent to network 50, 2. Command code (command word) with minimum value, 3. Key field with minimum value, 4. Key field with shortest 5. The one with the smallest data field (including the destination selection word), and the one with the shortest data field.

In view of the purpose of explaining the overview here, it should be noted that if the priority is determined at the node 54, a collision display (= collision display, hereinafter referred to as Acol or Bcol) Is returned to the route that received the transmission of the loser in the determination of the priority. By this collision display,
The transmitting microprocessor is aware that network 50 has been aborted because it is being used for higher priority transmissions and therefore will have to try again later. You can

Simplified examples are shown in the various schemes of FIG. In this embodiment, the network 50 operates in cooperation with a high-speed random access memory arranged in a tree structure using four separate microprocessors. More specifically, IFP14 and three AMPs 18, 19 and 20
And. Each of the sub-figures 2A, 2B,.
It corresponds to one of ten consecutive time samples from t = 0 to t = 9, and at each of those times, a different one sent from each of the microprocessors in this network. Fig. 3 illustrates aspects of the distribution of a simplified (four character) serial message, as well as the state of communication between the port and the microprocessor at various times. The drawing, which is merely labeled as FIG. 2, shows the state of the system before the start of the transmission of signals. In each of the above figures,
In order to be in the null state (zero state), that is, the idle state, it is assumed that the transmission represented by “□” must be performed. Since there is an agreement that the data content that takes the minimum value has priority, the message packet "EDDV" sent from AMP19 in Fig. 2A.
Is the first message packet transmitted through the system. Each message in the figure is held within a high speed random access memory (sometimes referred to as HSRAM) in a microprocessor, as described in more detail below. The HSRAM 26 has an input area and an output area, which are schematically shown in FIG. 2, and a packet has a FIFO (first-in first-out) state in this output area at time t = 0. They are arranged vertically side by side in a manner so that they can be taken out at the time of transfer as indicated by the arrow for the cursor written in the HSRAM 26 in the figure. At this point, all transmissions in network 50 are in a null or idle (□) state.
Is shown.

On the other hand, at time t = 1 shown in FIG. 2B, the leading bytes of each message packet are sent to the network 50 simultaneously with each other, and at this time, all the nodes 54 still show the idle state indication. Has returned
All transmission states above the first layer are also in the idle state. During the first clock interval, the first byte of each message is the lowest node IN
_It is set inside ₁ and IN ₂ , and at t = 2 (2C
Figure) The conflict is settled, and both the upstream transmission and the downstream transmission are performed in succession. Node IN
₁ is receiving an "E" on both of its input ports and is forwarding it upstream to the next layer,
In the downstream direction, an undetermined state is displayed for both transmission processors. However, the node IN ₂ belonging to the same hierarchy determines the priority in the case of a collision between “E” from the processor 19 and “P” from the processor 20 by assigning priority to “E”. Is determined to exist, and the port A is moved to the port C on the up tree side.
While returning a Bcol signal to the microprocessor 20. When Bcol signal is returned to the microprocessor 20, IN ₂ node in practice, will be the A input port is locked to the C output port, whereby the vertices serial signal string from the microprocessor 19 nodes II
It will be transmitted to N1.

In the IN ₁ node, the first two letters are both "E
D ”, and as a result, as shown in FIG. 2C, it is impossible to make a decision at the time t = 2 at this node. Furthermore, three microprocessors 14, 15 and
The common leading character "E" sent from 19 is t = 3
When the IIN1 vertex node is reached at time (Fig. 2D) and this letter "E" is transferred to this vertex node IIN1 the second letter "D" which is also common to all of them The transfer direction is reversed and directed to the downstream direction. Although at this point is in a state not Kudase the determination node IN ₁ is still, however, at this time, the third character "F" in each of a series of microprocessors 14, 18 and 19, "E" and "D "it is being transmitted to the node IN _1. The fact that the microprocessor 20 receives the Bcol signal means that this processor 20 has been defeated in the competition for the priority, and therefore the processor 20 shows an idle indication (□) if it receives the Bcol signal. Is transmitted, and thereafter, only this idle display (□) is transmitted. The respective cursor arrows written in their respective output buffers indicate that microprocessor 20 has been returned to its initial state while the other microprocessors continue to send a continuous series of characters. Therefore, the important event at time t = 4 (FIG. 2E) is that a determination is made regarding the port of node IN1 and that the _first character ("E") is the first character through all lines. That is, the data is inverted and transmitted toward the node hierarchy of the hierarchy. At the time of t = 5 (Fig. 2F), the second collision is displayed, and in this case, the B port of the node IIN ₁ wins the competition and Acol is generated.

During the next few clock times, the downstream serial stream is continuously broadcast,
At time t = 6 (Fig. 2G), the first character of the message is set in the input area of all HSRAM 26. Another thing to keep in mind here is that
Node determination of priority made previously in IN ₁ is that it is invalidated at this point, because, third letter sent from the processor 18 ( "E") of the microprocessor 19 The third sent by
This is because, when the competition with the th character ("D") is lost, Acol is displayed from the nodes IIN1 in the higher hierarchy. As indicated by the cursor arrows in FIG. 2H, microprocessors 14, 18 and 20 have been returned to their initial state, and the winning microprocessor 19 has all transmitted at t = 4. Already completed at time. As can be seen from FIGS. 2H, 2I, and 2J,
Priority messages “ED
DV ”will be loaded. At t = 8 (Fig. 2I),
This message has already flowed out of the first hierarchy, and the vertex node IIN ₁ is already reset at t = 7, which means that the last downstream character has been transferred to the microprocessor. This is because only idle signals are already in competition with each other. At time t = 9 (Fig. 2J), the nodes IN ₁ and IN ₂ belonging to the first layer are reset, and
The defeated microprocessors 14, 18 and 20 all decide to re-contend for priority on the network by sending the first character of the message when the network again indicates idle. Become. In fact, as will be explained later, an acknowledgment signal is transmitted to the winning microprocessor.
This is not essential for the most generalization of the invention.

After the message has been broadcast to all microprocessors in this way, the message
It is utilized by any of those microprocessors or by all of them as needed. How many microprocessors are used depends on the mode of operation and the function to be executed, and there are various variations in the operation mode and function.

(Global Intercommunication and Control) The example described above as a way for the network to give priority to one message in a group of conflicting messages is for the transfer of primary data messages. is there. However, complex multiprocessor systems need to utilize many other types of communications and commands to provide the good efficiency and versatility required today. Key functions that must be provided include, in addition to the transfer of primary data, what can be broadly referred to as multiprocessor modes, acknowledgments to messages, status indications, and control signals. I have. The following sections discuss, from a global perspective, how the various modes and messages cooperate with a sorting and communication network that performs sorting and communication for prioritization, i.e., multiprocessor systems. It presents an overview described from a system perspective. For a more detailed understanding, please refer to FIGS. 8 and 13 and the following description of those figures.

In the broadcast or broadcast mode, the message is delivered to all processors simultaneously, without explicitly stating the particular receiving processor or processors. This mode is typically used for responses, status queries, commands,
And control functions.

If the receiving processor needs to be specified, the redirection information contained in the message packet itself will accept or reject the packet locally (= in individual processors). Criterion for judging is provided. As an example, the interface logic inside the receiving processor module may, according to the map information stored in the high-speed RAM 26, cause the data of the packet to fall within the range of the particular processor in which the interface logic is incorporated. Identify if it is included. By variously setting the map bits in the high-speed RAM, the criteria for various selection schemes can be easily set, including, for example, the selection of a particular receiving processor, ("hashing" Selection of a portion of the stored database, selection of a logical process type ("class"), and so on. The use of broadcast with local access control (= access control performed on individual processors) is particularly beneficial for database management systems, which are widely distributed and require little overhead software. Access to any part of the relational database or distributed local copy of any of a plurality of globally known logical processes. Therefore, this system can specify and select one transfer destination processor as a transfer destination of a message, and can also specify and select a plurality of resources belonging to one class. Level database queries often involve cross-references between different parts of the database,
It requires a consistent reference for a given task. The transaction number (TN) embedded in the message can be of various attributes, among others, providing the identity and reference of such a global transaction. A large number of tasks can be concurrently processed by local processor modules (local processor modules) that operate asynchronously with each other, and each task or subtask is processed by an appropriate TN. Is to have. By using various combinations of TN, DSW (destination selection word) and commands, virtually unlimited flexibility is achieved. Extensive sort / merge operations for a large number of tasks whose allocation and processing are done asynchronously.
ration) can be applied. TN
Can be assigned and abandoned, and the merge operation can be started and stopped. Certain messages, such as continuation messages, may have priority over transmission of other messages. By using a TN and a local processor that updates the status for that TN, only one
Only one query can determine the status of the global resource for a given TN. Distributed updates can also be achieved with a single communication. The system of the present invention allows all of the above functions to be performed without extending the software or significantly increasing the overhead burden.

The consequence of using the present invention is that a multiprocessor system with a much larger number of processors than would normally be found in the prior art.
The system can be operated very effectively for the task in question. Microprocessors are now inexpensive, and systems that perform well in problem areas are simply called "raw" power ("raw" power).
It is possible to realize a system in which power is not only high performance.

A consistent priority protocol covering all message types and various subtypes has been defined to encompass all of the various messages that are provided to the network. Response message, status
Messages, as well as control messages, are different types of messages from primary data messages,
They likewise utilize the contention / merge operations of the network and are thereby given priority while being transferred.
The response message in this system is a positive response (AC
K), Negative Acknowledgment (NAK), or an indication that the processor does not have the resources to do meaningful processing for the message ("not applicable processor" -NAP ). NAK
The response may be of any of several different types indicating a lock condition, an error condition, or an overrun condition. There may be only one source processor or multiple source processors,
The response message is given a higher priority than the primary data message because the originating processor needs such a response after finishing sending the message.

The system further uses a SACK message (status acknowledgment message), which is a readiness status of one local processor for a particular task or transaction (what operations can be performed). It indicates the readiness state). The contents of this SACK response are updated locally (= in each processor, that is, in the local processor) and kept accessible to the network. Such a SACK response is combined with the merge operation of the network to provide a global status report with a single query for a given task or transaction. Since the status response follows the priority protocol, the response with the smallest data content among the responses related to one transaction number automatically takes priority, whereby the lowest readiness state becomes the global system state. And this is done by a single uninterrupted operation. Further, such a SACK indication may be used with certain primary messages, thereby setting various protocols, such as system initialization and lockout operations.

The priority protocol for the various message types is first defined for the command code, which is the first of the command words at the beginning of each message and response, as shown in FIG. Are used. This allows for sufficient distinction between message types and subtypes, although it is possible to have more levels of distinction. As can be seen from FIG. 11, in this embodiment, the SACK response is 7
The two different status levels are distinguished (and also provide criteria for priority determination). In the case of a response message, a tag in the form of a 10-bit OPID follows the above 6 bits (see FIG. 3). Both TN and OPID can function as different sorting criteria, and the reason is
This is because these TN and OPID have different data contents inside the tag area.

After each primary message has been transmitted over the network, the interface part of all processors, even if it is a NAP, will generate a reply message anyway. The response messages also compete with each other on the network, so that a single or common winning response message is broadcast to all processors. The lost message packet will be tried again at a later time, but again after a very short delay, thereby ensuring that the network is used substantially continuously. . If multiple processors send ACK responses, those ACK responses will be sorted based on the OPID.

With the invention, the result is that the starting and stopping and control of tasks as well as the querying of tasks can be carried out by a very large number of physical processors and with little overhead. This is
This allows the raw power of multiple processors to be used effectively for handling problem conditions, since this low power is devoted to coordination and control of the system. This is because an extremely small amount is required. Coordination and control overhead are fundamental constraints on the efficiency of any distributed processing system.

For the purpose of global control (that is, control of the network), various types of control communication are used. Accordingly, the "Merge Stop", "Status Request", and "Merge Start" messages, messages for allocating certain tasks, and messages for abandoning certain tasks have the same format as data messages. Therefore, those messages are also referred to herein as primary messages. These control messages also contain the TN, and are located in place in the priority protocol. This will be explained later with reference to FIGS. 10 and 11.

The term "global semaphore buffer system" was used earlier because the high speed random access memory 26 and control logic 28 shown in FIG. This is due to the fact that it plays an important role both in the two-way communication of instructions. This global semaphore
The buffer system provides access duplication, which means that both the fast-running network structure 50 and the slower-running microprocessor can send messages, , Control or status indications can be referenced without delay and without the need for direct communication between the network and the microprocessor. To achieve this, the control logic 28 connects the memory 26 to the network 50 and the microprocessor in a time multiplexed manner with interleaved woed cycles. As a result, it is the same as creating separate ports that can commonly access the memory 26. The global resource, i.e., network 50 and the plurality of microprocessors, use the transaction number as an address locator that locates the portion of memory 26 that is allocated to store the status of the transaction. be able to. Local level (=
At the individual processor level), the status of the subtasks for a given transaction, including all kinds of available states, is updated inside the memory 26 under the control of the microprocessor, and the control logic
Locking to the buffer system is performed by 28. By using one of seven different ready states, entries can be conveniently retrieved from different dedicated portions of memory 26. When an inquiry is received from the network, the status of the processor is communicated (ie the "semaphore" is read) and a priority decision is made in the network, with the degree of completion being determined. The lowest readiness state has gained priority.
With the above-described configuration, a quick hardware response from one processor to one query can be obtained. Therefore, it is possible to know without delay and without using software whether or not execution of all of a plurality of distributed subtasks relating to a given task has been completed. Further, in this system, any of the communicating processor modules can assign a transaction number.
This transaction number assignment is the act of assigning an available transaction number for use in messages or for use within each global semaphore buffer system.

The preferred embodiment of the combined use of transaction identity and status indication is that each of the multiple processors sends out all messages related to a given criterion in order. There is a composite merge operation that requires If it is a system according to the prior art, each processor first receives its task and completes its processing, and then uses the result of that processing as a sort of "master" to perform the final merge operation. It would have to take the form of forwarding to the processor. Thus, the master processor is a significant bottleneck to the efficiency of the system.

If the global readiness state establishes that all of the affected processors are in a ready state, the messages with the highest priority in the memory 26 provided for each processor are sent to the network simultaneously with each other. The messages are then prioritized during the merge as described above. Successive retransmission attempts are made for a number of groups of messages, resulting in multiple messages ordered from highest to lowest priority for the transaction number, ending with the lowest priority. A serialized message sequence is generated, with things coming. According to a special command message, this system allows the merge operation to be stopped midway and restarted midway, so that multiple merge operations that are in the middle of execution at the same time can be executed. The state in which the network 50 is shared can exist so that the resources of the system can be used extremely effectively.

Therefore, at any time, this network
All of the active processors connected to 50 are capable of performing operations on messages related to various transaction numbers asynchronously with each other. If the same transaction number or "current" transaction number is referenced by one status inquiry, all processors respond synchronously to each other with one of the available status levels. . For example,
The "START MERGE" message causes a test (= investigation) of the global semaphore specified by a particular transaction number, and if the global state resulting from this test is "Ready" If it is in the state (that is, if it is either “SEND READY” or “RECEIVE READY”), the current transaction number (present tran)
(saction number: PTN) is set equal to the transmitted TN value included in this “merge start” message. (If the global state resulting from the test was not the "ready" state, the value of PTN is "TN0 (this means that the transaction number (TN) is" 0 ")." Will be returned to the value).

In addition, the "STOP MERGE" message,
Resets the current transaction number to “0”. In this way, "TN0" is a message (point-to-point) from one processor to another.
Used as the "default" value transaction number used for the two-point message). In other words, this "TN0" specifies the operation of the "non-merge" mode.

This global intercommunication system uses the message structure shown in FIGS. 3A, 3B, 3C, and 11 and the high speed random access memory 26 structure shown in FIG. And the one shown in FIG. A more detailed description will be given later in connection with FIGS. 5, 7, 9 and 13.

As can be seen from FIGS. 3A to 3C and FIG. 11, the command code used for the response is from 00 to 0F (hexadecimal), and the command code used for the primary message is 10 (16). Radix) to larger values. Therefore, the response has priority over the primary message, and the smallest value comes first in the arrangement order shown in FIG.

One dedicated storage area inside the high-speed RAM memory 26 "(FIG. 8) (the area described as" transaction number "in FIG. 8) is a word format (the seven types of readiness described above) in FIG. State, TN assigned state, and TN unassigned state). Among other dedicated parts of this memory 26 "include a circular buffer for input (received messages) and a storage space for output messages. The separation area is used as a message completion vector area, and this area allows a pointer to be placed on an output message that has been transmitted, thereby effectively utilizing storage space for the output message. It has become.

As can be seen, for the memory 26 and the control logic 28, their queuing and data buffering functions are certainly important, but together with them, global transactions can be performed individually. Multiple co-operation, which is decentralized with respect to the processor, is of particular importance.

(Active Logic Node) In each of the two networks provided with redundancy, each of the plurality of active logic nodes 54 in FIG. 1 has the same configuration as each other, except that Only the direction reversal node 54 at the top of each network does not have an upstream port, but instead has a mere signal reversal path for reversing the direction downstream. As shown in FIG. 4, one node 54
It can be largely divided into two groups based on function. One of these functional groups relates to the transmission of messages and collision signals (collision numbers), the other relates to the generation and retransmission of common clock signals. The clock signals are synchronized so that there is no skew between the respective clock signals at different nodes, ie, zero skew. The two functional groups are not independent of each other, because the zero skew clock circuit forms an important part of the signal transmission system. Both word clock (consisting of two serial bytes) and byte clock are used. Specifically, it is necessary to control the active logic node 54 externally, either when setting or resetting the state of the active logic node 54, or when setting different operating modes. No such control is actually performed. Furthermore, because each node 54 has the same structure as each other, it is possible to mass-produce those nodes using modern IC technology, thereby increasing the reliability and increasing the cost. Can be reduced.

Each of the "ports" of A, B and C referred to above each has ten input data lines and ten output data lines. For example, at the A port, the input line is represented by AI and the output line is represented by A0. One "collision" line (i.e., "collision" line) is used for each port along with the upstream clock line and the downstream clock line (e.g., Acol is used for port A). ). The respective data lines of the A port and the B port are connected to a multiplexer 60, which is the preferential word of two words competing with each other.
Or (if their competing words are identical to each other)
The common word is switched and connected to the up register 62 connected to the upstream port (C port) as the data signal C0. At the same time, the downstream data transmitted from the higher hierarchical node and received at the C port is shifted into the down register 64 and shifted out therefrom, and the A port and the B port Occurs as output to both.

One of the serial upstream streams of bytes can be blocked, however, without causing any extra upstream or downstream delay, and the multiple words are: word·
Under the control of the clock as well as the byte clock, it proceeds through the up register 62 and the down register 64 in a continuous sequence.

Conflicting bytes supplied to the A port and the B port at the same time are detected by the first and second parity detectors 6.
6 and 67, and also sent to a comparator 70. The comparator 70 obtains a priority based on the eight data bits and one control bit so that the data content of the minimum value takes priority. To determine the priority. In the priority determination protocol, the "idle" signal, that is, the signal when no message is present, is a continuous "1" sequence. Parity errors can be caused by typical causes, such as the presence of excessive noise, or by any other factors that affect signal transmission or circuit operation. However, in the system of the present embodiment, the parity error indication is also used for another important application. That is, each time a microprocessor transitions to an inoperative state, the transition is marked each time, and this marking is such that all output lines, including the parity line, are high (i.e., the value is "1"). ) So that an odd parity error condition is thereby generated. This parity error indication is transmitted as a "marker" in the network if one error occurs, which allows the system to identify that a change has occurred in the global resource and to indicate that the change has occurred. You can start a procedure to determine what it is.

The pair of parity detectors 66 and 67 and the comparator 70 supply a signal to a control circuit 72. The control circuit 72 includes a priority message switching circuit 74, and determines the priority. If so, the multiplexer 60 is configured to lock the multiplexer 60 to one of two states in response to the output of the comparator 70, and to generate and propagate a downstream collision signal. Is configured. The name of the transition parity error propagation circuit 76 is because it forces the parity error state in the network described above, in which all lines are simultaneously "1". Reset circuit
Reference numeral 78 denotes an end of message (EOM) for returning the node to an initial state.
Includes detector 80.

In order for the functions described above and those described below to be performed, each active logic node may perform these functions using a microprocessor chip. However, they can be more easily implemented by performing their functions in accordance with the state diagram of FIG. 5 and the logical equations described below. In the state diagram of FIG. 5, the state S0 represents the idle state, and the state in which the determination is not made that one port has priority over the other port because the messages competing with each other are the same. It represents. S1 state and S2
The states are a state in which the A port is prioritized and a state in which the B port is prioritized, respectively. Therefore, if the BI data content is larger than the AI data content and no parity error exists in the AI, or if there is a parity error in the BI (these AIs have a parity error). The condition that the parity error does not exist and the condition that a parity error exists in BI are denoted by ▲ ▼ and BIPE, respectively, and are represented by the state of the flip-flop. . AI and BI
The logical state (logical condition) opposite to that described above exists as a state (condition) in which the device should transition to the S2 state. If a higher layer node issues an indication that a collision has occurred in that hierarchy, that indication will be sent back as COLIN in a downstream signal. This device has the S0 state, S1 state,
Regardless of which of the two states S1 and S2 are in, the state shifts to the state S3, and this collision signal is transferred downstream as Acol and Bcol. S1 state or S2
When the node is in the state, since this node has already made a decision, the collision signal is sent downstream to the (two) nodes in the lower hierarchy in the same manner,
At this time, the priority message switching circuit 74 is locked to the A port or the B port depending on the situation.

The reset circuit 78 includes an EOM detector 80, which is used to reset the node from S3 to S0 (fifth node).
(Figure) is performed. The first reset mode is the end of message (EO) terminating data field in the primary message as shown in FIG.
M) field is used. Using a group of flip-flops and gates, the following logic state is created.

URINC ・ URC ・ URCDLY where URC represents the control bit in the up register, URINC represents the value of the control bit in the input signal input to this up register, and URCDLY is the up register delay. It represents the C value (= value of control bit) in the flip-flop.

As shown in FIG. 6, a bit pair (bit pair) in which two consecutive bits in a sequence of control bits are set as one set
Specify some fields and also indicate the transition from one field to the next. For example, "1" used at idle
From the control bit state that is followed only by "0, 1" bit
The transition to a sequence (= bit pair) specifies the start of a field. This "0,1" sequence is used to identify the start of the data field. The subsequent string of "1,0" control bits indicates an internal field or subfield, and the end of message (EOM) is identified by the "0,0" control bit pair. Is done. "1,
The state where the bit pair of “0, 0” comes after the string of the bit pair of “0” is a unique state and can be easily identified. The URINC signal, the URC signal, and the URCDLY signal are ANDed together, and each of these signals is delayed from each other by one byte clock. The waveform of the signal resulting from these ANDs is high until the beginning of the message packet, turns low at this start, and while this data (= message packet) continues,
The waveform stays at a low level. This waveform shows two byte clocks after the EOM is generated
Return to high level. EOM is detected by this transition in which the waveforms URINC, URC, and URCDLY turn positive. As shown in FIG. 5, this positive transition causes S1 or S2
The operation of returning from S0 to S0 is triggered.

When a node in a higher hierarchy is reset, it becomes a ▼ state, indicating that the collision state has disappeared. This logic state initiates a return operation from S3 to the base state S0. It should be noted that this ▲ ▼ state propagates down the layers of the network 50 as they "run through" one after another. . As described above, each node can reset itself regardless of the length of the message. It should be further noted that, regardless of the initial state of the network, all nodes will be reset to the S0 state if an idle signal is provided.

The collision signal is returned to multiple processor modules. The modules store the collision state information and return to transmitting the idle sequence, the transmission of the idle sequence being performed while the processor winning the contention continues to transmit. I have. The processor is from COLIN ▲
As soon as the transition to ▼ is detected, a new transmission can be started. In addition to this, the processor determines that N is the number of layers in the network:
A new transmission can be initiated if the idle signal has been received for 2N byte clocks, such that such a situation is similar to the former situation. Because it indicates that no earlier transmissions remain in this network. According to the latter of these schemes for enabling new transmissions, a processor joining the network for the first time can enter into a message synchronization state with the network if the traffic is small, so that this initial Participating processors do not have to wait for polls from other processors to initiate intercommunication with other processors on this network.

The parity error state is described in the state diagram of FIG. 5 and is set according to the following logical equation.

PESIG = AIPE ・ ▲ ▼ ＋ BIPE ・ ▲
▼ If the logic state of this PESIG is true, the input signal URIN to the up register is (URIN O ... URIN 7, C, P
= 1 ... 1,1,1). To satisfy the above equation, the transition parity error propagation circuit 76 includes a flip-flop for the AIPE, that is, a parity error of the A input, and a delay flip-flop (AIPEDLY). The latter flip flop depends on the setting of AIPE,
The state is set one byte clock later than that. Therefore, regarding the A input, when the flip-flop for AIPE is set by a parity error, the PESIG value becomes high for one byte clock.
Level, so this PESIG signal
It is propagated only once when the first indication of an error is made. This same condition occurs when all of the data bits, control bits, and parity bits are all “1” values, but the transition described above for the state of the global resource occurs. This is the state that occurs when you do. This forces all lines to go high, forcing a state of all ones and establishing a total number even state (odd parity state), which results in the AIPE flip Flop and AIPE
The DLY flip-flop and are set to indicate a parity error. The above arrangement operates in a similar manner when the message packet received at the B port contains a parity error or a forced parity indication to indicate a status change.

Parity errors, caused by noise effects and other variables, usually do not affect the operation of the processor because they use redundant dual networks. Is. Monitoring (monitor)
Indicator light (= indicator light:
(Not shown) is used to indicate the occurrence of a parity error. However, for a parity error that propagates only once indicating a status change, it initiates a routine to evaluate the significance of the change.

As shown in FIG. 4, the clocking system used for this node 54 has a skew between clocks at all node elements, regardless of the number of hierarchies used in the network. ) Is zero, i.e., to maintain a zero skew state. Clock circuit 86 includes first and second exclusive OR gates 88, 89, the exclusive OR gates of which are designated A and B, respectively.
The outputs of the gates are coupled by an adder circuit 92 such that a subtraction (ie, a "BA" operation) is performed therebetween, and the output of the adder circuit 92 is passed through a low pass filter 94. After that, it controls the phase of the output sent from an oscillator (PLO) 96, which is a phase locked loop.
The inputs to the first exclusive OR gate 88 are the output of this PLO 96 and the downstream clock supplied via the isolated drive circuit 97 from the adjacent higher level node element.
The line of this clock is labeled "Word Clock", which is obtained from a neighboring higher hierarchy after a known delay τ, and this same clock signal is now One isolated drive circuit
Through 98, it is returned to that node in the adjacent higher hierarchy. The input to the second exclusive-OR gate 89 consists of this word clock and clock feedback from the adjacent lower hierarchy, which in turn receives the signal from this PLO 96. .

The word clock line above is the third exclusive OR
Connected to the two inputs of gate 100, both of which are directly connected and the τc delay line
And 101 are connected. As a result, a byte clock signal having a frequency twice as high as that of the word clock and being in timing with the word clock is obtained.

The operation of the clock circuit 86 described above may be better understood with reference to the timing diagram of FIG. The clock out signal (clock output signal) is the output of PLO 96. Of course, the main purpose of this clocking system is to maintain a zero time skew condition between the clock output signals for all nodes in the network, so of course those clock outputs The signals must have their nominal frequencies also identical to each other. The delay τ due to the transmission line between the nodes is set to a substantially constant value, but the value of the delay itself can be set to a long time. If the method disclosed here is adopted, the byte clock speed of the network and the node should be as long as 28 feet (8.53 m) when the speed used in the actual system (120 ns) is adopted. It is possible. As one of ordinary skill in the art will readily appreciate, a network that is not fully populated with the maximum possible number of processor modules can be added with additional layers to increase the length of this 28-foot integral multiple. Can easily be obtained. In that case, the waiting time, ie the transmission time of the transmission made through the network, is correspondingly increased.

As shown by the waveform just below the clock out signal in FIG. 7, the word clock from the adjacent higher hierarchy has a waveform similar to the clock out signal, except that τ Just late. This word clock forms a fundamental timing reference common to all nodes, but it is possible that the leading edge of each clock out signal is controlled within the circuit. Since their leading edge can be preceded by a word clock, so that all nodes can be kept in sync. As can be seen with reference to waveforms A and B, the pulse A generated by the first OR gate 88 ends at the leading edge of the word clock, while the second
The pulse B generated by the OR gate 89 has a word edge at the leading edge.
Coincides with the leading edge of the clock. The trailing edge of this B pulse is located at the beginning of the feedback pulse from the adjacent lower layer module, and since this feedback pulse is delayed by τ, the B pulse has a constant duration. It has become. Clock circuit 86
Acts to keep the duration of pulse A the same as the duration of pulse B. The reason for doing so is that as the phase of PLO96 is advanced and synchronization is established, Output signal of circuit 92 (subtraction "BA")
This is because the signal that has performed) approaches zero. In practice, adjustments are made to the leading edge of the A signal, which may either lead or lag the preferred position, as indicated by the dashed line, so that the leading edge of the A signal is the word. It should be at a position that precedes the leading edge of the clock by time τ. At all nodes, if the leading edge of the clock out signal is located at this preferred nominal position, there will be a zero skew condition between word clocks. Thus, each processor connected to the network is free of the constraints on the total length of the path from one processor to another, but without delay accumulation and the difference in propagation time. It does not occur.

To generate a double frequency byte clock,
Words delayed by delay time τc by delay line 101
The clock is duplicated and this delay line 101 is also gate 100
Signal is supplied to Thus, as can be seen from the waveform labeled byte clock in FIG. 7, byte clock pulses having a duration .tau.c are generated at both the leading and trailing edges of the word clock. You. The generation of this pulse occurs twice during each word clock interval, and at all nodes in synchronization with the word clock. In the above description, the delays caused by the transmission lines between the nodes are almost the same no matter which direction the transmission is from layer to layer, so that in effect,
It is a natural assumption that all word clocks and byte clocks in this system are kept in a stable phase relationship with each other. Thus the byte clock generated locally (= inside individual nodes) is
At each node, it provides a clocking function for a 2-byte word (= word of 2 bytes) of a message for that individual byte.

The active logic node described above has potential advantages whenever it is desired to resolve conflicts between simultaneously transmitted message packets based on their data content. In contrast, for example,
U.S. Pat. No. 4,251,879, issued Feb. 17, 1981, entitled "Speed Independent Arbiter Switch for Digital Communication Networks"
for Digital Communication Nbiworks) ",
The aim is to determine which is the first received signal in time and uses an externally provided processing or control circuit.

(Processor Module) The individual processors illustrated in the schematic diagram of the entire system in FIG. 1 are interface processors (IFPs) 14 and 16 and access module processors (AMP) 18 to 18 respectively. 23 specific examples,
Also, these processors have been broadly subdivided into several key components. More detailed examples of the configuration of these processor modules (IFP and AMP)
There will be a correspondence between the functional rough subdivisions of FIG. 1, but not only that, but also a significant number of further subdivisions. As used herein, the term "processor module"
FIG. 8 refers generally to the assembly illustrated in FIG. 8, which may include any of the optional elements described below to enable it to function as either an IFP or an AMP. . Also, the term "microprocessor system" refers to a system 103 that includes a microprocessor 105, where the microprocessor 105 is, for example, an Intel 8086.
Type (Intel 8086) 16-bit microprocessor. The address bus and data bus of this microprocessor 105 are the same as those of the microprocessor system 103.
Is connected to a general peripheral system such as a main RAM 107 and a peripheral device controller 109. The peripheral device controller 109 has a processor module of AMP and a peripheral device of disk / disk.
This is shown as an example that can be used when the drive 111 is used. On the other hand, if the processor module is to act as an IFP, the controller or interface may be replaced by a channel interface, for example, as shown in the dashed rectangle. Such an exemplary IFP provides communication with a host system channel or bus. Since conventional general controllers and interfaces can be used for the microprocessor system 103, it is not necessary to describe those controllers and interfaces in further detail.

It should be noted that the use of one disk drive per microprocessor can indicate a cost and performance advantage.
The advantage of such a scheme is generally true for databases, but sometimes it is necessary to configure the microprocessor such that one microprocessor can access multiple secondary storage devices. Can be beneficial. In the schematic diagram, other commonly used subsystems are not shown for simplicity. The omitted subsystem is, for example, an interrupt controller or the like, and the interrupt controller is supplied by a manufacturer of a semiconductor for use in combination with its own system. Those of ordinary skill in the art will also appreciate the importance of taking appropriate measures to supply power to the processor modules that can maximize the redundancy and reliability that the present invention can provide. Will be understood.

Peripheral controller 109 and channel interface, shown as optional elements in microprocessor system 103, correspond to the IFP interface and disk controller in FIG. On the other hand, the high-speed RAM 26 of FIG. 1 actually comprises a first HSRAM 26 'and a second HSRAM 26 ", each of which functions by time multiplexing (time multiplexing). From above is a de facto 3-
It is a port device, and is connected to the microprocessor bus system via one of the ports (the port indicated by “C” in the figure). Each of the HSRAMs 26 ', 26 "cooperates with a first or second network interface 120, 120', respectively, so that each has a first and second network interface.
50a and 50b (these networks are not shown in FIG. 8), input (receive) port A and output (transmit)
Communication is performed via the port B. Since the two systems are redundant with each other, the second network interface 120 '
And the second HSRAM 26 "need only be described in detail. For the network interfaces 120, 120 'the first
Although shown and described in more detail in connection with FIG. 13, they can be divided into the following four main parts if they are largely subdivided.

10 input lines from the second network 50b
An input register array / control circuit 122 connected to the A port of HSRAM 26 "via the interface data bus and interface address bus.

An output register array / control circuit 12 connecting the output lines to the second network 50b to the interface data and interface address buses and the B port of the second HSRAM 26 ".
Four.

A microprocessor bus interface / control circuit 126 connected to the interface address and interface data buses and to the HSRAM 26 ″ A and B ports.

A clock generation circuit 128 that receives a word clock from the network and generates a plurality of clocks synchronized with each other and in an appropriate phase relationship for controlling the interface 120 '.

Second network interface 120 'and HSR
AM26 ″ coordinates with the microprocessor system 103 to coordinate the transfer of data between a fast-running network and a slower-running processor compared to it. It also serves the function of queuing messages exchanged between different systems (= network system and processor system).
The bus interface / control circuit 126 can be said to be for performing (read / write function: R / W function) in cooperation with the microprocessor system, and the microprocessor system includes ( HSRAM2 (at least if it is an Intel 8086)
6 "and the ability to receive data from the HSRAM 26".

The structure of IFP and that of AMP are similar in their actions, however, HSRAM26 ″
There may be a considerable difference between IFP and AMP regarding the size of the input message storage area and the size of the output message storage area inside. In relational database systems, the IFP uses a large input message to receive new messages from the high speed network inside the HSRAM26 ″ in order to constantly utilize the network to meet the requirements of the host computer. Has storage space, and vice versa for AMP, where more storage space must be available for processed message packets to be sent to the high speed network The HSRAM 26 "also operates in cooperation with the main RAM 107 in the microprocessor system 103, which main RAM 107 comprises a message buffer section for each network.

Main R for microprocessor system 103
The manner of allocating the system address space inside the AM 107 is shown in FIG. 9, which will be briefly described. According to a general method, the address allocated to the system random access function by leaving the space for expansion used when the storage capacity for random access is increased, and the I / O address space And ROM and
And an address space allocated for the functions of PROM (including EPROM). In addition, some portions of the system address space may be used for message packets coming from the first and second high speed RAMs 26 ', 26 ", respectively, and for message packets going out to those high speed RAMs. This allows for great flexibility in the operation of the system, even though the microprocessor 105 can address the HSRAM 26 ″, by virtue of the action of the main RAM 107. This is because it is possible to hardly be restricted by the interdependency between software and hardware.

Referring again to FIG. 8, as already mentioned,
HSRAM26 ″ which can be accessed from two directions
Controls multiprocessor mode, distributed updates,
And configured to perform core functions in managing the flow of message packets. To accomplish these and other objectives, the HSRAM 26 "is divided into a number of different internal sectors. The relative arrangement of the various sectors shown in FIG. Specific addresses specifying the boundaries of those sectors, which are employed in all of the individual processor modules in the system, indicate the addresses used in an actual system. It should be noted that the size of these memory sectors and their relative placement can vary greatly depending on the specific system situation. In the example shown, a 16-bit memory word is employed.The selection map and response directory are dedicated look-up types of a type that need only be written once during initialization. The transaction number section provides a dynamically revisable (= contents can be changed many times during operation) lookup table. I have.

The memory section of the selection map starts at location 0, but in this example there are basically four different maps used within this memory section, which maps are mutually exclusive. It is used in a method related to. The destination selection word (destin) contained in the message packet
ation selection word (DSW) is used in conjunction with a dedicated selection map in HSRAM26 ″. This destination selection word consists of a total of 16 bits, and 12 of those bit positions. It contains a map address that occupies and map selection data that occupies the other four bits.The first 1024 16-bit memory words of HSRAM each contain four map address values. Includes maps for all four maps with one memory access to HSRAM according to the address values specified in DSW.
The bits are obtained, while the map selection bits contained in the DSW determine which map to use.

FIG. 15 shows the conceptual structure of the above map sections, where each map is as if it consisted of physically separated 4096 × 1 bit RAM. Is shown. For convenience in implementation, it is convenient for all map data to be stored in a single portion of the HSRAM, as shown in FIG. DSW Management Section 190 (13th
Figure 4) controls the multiplexing operation for the four bits from each of the four maps of Figure 15 obtained from one 16-bit word in HSRAM. As will be appreciated by those skilled in the art, the advantage of this scheme is that HSRA
The processor can initialize the map using the same means used to access the other parts of M.

Further, three different classes of destination selection words are used, and correspondingly, the storage locations of the selection map are hash selection portion, class selection portion, and destination processor identification information (destination proc).
essor identification (DPID) is divided into selected parts. This DPID specifies whether the processor 105 is a specific processor intended as a destination of the message packet. On the contrary,
The class selection portion specifies whether the processor is one of a plurality of processors belonging to a particular processing class to receive the message packet, that is, whether the processor is a member of the processor group. Is what you do. The hash value is stored according to a distribution method when the database is distributed inside the relational database system, and this distribution method is an algorithm for a specific relation adopted in the system, In addition, it follows the distributed storage method. When specifying a processor, the hash value in this specific example can be specified as having one of a primary responsibility and a backup responsibility for the data. ing. Therefore, according to the above multiple selection maps, H.
S.RAM26 ″ can be addressed directly to determine if the processor is the destination or not. This feature will prioritize messages to all network interfaces. It is a complementary function that complements the method of broadcasting to 120, and also allows local access to the status of the microprocessor 105 without interrupts.

One section of the HSRAM26 ″, independent of the rest, serves as the central means for checking and controlling globally distributed activities. As already mentioned. , And as shown in Figure 3, a transaction number (TN) is assigned to each of the various operations sent to and received from network 50b. The TN is included in each of the HSRAMs 26 ″ so that each processor system 103 has a global transaction identity (transaction identification information) when executing the subtasks that it has accepted independently. Dedicated block for storing the addresses of multiple available transaction numbers when performing their subtasks. Houses the (entry for = Status) the status entries that are locally controlled and updated by the microprocessor system 103. TN is used in a variety of different ways, both locally and globally, when performing intercommunication functions. Transaction numbers are used to identify subtasks, invoke data, provide commands, control message flow, and identify the type of global processing dynamics. The transaction number can be assigned, abandoned or modified during the execution of the global communication. These features are described in further detail below.

Among the TN features, the most complex, but perhaps the most effective, is the local processor (== Its ability to allow distributed updates of the status of individual processor modules). Each control process (ie task or multiprocessor activity)
Has its own TN.

The readiness state (what the processor is ready to do) is now held in the transaction number section of HSRAM26 ″, which is the microprocessor's readiness value. Modified locally (= inside individual processor modules) under the control of the system 103. The microprocessor system 103 has the appropriate entry (eg SACK / Busy) in the response directory of FIG. ) (Address is "050D (hexadecimal)"), and this SACK / Busy status is entered into the HSRAM 26 "by transferring the image as it is reproduced. The entry entered in a certain TN address (= the storage location corresponding to the transaction number) is the A and B ports of HSRAM26 ″. It is possible to access from the network 50b via the network and via the interface 120 '. The inquiry is made by using a "status request" message including the command code (see FIG. 11) of the status request (status request) and TN. Interface 120 'is the TN of the specified TN
Using the contents stored in the address, a response directory storing a response message written in an appropriate format is referred to. Global status query for a given TN to a second network interface
If 120 'is received, it elicits a direct response, which is only under hardware control. No pre-communication is required and the microprocessor system 103 is neither interrupted nor affected. However, if the status was set by transmitting a "lock" indication to interface 120 ', microprocessor system 103 would disable the interrupt and interface 120' would reset address "0501". (Hexadecimal) "and continue to communicate until the lock word is removed later.

The word format in the readiness state is shown in seven states from “busy (state during operation)” to “initial (initial state)” in FIG. 12, and FIG. Figure 3 illustrates one useful example employed in some practical systems. Modifications in which the readiness state is classified into more types and those in which the readiness state is classified into fewer types are possible. However, by using the seven types of states shown in FIG. Extensive control can be performed. HSRAM2
6 ”continuously updates the status level of the individual TN (= readiness level represented by the entry stored in the individual TN address), thereby increasing the availability of the subtask and the subtask It is the responsibility of the microprocessor system to ensure that the progress of the process is reflected, and that such updates are made using the format shown in FIG.
By writing to the address, it can be easily executed.

In Fig. 10, each status response (status response)
Is the status acknowledgment command code: S
ACK). These SACK responses sent to the network are actually composed of the command code of FIG. 10, the numeric part of the word format of FIG. 12, and the originating processor ID (OPID), This is as shown in FIG. Therefore, those
The SACK responses form a group of priority subgroups within the overall priority rule shown in FIG. OPID has meaning in terms of priority conventions, for example, because one processor with multiple processors
It works with TN, but if any of them are in the "busy" state, the determination of the highest priority message to be broadcast will be based on this OPID. Transfer and coordination of the system can also be performed based on this data (OPID).

Priority rules are defined for SACK messages (= SACK responses), and multiple microprocessors
Compared to the conventional system, the response is simultaneously sent from the system 103 and the priority is dynamically determined (while performing transmission) in the network 50b. Determining the status of a global resource for a given task is to be performed in a greatly improved manner. The resulting response is unique, never represents an unspecified condition, and does not require software or cause the local processor (= individual processor module) to spend time. . Thus, for example, deadlocks never occur due to frequent status requests that interfere with task execution. At various status levels, many optional operations of the multiprocessor are available. Local processors can continue to operate independently of each other, and with a single query, one,
Never before has a global, prioritized response been elicited.

A more detailed description of the sequence shown in FIG. 12 may be helpful here.
"Bizy" state and "waiting"
A state is a state in which an assigned or delegated subtask will gradually progress to a more complete stage, while a "waiting" state requires more communication or events. Represents the state of being. These "visi" and "waiting" states are those where the status of a TN goes up to a higher level, and eventually a message / message about that TN
FIG. 9 shows an example of a level increase in which a packet reaches a status level at which a packet can be transmitted or received.

On the other hand, when transmitting or receiving a message packet, the ability of the TN in message control, which is another feature of the TN, is exhibited. When the microprocessor system 103 has a message to send, the status display shows "Ready to send (se
nd ready) ”. Microprocessor system 10
In step 3, in addition to updating the status display, the value of the "next message vector" is input to the HSRAM 26 "using the word format shown in Fig. 12. The input entry corresponds to the corresponding output message. HSRAM2
It specifies from which location of 6 ″ it should be retrieved. This vector is used to connect multiple output messages related to a particular TN to one network (= chain). It is used internally in the interface 120 '.

A function related to the above functions is “Ready to receive (rece
ive ready) ”state. In the "ready for reception" state, the input message count value obtained from the microprocessor system 103 is held at the storage location of TN (= TN address), and the input message count value is obtained. Is a value related to the number of messages that can be received for a given TN. This count value is decremented as input messages are successively transferred, and may eventually become zero. If it reaches zero, no more messages can be received and an overrun condition will be indicated. As described above, the transmission speed between the network 50b and the microprocessor system 103 can be adjusted using the TN.

To explain the local (= individual processor) aspect, at the individual processor, while processing is being performed, the TN uses in the transmitted and received messages a constant constant that applies throughout the system. Is held as. The "TN0" state, or default state, also serves as a local command to specify the fact that the message should be used in non-merge mode.

To explain from a global perspective, "TN0" and "TN
By discriminating various values of > 0 " as having different properties, one command function among a plurality of command functions using TN is defined. That is, by distinguishing the TN in such a manner, a characteristic description representing either “merge / non-merge” is attached to each message packet, and thereby, a plurality of messages are To determine priority and sort
A powerful system operating system has been obtained. Similarly, "Assigned (assigned state)", "Unassigned (unassigned state)", "non-participating processor (Non-Par
ticipant) "and" initial "status to perform global intercommunication and control functions. An "unassigned" state is a state where the processor has previously abandoned the TN, and thus it needs to receive a new primary message to reactivate the TN. If the processor displays "Unassigned" when the status display should be "Assigned", this indicates that the TN was not properly entered,
A corrective action must be performed. If the TN is "assigned" when it should be "unassigned", this indicates either an incomplete transfer or a conflict between the two processors for a new TN. May be an indication of what is happening. Neither of these `` assigned '' and `` unassigned '' are treated as a readiness state, because at the time they are displayed, the processor has not yet started working on the TN. It is.

Furthermore, "Initial" state and "Non-participating processor"
Status is also important in the context of global resources. The processor that is about to go online, that is, the processor that must complete the process of joining the system, is in an "initial" state, which is an administrative step in order to bring this processor online. It is necessary to step on. A processor that is in the "non-participating processor" state for a given task does not need to perform any processing locally, but by tracking this TN, it is inadvertently improperly used Need to be done.

Referring again to FIG. 10, the dedicated directory or reference section of the HSRAM 26 "may have a plurality of prioritized, multiple types of hardware used to generate responses other than the types described above. Also includes other types of messages: NA (not assigned:
The entry "meaning" not allocated ") is prepared for future use and kept available. The three different types of NAK responses (Overrun, TN Error, and Locked NAK responses) have the lowest data content and therefore have the highest priority, but they are NAK response indicates an error condition. A plurality of SACK responses are followed by an ACK response and a NAP response (non-corresponding processor response), which are arranged in order of decreasing priority. In the configuration of this specific example, two response command codes are not assigned a function (that is, NA), and are ready for future use. Because the directories described above can be initialized by software and used by hardware, any of a wide variety of response message texts can be generated quickly and flexibly. Can be.

Using one independent part of the above directory that is independent of the other parts, TOP, GET, PUT,
Also, the respective addresses of BOTTOM are stored, namely pointers to the function of the circular buffer for input messages and pointers to completion output messages. These pointers are used for the management of input messages and the management of output messages, respectively.
In cooperation with their respective dedicated sectors. The circular buffer method is used for input messages. In this case, “TOP” stored in the directory section of HSRAM26 ″ is a variable address that specifies the upper limit address position for input messages. I have. The PUT address stored in the same directory section specifies the address location where the circuit should store the next message to be received. The GET address is set and updated by the software so that the software can recognize in the hardware the address position where the buffer is blanked.

The management of the input message buffer is performed in such a way that the PUT is set to the bottom address of the buffer and that the GET address is equal to TOP. The operational rule set by the software is that GET must not be set to a value equal to PUT, and if so, an ambiguity condition will result. Will be. When an input message is entered into the input message buffer in HSRAM26 ″, the message length value contained within the message itself determines the starting point of the next incoming message, and The PUT address stored in the directory is modified to display the storage location in the buffer that should receive the next incoming message. The input message can be retrieved when the work ability of the user permits.

The data stored in the output message storage space in the HSRAM 26 ″ is an output message completion vector held inside a circular buffer independent of other parts,
And the next message vector in HSRAM 26 ". Editing (assembling) and storing of individual messages can be performed at any location, and, for a plurality of messages related to each other, the messages are transferred to the network. In the directory section of HSRAM26 ″, the addresses of TOP, BOTTOM, PUT, and GET are input as described above. And has been updated,
Thereby, a dynamic current indicator for the location in the output message completion buffer is maintained. The message completion vector constitutes an index address for pointing to a message stored in the output message storage space and indicated by the received response that the transfer has been properly performed. ing. As will be explained later, this system makes it easy for the microprocessor system 103 to input outgoing messages, while it allows complex concatenated vector sequences to be organized in an orderly manner. So that the output message storage space is used efficiently,
It allows the transfer of message chains.

The protocol of Figure 11 described above in connection with the response is
Following the response, the primary message is also specified. A plurality of types of response messages are arranged in succession with each other, and hexadecimal command codes are illustrated in ascending order. Within the group of primary messages, the merge stop message (which is also the basic control message, the non-merge control message) has the lowest data content and therefore the highest priority. is there. This message constitutes a control communication that terminates the merge mode in the network as well as in the processor module.

Too many different types of primary data
The messages can be used in ascending priority order, and they can be classified according to their application requirements and system requirements. As mentioned earlier, a continuation message that follows another message may be given a higher priority to maintain continuity from the preceding message packet. it can.

The bottom group in Figure 11, consisting of four types of primary messages, is the only type of status message that requires a status response from higher priority to lower priority. status·
It includes a request message, respective control messages requesting "TN abandonment" and "TN allocation", and a lower priority "merge start" control message.

The above configuration enables operations that can be used in many applications, as will be apparent from more detailed examples described later. The processor module has the current transaction number (PTN)
Is designed to work based on
The same is true whether the PTN is specified externally, by command from the network, or generated internally while performing a sequence of operations. When the merge operation is being executed, the processor module is executing the operation by utilizing the global reference, that is, the transaction identity (= information for identifying the transaction). Is defined by TN. Starting, stopping, and resuming the merge operation is performed using only simple message changes. If the subtask does not need to merge the messages, or if a message packet occurs that has no particular relationship to other messages, those messages will be "TN0"
, Queued for output to the base state, or default state (0), which is currently determined by the transaction number.
Is maintained while the true state is maintained. This "TN0" state allows messages to be queued for transfer when merge mode is not used.

(Network Interface System) Referring now to FIG. 13, which shows in more detail one specific example of an interface circuit suitable for use in the system of the present invention. Although the description in this "Network Interface System" chapter contains a number of detailed features that are not necessary for an understanding of the present invention, these features are not incorporated into the actual system. Therefore, it is included in the description for clarifying the positioning of various embodiments with respect to the gist of the present invention. Descriptions of specific configurations and detailed structures for gating, which are not the subject of the present invention and relate to well-known means, may be omitted because various alternative configurations can be adopted. Or decided to simplify it. Fig. 13 shows the eighth
Fig. 3 is a detailed view of the second network interface 120 'as well as the HSRAM 26 "shown in the figure. The respective interfaces 120, 120' for the two networks function in a similar manner to one another and therefore It is sufficient to explain only one.

In FIG. 13A, the input from the active logic network 50, which is connected to the interface shown in FIG. 13A, is passed through a multiplexer 142 and a known parity check circuit 144 to the network message management circuit 1
Supply to 40. The multiplexer 142 is further connected to a data bus of the microprocessor system, which allows access to the message management circuit 140 via this data bus. This feature allows the microprocessor system to operate the interface in a step-by-step test mode, and that the interface is connected to the network as if it were online. As described above, data transfer is performed. The input from the network is the receive network data register 146.
To the first register 146.
And the byte data input to this register 146 via the byte buffer 148 for reception.
8 stores its own byte data in this register 14 after the input of byte data to the first section.
Fill in another section of 6. This allows both of the two bytes that make up each received word to be
It will be input to the receiving network data register 146 and will be kept there available.

The output message to be transmitted is input to the transmission network data register 150, and a parity bit is added inside the ordinary parity generation circuit 132. The message is sent from the network message management circuit 140 to the network connected to it, or (if test mode is used) to the microprocessor system data bus. For the purpose of managing a message inside the interface, the format of the transmission message stored in the random access memory 168 includes not only the message data but also the identification data. As can be seen from FIG. 21A, any of the commands, tags, keys, and DSWs can be combined with the primary data to be transmitted.

The configuration shown in FIG. 13A is essentially the same as that shown in FIG. 8 except that in FIG.
An interface data bus and an interface address bus are separately connected to the input port A and the input port B of the HSRAM26 ″, and the address bus and the data bus of the microprocessor system 103 are also connected.
The bus is shown as connected to a separate C port. However, in reality, as shown in FIG. 13A, such access from two independent directions is performed inside this interface.
This is accomplished by time-division multiplexing of the input and output address functions in the HSRAM26 ″. Microprocessor data bus and address
The buses are connected to the respective buses of the interface via gates 145 and 149, respectively, which allow the microprocessor to operate asynchronously based on its own internal clock.

The timing scheme employed is based on clock pulses, phase control waveforms, and phase subdivided waveforms, which are
Generated by clock circuit 156 (Figure 13),
It has the timing relationship shown in Fig. 4 (first
4 will be explained later). The interface clock circuit 156 is the network clock from the node closest to it.
The word clock is received, and the phase lock clock source 157 includes means for maintaining zero time skew as described above in connection with FIG. The nominal network word clock speed in the 240ns network
Time subdivision within clock circuit 156 is performed by a frequency multiplier (not shown in detail) held in a phase locked state defining a reference period of 40 ns duration. High-speed clock (PLCL in Fig. 14
(Shown as K). The basic word period is defined by the periodic signal labeled CLKSRA in the figure, which has a total period of 240 ns and is inverted every half cycle. Two other signals with the same frequency and duration as this CLKSRA, frequency divider 158 based on PLCLK.
These signals are each generated by CLKSRA
At the time delayed by one cycle and two cycles of PLCLK from CLKSRB and CLKSRB and CLKS, respectively.
Given the name RC.

Based on the above various signals, the control logic 159
Timing waveforms called "IO GATE", "RECV GATE", and "SEND GATE" (hereinafter also referred to as gate signals)
, And these timing waveforms represent each of the three equally spaced intervals of the word period. These intervals are labeled with the corresponding names of "IO phase", "reception phase", and "transmission phase". Each of these phases defined by the gate signal is further
"IO CLK" signal, "RECV CLK" signal, and "SEND CL
It is subdivided into two equally divided half-intervals by the "K" signal, which subdivisions define the second half of each phase. The byte clocking function is managed by a "BYTE CTRL" signal and a "BYTE CLK" signal.

The above IO phase, RECV phase (reception phase),
The SEND and SEND phases provide the basis for the random access memory 168 and the bus of the microprocessor system to perform time-multiplexed operations. Things. The interface can only receive or transmit one word per word period to and from the high-speed network, and obviously, the reception and transmission never occur at the same time. The transfer rate of the transfer to and from the microprocessor system is:
It is much lower than the transfer rate to and from this network, but even if both are at the same speed,
It does not overburden the capabilities of the interface circuit. The system configuration of this interface is direct to random access memory 168.
Most operations are performed by the access, so that little internal processing or software is required. Thus, as the system periodically progresses through successive phases in each word period, the words are determined one after the other and without colliding with each other. , Thereby performing various functions. By way of example, sending messages to the bus between receipts of messages from the microprocessor, and each of them using alternating portions of memory 168. You can

Intercommunication between the data bus of the microprocessor system and the network interface is performed by the IO management circuit 160 (Read / Writing this IO).
e) Sometimes called)). A microprocessor bus with a write gate 162 for gating the word coming from the microprocessor system and a system read register 164 for sending the word to the microprocessor system,
There is a connection between the network interface and the bus interface.

Further, a memory address register 165 and a parity generator / check circuit 166 are incorporated in the network interface subsystem. In this specific example, the high-speed memory (= HSRAM) is composed of a random access memory 168 of 4K words × 17 bits. The usage of the dedicated memory area is as described above. This random
The size (= capacity) of the access memory can easily be reduced or expanded to meet the needs of a particular individual application.

A receive message buffer management circuit 170 is connected to the data bus of the microprocessor and further to the address bus of the memory 168. The term “received messages” refers to “PUs” coming from the network and stored in a circular buffer.
It may also be used to point to a message that is entered into the storage location of "T", and after this entry, the message thus entered into the circular buffer will be forwarded to the microprocessor. Sometimes used to indicate something. When a transfer to this microprocessor occurs, the "GE
The value of "T" specifies from which location the system should perform successive retrieval operations in performing retrieval of received messages to be forwarded to the microprocessor system. Multiple address values used to access the random access memory 168 are stored in the GET register 17
2. Input to the TOP register 174, PUT counter 175, and BOTTM register 176, respectively. PUT counter 175 is BOTTO
It is updated by incrementing by 1 from the initial position designated by the M register 176. TOP
Register 174 provides an indication of the other side of the boundary. Both TOP and BOTTM values can be manipulated by software control, which allows
It is possible to change both the size of the receive message buffer and the absolute storage location in HSRAM. If the contents of the PUT register equals the contents of the TOP register, the PUT register is reset and the BOTTO
It is equal to the contents of the M register, which allows this buffer to be used as a circular buffer. The above GET register, TOP register, BOTTOM register, and PUT counter are used to manage both the input message circular buffer and the output message complete circular buffer.

The input to the GET register 172 is made under software control, because the next address (next address) is determined in the buffer according to the length of the message currently being handled. .
GET register 172, PUT counter 175, and TOP register 1
Comparators 178 and 179 connected to the respective outputs of 74 are used to detect and indicate overrun conditions.
The overrun state is a state that occurs when the value of GET and the value of PUT are set to the same value, or when an attempt is made to set the value of GET to a value larger than the value of TOP. In either of these cases, an overrun status indication will be sent, and this status indication will continue to be sent until the overrun condition is corrected.

Such a continuous scheme for configuring and operating a "received message" circular buffer is a scheme particularly suitable for this system. By allowing cross checks to avoid conflicts,
"PUT" can be managed by hardware, and "GET" can be managed dynamically. However, it is also possible to adopt a buffer system of a method other than this. However, this will probably add some extra burden on the circuit and software. Referring now to FIG. 21B, the format of the received message stored within memory 168 further includes identification data in the form of map result, data length, and key length. How to obtain the data will be described later.

DSW management section 190 inside this interface
Includes a destination selection word register 192, to which a destination selection word (DSW) to be transferred to the address bus is input. When the dedicated DSW section of the memory 168 is addressed using the DSW, the output sent from the memory 168 onto the data bus returns data, and based on the data, the DSW management section 190 sends the message packet to the relevant processor. It can be determined whether or not this is the transfer destination. As can be seen from FIG. 13A, the destination selection word is a 2-bit map nibble (nybl) address and a 10-bit map word
It consists of an address and 4 bits for map selection. The "nibble" address of these is memory 168
It is used to describe subsections of words from. The 4 bits for map selection are supplied to the map result comparator 194, which is the multiplexer 19
Receiving the associated map data from memory 168 via 6. Multiplexer 196 receives 16 bits of data, the 16 bits being the four different maps stored at the address specified by the 10 bits of the map word address contained in the DSW. -Represents data nibbles. Memory 168 is arranged with its dedicated map sections in a form particularly suitable for comparison, so as to facilitate the comparisons made herein. D being supplied to the multiplexer 196 for its control, D
The remaining 2 bits in SW select the appropriate one of the four map nibbles. The comparison is made and the map
The code is entered into the map result register 197 and inserted into the input message being entered into memory 168. If the comparison shows that there is no "1" bit in any of the selected maps, a "reject" signal is generated and the processor module causes It is indicated that the message packet is not intended to be received.

Referring to FIG. 15, a schematic illustration of a preferred method for subdividing a dedicated destination selection section of memory 168 and for comparing map results is shown. Has been done. Each map is 4096
It is composed of words × 1 bit, and is further subdivided into individual processor ID sectors, class ID sectors, and hashing sectors (see FIG. 8). When a common map address is selected using 12 address bits (10-bit map address and 2-bit nibble), one bit output is obtained from each map. (The multiplexer and its nibbles in Figure 13 are not shown in Figure 15 for clarity). The four parallel bit outputs are composed of four AND gates A
The ND gate group 198 can be compared with 4 bits for map selection, and as a result,
If more than one match is obtained, the output of OR gate 199 goes to the "true" state. This map result can be entered into the map result register 197 of Figure 13A, which causes the message to be accepted into memory 168. If not, the message is rejected and a NAK is sent.

The command word management section 200
Includes a command register 202 that receives the word.
The TN field of the command word can be used to access the address bus, which accesses the indexed received TN to determine the appropriate response message (see Figure 18). ). Furthermore,
When the "Start Merge" command is executed, TN
From the field to PTNR (current transaction number
Register) 206, a data transfer path is secured,
This is so that the value of the PTN (current transaction number) can be changed in accordance with the “merge start” command.

The input message input to the memory 168, as described with respect to FIG. 21, may include the length of the data and / or key fields, if any, to make the address vector available. It includes the value. Their length values are determined by a receive data length counter 210 and a receive key length counter 211, each of which is used when the input source provides a field corresponding to the respective counter. Field counts the number of words in the sequence.

In addition, a send message management section 220 is used, which includes an acceptance function for storing processed packets in memory 168 and a function for sending those stored packets to the network at a later time. are doing. This section 220 includes the transmit transaction vector counter 222, transmit data length counter 2
24, and a transmit key length counter 226, which are bidirectionally connected to the data bus. The transmit transaction vector counter 222 is connected to the address bus, while the transmit data length counter 224 is connected to the address generator 228,
This address generator 228 is further connected to the address bus. The message is transmitted using both the output buffer section and the circular buffer constituting the output message completion vector section of FIG. However, in this particular example, after a plurality of message packets have been sequentially input, they are now retrieved in the order defined by the vector.

Inside this interface, the independent operation phases are executed at mutually exclusive times, and by adopting such a time division method, the memory 168 is configured so that the network clock speed is To receive and supply message packets from the network, to perform internal operations at high efficient speeds, and to operate microprocessor systems asynchronously at their own slow clock speeds. It is possible to communicate between them. To control the gating operation of messages to various counters and registers, the phase control circuit operates in response to control bits, which control commands, DSW, data, and individual It generates other signals indicating the field. Transmission state control circuit 25
0, the reception state control circuit 260 and the R / W (read / write) state control circuit 270 receive the clock pulse,
Identify fields in the data and send, receive,
It also controls the sequencing of the data flow during the clocking of the processor.

Control of this interface is provided by three finite state machines (FSMs), each of which is for a transmit phase, a receive phase, and a processor (R / W) phase. These FSMs are constructed in a general manner using a programmable logic array (PLA), status registers, and action ROM. Each FSM is advanced to the next state once every network clock cycle. Due to the large number of control signals to be generated, the PLA output is further encoded by the action ROM. As will be readily appreciated by those skilled in the art, the translation of a control sequence written for the FSM mode, and thus having general details and operation, which is necessary for the operation of the network, It is a simple task with a lot of work.

The inclusion of the state diagrams of FIGS. 17 and 19 and the matrix diagram of FIG. 18 in the accompanying drawings provides a comprehensive view of internal structural design features that can be employed in fairly complex systems. This is to present detailed details. FIG. 17 is a diagram related to the reception phase, and FIG. 19 is a diagram related to the transmission phase.The notations used in these figures correspond to the notations used elsewhere in this specification and the drawings. doing. For example, the following terms:

RKLC = Receive Key Length Counter RDLA = Receive Data Length Counter RNDR = Receive Network Data Word Register PUTC = Put Counter (PUT Counter) ) GETR = Get Register The state diagram can therefore be understood without any explanation by reference in contrast to Figure 13 and the specification. The state diagrams detail the various sequences and conditionals involved in complex message management as well as interprocessor communication. Figure 17 (17A
In FIG. 18, the respective states in which the labels “Generate a response” and “Decode the response” are written, and the respective conditional statements indicated by broken-line rectangles are the matrices in FIG. • Follow the specified responses and actions described in the diagram. FIG. 18 shows DATA (data), STOP (stop), STATUS (status), RELQ (abandon), ASGN (allocation) and STRT (primary message) of a predetermined transaction number (TN). Start) and the corresponding response messages LOCK (lock), TNER (TN error), OVER (overrun), nine different status responses corresponding to FIG. 12, ACKR (acknowledgement) and NAPR (no response) (A processor response). As for the dotted lines in the table, the upper part of the dotted line indicates a specific response, and the lower part of the dotted line indicates a specific process. The meaning of the symbols used in the table is listed below the table. The primary message always has a transaction number (TN) regardless of the data message or control message.

When a primary message having a certain TN is transmitted via the network, the network interface section 120 of each station generates various response messages according to the processing state of the subtask related to the TN. The response messages used in the system according to the present invention include a positive response (ACK) and a negative response (NA).
K), or a non-compliant processor response (NAP), which is a response indicating that it does not have the requested data resource. There are several different types of NAK responses, depending on factors such as lock (LOCK), TN error (TNER), and overrun (OVER) of buffers and the like.

Here, in addition, the processor at its station uses a status acknowledgment (SACK), which indicates a ready state for transmission for the processing of a particular task. Also,
The signal representing this SACK is used together with a specific primary message for various protocols, such as system initialization,
Used to perform lockout processing. The SACK response is
As shown in FIG. 11, there are nine status levels indicating different meanings, and the word format is as shown in FIG. It is the responsibility of the processor in the station to constantly update the status level of each sub-task process in the station in charge of the multiple sub-task processes related to multiple TNs according to the progress of the process. is there. In FIG. 12, the states of “Bizi” and “Waiting”
This indicates that a specific subtask assigned together is in the state of moving to the next phase.

If the processor module 103 had a message to send, its status is "ready to send". “Reception preparation completed” indicates that the processor module can receive a message having a preset TN.
The multiple TN values to be used are the HS of each station beforehand.
It is initially set in RAM, but is abandoned during operation or assigned a new TN. "Assigned" and "Unassigned" are responses whether or not the TN is set at the station.

As described above, since a TN that allows each station in the system to synonymously recognize what task the transmitted message relates to is included, even if a certain message is transmitted collectively in the network, each station can transmit the message. Since it is possible to specify which task the transmitted message is related to, a plurality of tasks can be processed simultaneously in the system.

In both FIG. 17 and FIG. 19, many of the condition judgments can execute a plurality of judgments at the same time. It is being changed one by one. In either case, the transmission operation and the reception operation are operations that proceed at a predetermined progress speed without requiring external control, and the configuration of the message and the operation method of the network have already been described. It is because it has become.

Typical processor system or multiprocessor
Many of the features employed in the system are not germane to the present invention and are therefore not specifically described. Among those features are:
There are parity error circuits, interrupt circuits, and various means for monitoring activities such as watchdog timers and a wide variety of test functions.

Here, a case where a plurality of tasks are simultaneously handled in the system according to the present invention will be summarized.

All the messages transmitted and received between the respective processors constituting the computing system according to the present invention have a message format as shown in FIG. 3, and as shown in FIGS. It has a command word consisting of a bit command code and a 10-bit tag field. Further, as shown in FIG. 11, in the 10-bit tag field, if the message is a primary message, the transaction number (TN) is displayed, and if it is a response message to the primary message, the sender ID number ( Must have an OPID). The message sent to the communication network in order to cause a given processor (s) to process a task is a primary message, and the task will be identified by this TN identification number. A plurality of TN values to be used in each processor are stored in a predetermined address in a high-speed RAM (HSRAM) in each constituent processor (FIG. 8).
Is normally initialized to 0400 to 0500 in HSRAM). The TN value can be assigned or abandoned on the way by a predetermined command code (command code) as a primary message (eleventh message).
Figure).

In addition to TN, the primary message is a destination selection word (DSW) for directly or indirectly indicating the destination processor or processors to which the message should be received.
(FIGS. 3A and 3B). Thus, by using various combinations of TN, DSW and command codes, a wide variety of inter-system intercommunication functions can be achieved. Primary messages are roughly classified into two types. One is to perform a distributed processing of a task or to transmit a processing result accompanied by data of a task to another processor, which has a key field data message of variable length data and a data field. Data message "(Fig. 3A, Fig. 11).
The other one is the result of inquiring about the status of the processing result of the task message, allocating a new TN before sending the task message, discarding the used TN, or inquiring of the status. When a positive response is received from all the processors related to the task processing related to a specific TN, the "control / status" for instructing to start or stop the merge, which is a command to transmit the processing results all at once.・ Message "(Fig. 3B, Fig. 11)
Figure). In the present embodiment, as shown in FIG. 11, eleven command codes ("11" to "1B") are transmitted for transmitting the data message (primary message) to which different specific TN values are assigned. They can be used at the same time.

The TN described in the tag portion in the command code of the final primary message sent to itself regardless of the data message or status message is currently treated as the TN, and this value is used by each processor. Currently updated in the TN counter (206) in the network interface (Figs. 8 and 13) and stored by the interface itself. Each constituent processor in the system was associated with multiple task processes. However, as mentioned above, be sure to use TN in the primary message.
As a result, it is possible to recognize what task the control or status response is required for,
The format of the response message indicating the requested TN response (command code “00” to “0F” in FIG. 3C and FIG. 11)
To send. Since the command code related to the response message is a numerical value smaller than the command code related to the primary message,
It is transmitted preferentially in the network, and its source is specified by the OPID.

As shown in the block diagram of FIG. 8, in each station, the network interface 120 operates separately from the processor module 103 and in synchronization with the active logic network, and the communication in the full-duplex communication configuration is performed. The message sent from the network is HSRA
It is sequentially stored at a predetermined address of M. In addition, the interface transmits a response related to a predetermined TN at the timing of the network (FIG. 7) together with the reception. When a status request or the like is received, transmission of a response message related to the current TN is given top priority. The processor module 103 in each station is connected to the HSRAM in the station.
The messages stored in the main RAM1
07, necessary processing or search is performed, and the result is sequentially stored as an output message at a predetermined address in the HSRAM. As described above, the processor module 103 is not directly involved in receiving a message from the network, storing the message in the HSRAM, and controlling the transmission of the processing result or the response message to the network, and these are not directly related to the network interface. It is in charge.

A time-division bus (the first bus) is used between the network interface 120, the HSRAM 26, and the microprocessor module 103.
4), the interface 120, which operates in synchronization with the network, and the processor
Each of the modules 103 operates at its own timing. In other words, each can access the HSRAM without being involved in the operation of the other party. H.
DS.TN, data message stored in S.RAM
Initialization and allocation of pointers and response directories,
The change or the like can be performed by another processor via the network, or the processor 103 in the station can be changed.
It can also be done by accessing from.

In this way, each station making up the system
Even if it is related to a plurality of task processes at the same time, based on the TN in the received primary message, it is possible to recognize the task related to which task, search or status response is requested, and TN
Can be responded to by attaching a sender ID in a predetermined response message format. The source processor of the primary message recognizes from which processor these response messages are sent by the source ID.

(Specific Example of System Operation) Described below is how the system shown in FIGS. 1, 8, and 13 is internally operated in various operation modes while cooperating with the network and the HSRAM. Here are some specific examples of how it works. These examples illustrate how the inter-relationship between the precedence rules, the addressing scheme employed here, and the transaction identity can explain how both local control and global intercommunication functions. Indicates whether to provide.

Transmitting and receiving primary data messages. In addition to the other figures, FIG. 16 will be further described. It is. Even if a message is received in a buffer or memory, acceptance is not achieved unless the logical state shown is satisfied. Although shown as a serial sequence of events in the figure, originally, a plurality of determinations are performed in parallel, that is, at the same time. Alternatively, an intermediate stage for reaching a certain operation stage may be performed by a circuit.

The message on the network of FIG. 1 is stored in the receive network data register 146 of FIG.
Passed until a condition is identified, at which time the message is known to be complete. If a "LOCK" condition exists,
The system sends a NAK / LOCK reject message by referring to the response directory in the HSRAM 26 "of FIG.

Otherwise, i.e., if the "lock" condition does not exist, the system moves to the map comparison check, which checks the D in the interface shown in FIG. 13A.
It is executed inside the SW management section 190. If there is a suitable comparison result, represented by "map output = 1", the system can continue to receive the message. If no such comparison exists, the message is rejected and a NAP is sent.

Once the appropriate map has been determined, the system is now ready to check the TN status, which is checked by the TN shown in FIG.
Directory (see TN status is strictly the status of the processor for a given TN, and thus the TN status in HSRAM).
Readiness state represented by the entry stored at the address). More specifically, this check of the TN status is performed to determine whether or not the local status (= the status of the individual processor module) is “ready to receive”. Here, it is assumed that the TN is already assigned by some preceding primary message.

As a result of this check, TN is in the "done" state,
If it is found to be in either a "non-participating processor" state or an "initial" state, then a "NAP" reject message is sent (TN is here strictly speaking HSRAM). It is the entry stored at the TN address in the following, but unless there is a risk of confusion, this entry will also be simply referred to as TN). If the found status is any other out-of-spec condition, the rejection message sent is a "NAK / TN error" and the two types of rejection messages are also the response in FIG. Retrieved from directory. If the status was "ready to receive", yet another determination will be made.

The other determination is related to "input overrun", and this determination is as described above.
This is done by comparing the GET address with the PUT address inside the I / O management buffer section 170 of FIG. 13A. Furthermore, the transaction number is also checked for a non-zero received message count value, and if this count value is zero,
It also indicates an input overrun. If an overrun condition exists, a "NAK / input overrun" is sent and the message is rejected.

If all the above conditions are satisfied, HSRAM2
An "ACK" message (acknowledgement message) is extracted from the response directory within 6 "and sent out on the network, and priority is contended with other processor modules. Some of these other processor modules may have also sent acknowledgments to the received message. at this point,
If the common response message received from the network (this "common" means merged) is "AC
K "message, and therefore indicates that" all "processor modules selected as receiving processor modules are capable of accepting a previously received message. Is accepted. If this response is in any form other than "ACK", the previous received message will be "all"
Rejected by processor.

Note on Receiving and Responding In this example, note that after the primary message is received, all processors generate any one of ACK, NAK, and NAP responses. As soon as the processor receives any one of these response messages, it can attempt to transmit the primary message. (The processor may also make this transmission attempt after a delay equal to or greater than the delay corresponding to the total latency for traversing the network, which was already discussed in the Active Logic Nodes chapter. As I did). Another thing to note is that if several processors send "identical" messages to each other, then all of those messages have won the race on the network. Is also possible. In that case, "all" of those sending processors
Will receive an ACK response. This is important with respect to broadcast and global semaphore mode operation, which will be described in detail in a later example.

Actual examples of the present invention that are actually used include even more types of responses in addition to those described above, and perform various operations. FIG. 18 shows their responses and actions for LOCK, TN error, and overrun interrupt states, nine different pre-identified status levels, and acknowledgment (ACK) and non-applicable processor responses. , Each item is shown in a column.

When a processor module is ready to send a message, the PTN value stored in the PTN register 206 in FIG. 13 is available, and therefore all that is required is that the TN status be "Ready to send". It just confirms that it is in the "completed" state. As can be seen from FIG. 12,
The entry "entry ready" contains the next message vector address for the output message. The output message that has been assembled is sent out over the network, and if contention is lost, this sending operation is repeated until a successful transmission, unless a PTN is changed, and a response is received if successful. become. If the transmission is successful and an acknowledgment is received, the address vector is changed. The next message vector is retrieved from the second word (FIG. 21A) in the current message, and this word is transferred from the transmit transaction vector counter 222 to the random access memory 168. If the output message section is not in an overrun condition, the PUT counter 175 is advanced by "1", which is indicated by PUT being equal to GET.
The next message vector transferred from the transmission transaction vector counter 222 is HSRAM
Input to the transaction number address currently specified by the transaction number register 206 in. If this new TN is in the "ready to send" state, the value of this input vector is again the next message associated with this transaction identity (next message).
Pointing to the storage location of For the format of the output message stored in HSRAM, see Chapter 21
See figure.

However, message management when sending a message can include many different forms of operation, including internal or external changes to the PTN. An error, overrun, or lock condition can cause the system to shift the transaction number to "TN0", which causes the system to return to non-merge mode and "TN0" Inspection of status at
It will continue until the "ready for transmission" state is identified or a new TN is assigned. See the flowchart in FIG. 19 (FIG. 19A) for conditions and conditions that can be employed in fairly complex embodiments.

Output Message Completion Buffer Example If the completion of transmission of a message is indicated by any other response message except "LOCK", a pointer to the newly completed output message buffer is output from the HSRAM. Stored in the message completion circular buffer section (see FIG. 8). This pointer is simply a 16-bit word representing the address of the output message buffer. (The format of the output message buffer is shown in FIG. 21. Note that the output message buffer contains a place to record the response message received from the network.)

The output message completion circular buffer is
It is responsible for the communication between the interface hardware 120 and the monitoring program located on the microprocessor 105. The program provided in this microprocessor stores the message to be output in HSRAM. As will be explained in more detail in the following example, multiple output messages are concatenated together (chained), with TN acting as the first pointer in this chain. Which can form complex sequences of operations. Another feature is that the network can be multiplexed or time-divisioned (multiplexed) between multiple TNs, which will also be detailed later, depending on various events existing in various parts of the network. The messages can be output in various orders.

Furthermore, the storage space in HSRAM occupied by successfully transmitted packets can be quickly recovered, so that the storage space can be reused for another output packet to be output. is important. An output message completion circular buffer performs this function.

If the transmission of a data message has been successfully completed and a response other than the "lock" response is received, the network interface determines whether the PUT pointer (0th hex) stored in HSRAM at "0510 (hexadecimal)". 10), and the address of the first word of the output message whose transmission has just been completed is stored in the address in the PUT register. (The value of the PUT pointer is "0512
(Hex), the PUT pointer is reset first so that it becomes the same as the BOT pointer (= BOTTOM pointer) stored in "0513 (hex)". ). PUT pointer is GET
If it becomes larger than the pointer (storage location "0511 (hexadecimal)"), the circular buffer is overrun, and an "error interrupt" is issued to the microprocessor.

Software running inside the microprocessor asynchronously examines the output message buffer pointed to by the GET pointer. If the processor completes any processing that it is requested to execute,
Advances the GET pointer by “1” (the value of this GET is TOP
Is reset to the value of BOT when it becomes larger than the value of.) GET
If = PUT, there are no more output messages to process. Otherwise, further output messages have been successfully transmitted and must be processed. This process involves returning the storage space of the output buffer of the HSRAM to free space, so that this space can be reused for other packets.

It is important to note that the outgoing message completion circular buffer and the incoming message circular buffer are distinct from each other, so that these two circular buffers are each a separate PUT, GET, TOP, and It is managed by each pointer of BOT. Depending on the configuration, as shown in FIG. 13, both circular buffers may share the circular buffer management hardware 170, but such a configuration is not required.

Initialization Procedure Each processor module has its own high-speed random access memory 168 (first
3), the memory 168 contains a directory of a plurality of potentially available TNs. However, the unassigned TN is clearly indicated as not assigned by the transaction number value stored in the storage location associated with the TN. Therefore,
Microprocessor system 103 identifies unassigned transaction numbers and uses one of them to initiate communication with other processor modules for a given transaction identity. You can choose to

Transaction numbers are assigned and updated locally under the control of the local microprocessor (= microprocessor in the processor module), but global control throughout the network is:
This is performed using the primary control messages "TN abandonment command" and "TN allocation command". There will never be a deadlock between multiple competing processor modules that may require the same TN, because the network may have a lower numbered processor. Is given priority. The remaining processors that tried to get the TN but did not get priority will receive a "NAK / TN error" response, which indicates that they have a different TN. Must be tried. Thus, full flexibility is gained in ensuring and verifying their transaction identities both internally and locally in the system.

It should be noted that repeated use of TN is
It means that the shift is between the basic transmission mode which is 0 "and the merge mode where TN is greater than zero. Therefore, this system can change not only the focus of its operation but also its nature by a single broadcast transmission of the TN.

Yet another to communicate changes in global status,
And a particularly useful scheme is the propagation of forced parity errors already described with respect to FIG. This unique display scheme, when interleaved and transmitted between other transmissions, causes the aborted system resources to be examined and the appropriate action to be taken.

Processor-to-Processor Communication There are two types of special forms of processor communication, one of which is directed to one particular destination processor, and the other of which involves a plurality of processors belonging to a class. This is communication performed as a transfer destination. Both of these types of transmission utilize DSW, and both of these transmissions are non-merged.
Performed by mode broadcasting.

In particular, when performing communication between one source processor and one destination processor, the destination processor identification information (destination processor identifica) is included in the DSW.
tion: DPID). Referring to FIG. 8, when the selection map portion of the HSRAM 26 "of each receiving processor module is addressed using the value of the DPID, only the specific processor module intended as the transfer destination is Generate an affirmative response to accept the message, and if the acknowledgment has been sent and it is finally successfully received, both processors will perform any required future operations. You can do it.

When a single message for a single control process is to be received by multiple processors belonging to a class, the map nibble and the map address in the DSW are used in the selection map portion of the HSRAM. The corresponding section is specified. All the receiving processors then send out acknowledgments to each other, and the acknowledgments continue to reach the source processor module until the round trip for this communication is finally completed. become.

Global broadcast mode processor communication can be used to communicate each message, primary data messages, status messages, control messages, and reply messages. The inherent capabilities of both the priority protocol and the network with the ability to grant priority make it easy to insert such messages into sequences of other types of messages.

Hashing mode processor selection is by far the most widely used processor selection method when performing data processing tasks in relational database systems. Multiple disjoint (= not sharing the same element) data subsets for primary data (= main data not for backup) and disjoint data subsets for backup data Distributed among different secondary storage devices according to a suitable algorithm. A message about the primary data if two processors respond simultaneously because one processor is sharing a subset of the primary data and another is sharing a subset of the backup data. Is given priority. In order for this condition to be compensated, a higher priority command code (12th
(See the figure). Maintaining the reliability and integrity of the database is also achieved by utilizing the various multi-processor modes described above, in which those modes are applied in the most advantageous way for the particular situation encountered. . By way of example, if a secondary storage device that shares some subset of the primary data fails, then special processor-to-processor communication can be used to update it. Error correction and rollback of a part of the database can be performed in the same manner or by operating in the class mode.

Transaction Number Examples The concept of transaction numbers has provided a new and powerful hardware mechanism for controlling multiprocessor systems. In the present system, the transaction number constitutes a "global semaphore", and the transmission / reception of a message to / from the network and the confirmation of the readiness state of a given task distributed to a plurality of processors are performed. Each plays an important role.

The transaction number (TN) is physically implemented as a 16-bit word in HSRAM 26. This word is formatted as shown in FIG. 12 so as to perform various functions. Since TN is stored in HSRAM, it can be accessed from both the microprocessor 105 and the network interface 120.

Global semaphore The term "semaphore" is used in computer science literature to refer to variables used to control multiple processes that are performed asynchronously with respect to each other.
It has become commonly used. A semaphore has the property that it can be "tested and set" in one uninterrupted operation.

As an example, "UNASSIGNED" and "ASSIGNE (unassigned)"
D: a state in which an assignment is made) ". In this case, the test-and-set behavior is defined as follows: If the semaphore was in the "unassigned" state, set the semaphore to the "assigned" state and indicate success; If the semaphore was already in the "assigned" state in response, leave the semaphore in the "assigned" state and display "failure". Thus, according to this semaphore, operations that successfully test and set the semaphore can continue their tasks, while operations that fail will reset the semaphore to an "unassigned" state. Or attempt to test and set another semaphore controlling another equivalent resource. As can be easily understood, if the test and set operation could be interrupted, there is a possibility that the two processes may access the same resource at the same time, thereby preventing the prediction. Erroneous results that cannot be obtained may occur.

Any multiprocessor system actually embodies in hardware a concept that can be equated with a semaphore to control access to the system's resources. However, conventional systems have
Only the semaphore of the copy (= the semaphore having one copy, that is, the semaphore provided only at one location) can be maintained. Therefore, if semaphores of a plurality of copies (= semaphores having a plurality of copies, that is, semaphores provided at a plurality of locations) are provided and maintained one by one in each processor, the semaphores can be simply accessed for testing. It is desirable both for the purpose of reducing the number of occurrences of contention and for the purpose of utilizing multivalent semaphore variables for other uses described below. The problem is that many copies of the semaphore must be completely synchronized, and if this is not followed, semaphores are provided to enhance it. In this case, the integrity of access to resources is lost.

A multi-copy semaphore, or "global" semaphore,
Provided by the system. The following table compares the behavior for global semaphores with single semaphores (one copy semaphore).

In the system of the present embodiment, “TN assignment (ASSIGN T
The N) command and the RELINQUISH TN command are responsible for the test and set function and the reset function for the transaction number used as a global semaphore. Referring to Figure 12, the "NAK / TN error" response indicates failure, while
A "SACK / Assigned" response indicates success.

Global network semaphores, including the synchronous clocking scheme used to clock multiple nodes synchronously, and the broadcast operation of transmitting the highest priority packet to all processors simultaneously. Is the basis for actualizing the concept. Due to the implementation of this concept, the system gives control of its allocation, deallocation and access of multiple copies of the desired system resource, simply granting TN to that resource. This can be done by doing. What is important to note here is that the control of distributed resources can be performed with a small software overhead, which is almost the same as in the case of a single semaphore. This is a significant advance over traditional systems because they cannot manage distributed resources or require complex software protocols and create hardware bottlenecks. Either it will be lost.

Readyness status "BUSY", "WAITIN
G), “READY” (preparation for transmission and reception respectively), “DONE”, and “NON-PARTICIPANT” (FIG. 12) Provides the ability to quickly check the readiness of a task assigned a TN. In this system, the meaning of each state described above is as shown in the following table.

The assignment of TN to a task is dynamically performed using a "TN assignment" command. Success indication ("SACK / assigned" response to "TN assignment" message)
Indicates that all enabled processors have successfully completed the assignment of the TN to the task. It should be noted with respect to Figure 11 that the "NAK / TN Error" response has a high priority (small value), so if any processor's network interface 120 detects a collision related to TN usage, That is, all processors receive a failure response. In addition, the OPID (originating processor ID) of this failure response transmitted over the network
The field will indicate the first (lowest numbered) processor among the processors that had a collision. This fact is used in the diagnostic routine.

Each processor handles the task by software, and TN is "busy", "waiting", "ready to send", "ready to receive", "end".
Or set to the applicable one of the “non-participating processors”. Any processor, including the first processor that issued the "TN allocation", at any time, by issued a "status request" command or "merge start" command, to complete the extent to which the task "TN" It is possible to easily check the condition of whether or not it is.

A "status request" is equivalent to one test of a multivalent (= possible value) global semaphore. As can be seen from FIG. 11, the highest priority status acknowledgment (SACK) message wins over contention on the network, resulting in the lowest readiness state being indicated. Further, the OPID field indicates the first of the processors in the lowest readiness state.
It will indicate the identity (feature) of the second (lowest numbered) processor.

This latter property is used to define a "non-bysy" form for "waiting" for completion of tasks distributed to multiple processors. First, "T
The processor that issued the "N allocation" is said to be the first "wait master". The processor then designates any other processor as a new "wait master" based on any criteria. When the new "wait master" has reached the desired readiness state, it issues an inquiry to all processors by issuing either a "merge start" or a "status request". If all of the other processors were ready, the SACK would indicate so. If some processors are still not ready, then the OPID in the SACK response
The field will display the first of the processors with the lowest readiness state. The "wait master" instructs the processor to become the new "wait master". Eventually, all processors will be ready, but until then, the system will only attempt to query the status each time at least one processor is notified that it has reached the ready state. It is. Thus, the system is not burdened with periodic status queries that consume resources without producing results. Further, according to this method, the system can surely know that all the processors have completed their work just at the time when the processing to be completed last is completed. As will be appreciated by those skilled in the art, a wide variety of other "standby" configurations can be employed within the scope of the inventive concept.

The "start merge" command is one special type of test and set instruction. If the status of the global semaphore is “ready to send” or “ready to receive”, the current transaction number register (PTNR) 206 (see FIG. 13) sends a “merge start” message (see FIG. 3). Is set to the value of the transaction number in parentheses, thereby setting the PTNR register. If any of the running processors is in a lower readiness state, the value of PTNR is not changed.

The “merge stop” command is a reset operation corresponding to the above operation, and the PT of all active processors is
It unconditionally resets NR to "TN0".

As will be explained later, only messages related to the current global task specified by PTNR will be sent to network interface 120.
It is supposed to be output from. Thus, the "Start Merge" and "Stop Merge" commands provide the ability to time multiplex, or time multiplex, the network between multiple tasks, and thus Can be arbitrarily stopped and / or resumed.

Of particular interest in the details of the invention are the network
The interface 120 allows the TN to be accessed by a command from the network and the T by the microprocessor 105.
There are times when N's access is never done at the same time. In the present embodiment, this is accomplished by a signal being sent from the receive status control circuit 260 to the read / write status control circuit 270,
This signal is in the "positive" state whenever a command from the network that may change the TN is being processed. During a brief period in which this signal is in the "positive" state, the processor has been inhibited from accessing the HSRAM by the control circuit 270. As will be appreciated by those skilled in the art, a wide variety of alternative configurations to the above configurations may be employed within the scope of the present invention.

Receiving Control Another function of the TN is controlling incoming messages.
By using the "Assign TN" command, it is possible to associate an input message stream in multiple processors for a given task. When the TN assigned to the task in a given processor is set to "ready to receive", the TN is
A count value indicating the number of packets ready to be accepted by the processor is also displayed (FIG. 12). The network interface 120 decrements this count after each successful receipt of an individual packet (this is done by arithmetically subtracting a "1" from the word in TN), and this decrement is It continues until the count value reaches zero. When the count value reaches zero, a "NACK / overrun" response is generated, which makes the processor sending the packet ready to accept more incoming packets for the processor sending the packet. You are informed that you have to wait until.
Furthermore, as can be seen from Fig. 18, at this time, the PTNR
The reset to "TN0" is also performed.

With the above operation mechanism, it is possible to directly control the flow of packets flowing through the network. It also ensures that one processor is not packed with large amounts of unprocessed packets and that the processor does not become a bottleneck for the system.

Transmission control As shown in FIG. 21A, as shown in FIG.
Each message stored in the HSRAM includes a field for containing a value of a new TN vector (= next message vector). If the message has been sent and the response to it has been successfully received, the new TN vector contained in the message just sent contains the new TN vector.
Stored (transferred from PTNR) to the address in S.RAM to store the current transaction number.
Therefore, the TN is updated each time an individual message is sent, and it is possible to automatically set the TN to a desired state upon successful transmission of the message. .

Referring to Figure 12, the "ready to send" TN format contains an address in the 14-bit HSRAM that points to the next packet to be output for a given task (TN). It is used to Thus, the TN stored in HSRAM also serves as a head pointer to the head of a first-in, first-out (FIFO) queue of messages for various tasks. Thus, as far as one given task (TN) is concerned, each processor will have a new TN
Attempts will be made to send packets in the order defined by the vector chain.

By combining with the mechanism for multiplexing the network at high speed (multiplexing) between multiple TNs (tasks) described above, it is possible to realize many sets of complicated combinations distributed among many processors. Clearly, tasks will be managed with very small software overhead. The configuration provided by the co-operation of networks, interfaces and processors can distribute its copy among hundreds of processors, and even among thousands of processors. This is a suitable configuration for allocating and deallocating resources, suspending and resuming tasks, and other controls for resources and tasks that can be performed.

Example of DSW (Destination Selection Word) The destination selection word (Fig. 3)
In cooperation with the SAW section of Figure 13) and HSRAM 26 (Figure 8), it provides multiple modes that allow: That is, what are those modes?
The network interface 120 of each receiving processor is such that the message being received is associated with that network interface.
There are a plurality of modes that allow the user to quickly determine whether or not the processing is intended to be performed by the processing 105. As described above, the DSW included in the received message selects the nibble stored in the DSW section of HSRAM and is compared with the nibble.

Processor Address As shown in FIG. 8, one portion of the DSRAM section of HSRAM is dedicated to storing processor address select nibbles. In the present system, each of the 1024 mountable processors is associated with one of the bit addresses contained in this portion of the HSRAM. The bit of the bit address associated with the processor's ID (identity) is set to "1", while all other bits in this section are set to "0". Thus, each processor has only one bit in this section set to "1".

Hash Map Another part of the DSW section of HSRAM is dedicated to storing hash maps. In the present system, two of the map selection bits are assigned to their hash maps, resulting in two complete sets containing all 4096 possible values. In hashed mode, the keys for the records stored in secondary storage are set according to a hashing algorithm, thereby assigning a "bucket" between 0 and 4095. . The processor responsible for the record contained in a given "bucket" has the "1" bit set in the mappy bit whose address corresponds to the bucket number of the bucket. . The other bits are set to "0". A given processor can be responsible for multiple buckets simply by setting multiple map bits.

In the structure of this embodiment, as will be easily understood, the setting of the map bit can be performed by the following method. That is, the method is given 1
Regarding one mappy selection bit, each bit address is set to "1" in only one processor, and any bit address is always set to "1" in any processor. Is. As a direct result of adopting this approach, each processor (AMP) shares a distinct, disjoint subset of the records in the database, and the overall system as a whole contains all of the records. Sets have come to exist.

Although the above examples have been described with reference to the problem of relational databases, as will be readily appreciated by those skilled in the art, disjoint subsets of the problem can be separated into individual Any task area that can be assigned to the processor,
The same scheme can be applied.

One more thing worth noting is that the complete map
Configuring one of the above-described schemes so that a bucket assigned to a given processor in one map can be assigned to a different processor in the other map. It means that you can Here, if one map is "primary" and the other map is "backup", the direct consequence is that the record that is primary on a given processor is: You can ensure that it is backed up on another processor. Further, there is no restriction on the number of processors that back up a given processor.

As will be appreciated by those skilled in the art, the number of distinct maps that can be implemented within the scope of the present invention can be three or more, and the number of buckets can be any number.

In each of the processor addresses and hash maps described above, examining the given one bit address for all processors results in the bit address being a "1" in only one processor. It can be seen that the corresponding bit address in all other processors is set to "0". However, a scheme in which the corresponding bit address is set to "1" in a plurality of processors is possible and useful. This method is called a "class address" mode.

The class address can be thought of as the name of a procedure or function whose copy exists in multiple processors. Any processor having the corresponding processing procedure or function has "1" in the corresponding bit address.
Bit is set.

To send a message to a class address, the corresponding class address in the DSW (FIG. 3) is set. All operational processors that are shown to "belong" to the class by setting the bit in the corresponding position in HSRAM to "1" will have their message packet sent out. Will be answered with "ACK". Processors that do not belong to the class respond with NAP.

Therefore, DSW allows the routing computations necessary to control the flow of messages in a multiprocessor system to be performed by the hardware. Also, the program can be independent of the knowledge of which processor has the various functions of the system. Furthermore, because the map is part of the HSRAM and is thus accessible from the microprocessor 105, it is possible to dynamically relocate certain functions from one processor to another.

Merging Examples In complex multiprocessor systems, tasks may require the execution of a series of interrelated operations. This is especially true for relational database systems that handle complex queries, in which data is assembled into files and then assembled in a particular manner. It may be necessary to refer to multiple secondary storage devices to create a file that can be redistributed to other processors. The following examples show how the systems of FIGS. 1, 8 and 13 can easily perform such functions by manipulating the TN, the DSW, and the global semaphore. This is a brief explanation of whether

First, there is a merge coordinator (typically, the merge coordinators are IFPs 14 through 16, but are not necessarily limited to them).
A plurality of AMPs belonging to one class that will be formed by merging two files (that is, functioning as a data source) are identified (among AMPs 18 to 23). One unassigned TN is selected and assigned to identify the data source function. It was not assigned until then for the second major function of distributing or hashing this file to another set of AMPs (which may be the processor of the original data source). Another TN is assigned.

The coordinator for this merge function is the first TN
Identify, using DSW, a plurality of processors belonging to a class that will perform merging work in files related to. The participating processors involved in this merging work raise the status level of the TN to "Bizy" or "Waiting" status,
Thereafter, control of the merge operation is passed to one of the participating processors involved in the merge operation (ie, the coordinator's work is delegated). Each of these multiple participating processors (all other processor modules are non-participating processors with respect to their transaction numbers) receives and receives message buckets for the tasks of the merge thus defined. After sending an acknowledge to the processor, the execution of the subtasks of the processor itself proceeds while updating the status level accordingly. Then, when the processor delegated the job of the merge coordinator has completed its own task, the processor shall send a status message to all other participating processors to inform them of the status regarding the transaction number. A request may be sent, thereby receiving a response indicating which of the participating processors has the lowest readiness state. Control of the merge operation is passed to the processor with the lowest readiness, after which it can poll all other participating processors when it has completed its work. If desired, the above process can be continued until a response is received indicating that all participating processors are ready. The processor, acting as the coordinator at the time such a response was received, will then
While using W to identify the participating processor that belongs to the class, transfer of the message to HSRAM26 is started. It is updated to "Ready to send". If the polling that is subsequently performed reveals that all participating AMPs are ready for transmission, the coordinator issues a start merge command for that particular TN.

While the merge operation is running, the processed data
The packets will be forwarded to a plurality of processor modules belonging to a class for distributing the results to secondary storage according to a relational database. Regardless of whether the plurality of receiving processors are the same as the plurality of processors that are the senders at this time, the participating processors belonging to the class involved in this distribution (that is, the receiving processors) are:
The transaction is identified by the DSW, and the transaction is identified by the new TN. For all participating processors involved in this new transaction, this new
A TN will be assigned and their participating processors will raise their readiness state level to "ready to receive". This DSW can be hashing-selective rather than class-specific, but in all cases, all participating processors can receive broadcasted messages while the merge is in progress. It is in a state. If a "merge start" is issued, a plurality of message packets from each of the sending participating processors to be involved in the sending operation, and simultaneously from each processor to each other, are sent out onto the network, and the message packets are added to the message packets. On the other hand, the priority is dynamically determined (during transmission). If each sending participating processor completes sending its own set of messages, then each of those sending participating processors has a defined "End of File". Attempting to send a message, this "end of file" message has lower priority than the various data messages. This "end of file" message will continue to lose contention with the data message until all of the participating processors start sending "end of file" messages, and will be sent from all participating processors. Finally, the transfer of an "end of file" message is achieved.
Once this transfer has been completed, the coordinator
"End of Merge" message,
You can also perform a "TN Abandon" following it,
This "TN abandonment" ends the transaction. Overrun, error, or lock conditions can be properly addressed by restarting the merge or transmission.

When the merge operation for one TN is completed,
The system may shift to the next TN in the sequence of TNs. Once each processor module has created a queue of message packets corresponding to this new TN, the processor modules will again start working on the network to perform the merge operation. It becomes possible. Due to the efficient use of the in-network merge operations, in addition to the individually performed intra-processor merge operations, this system provides a significantly larger sort / Merge tasks can be performed.
When the present invention is adopted, the time required to sort a certain file in the system can be expressed by the following formula, where n is the number of records and m is the number of processors. .

In this equation, C ₂ is a constant and for this example is estimated to be about 10 microseconds when 100 byte messages are used, and C ₁ is a typical 16-bit microprocessor. About 1 if used
It is a constant estimated to be milliseconds. N in various combinations
The approximate sort / merge times for the combinations of and m are shown in the following table in seconds, and their values are those when 100 byte records are used.

It is not easy to evaluate the numbers of the specific examples shown in the above table in comparison with the conventional system. The reason is that two kinds of interrelated sort processing sequences (sort by processor and sort by network) are involved, and in the first place, there are almost no systems having such a capability. Because. In addition, the system sorts and merges long and variable messages, whereas
In general, many sort capabilities are evaluated in terms of bytes or words.

Yet another important factor is that the system is a multiprocessor itself, not a dedicated system for sort / merge processing. The system is able to shift between merge and non-merge operations locally and globally with complete flexibility, and this shift can be done without any software penalty. , Without any loss of system efficiency.

Example Task Request / Task Response Cycle Referring to FIG. 1, any processor 14, 16, or 18-23 connected to network 50 may cause one or more other processors to perform the task. Of the task request is formed in an appropriate format in the form of a message packet. In a relational database system, most of these tasks originate from the host computer 10, 12 and are input into the system via interface processors 14, 16, except that This is not a requirement. This message packet, formed in the proper format, is injected into the contention on the network for contention with packets from other processors, and the priority level of other tasks as well as the state of operation on this processor Depending on your level, you may sometimes get priority. A task may have its contents specified by one message packet, or may be specified by multiple continuation packets, but the continuation packet that follows is a group of data messages (11th (See figure), a relatively high priority level is assigned, so that the delay in receiving the following parts is as short as possible.

The message packet contains a transaction identity (= transaction identification information) in the form of a transaction number. This transaction number is a non-merge mode, which is the mode related to the method for extracting the processing result, that is, the default mode (“TNO”) and the merge mode (“TN
All TN except "O") is inherently provided with the property of distinguishing according to the selection. Further, the message packet contains the DSW. This DSW essentially specifies the transfer destination processor and the mode of multiprocessor operation. This specification is performed by specifying a specific processor, a class including a plurality of processors, or specifying hashing. In this embodiment, hashing is hashing a part of the relational database. A message packet that is broadcast to the target processor (designated destination processor) via the network 50 is locally accepted by the processor (= the acceptance by the processor itself is appropriate). The authentication is performed by an acknowledgment (ACK). Processor 14, 1
6 and 18 to 23 all send responses simultaneously to the network 50 following the EOM (end of message), however, the ACK sent from the designated destination processor takes priority. , And will be received by the originating processor.

Then, the designated transfer destination processor sends the received message to the local microprocessor through the local HSRAM (= HSRAM provided in each processor module) and the interface 120 (FIGS. 8 and 13). When it is transferred to, the processing requested by this request packet (= message sent) is executed asynchronously (= out of synchronization with elements other than the processor module in question). When a relational database task is performed, the DSW typically specifies a portion of a disjoint data subset (which is stored on the disk drive for that subset). However, at times, a task may be performed that does not require browsing the stored database. A specific operation or algorithm may be executed by each processor, and when a plurality of processors are designated as the designated transfer destination processor, each of those processors
The task may be performed on a disjoint subset of the entire task. The variable-length message packet is configured so that an operation to be performed and a file to be referenced in the database system can be specified by a request message. Note that there may be a large number of message packets for a given task, in which case the discrimination criteria for sorting performed inside the network Key field that can be arbitrarily adopted in order to provide an appropriate characteristic (FIG. 3)
Is becoming important.

The task response packet generated by each processor attempting to respond is forwarded from the microprocessor to the local HSRAM 26 via the control logic 28 of FIG. 1, where the task response packet is shown in FIG. 21A. Stored in outgoing message format. If the task response is one that requires the use of a continuation packet, then such a continuation packet is sent after the first packet, but given a higher priority for continuation. It If the system is operating in merge mode and each processor is generating a large number of packets for one transaction number, those packets are first locally (= individual processor = Chaining (internally) in the sort order, and then merging over the network 50 can be arranged in a global sort order.

The task result packet consists of processors 14, 16 and 18-23.
To the network 50 to form a group of simulcast packets, and one top priority message packet is broadcast back to all processors after a predetermined network delay. The transfer of those task result packets depends on the nature of the task.
In some cases, the source processor that originally issued the request message is used as the transfer destination.
The transfer may be performed with one or a plurality of other processors as the transfer destinations. Further, the transfer may be performed in any of the plurality of multiprocessor modes described above. The most common case in a relational database system is to perform merging and redistribution at the same time while selecting a destination using hashing. Therefore, as can be understood from that, "task request /
Within the "task response" cycle, each processor can operate as the originating processor, as the coordinator processor, and as the responding processor, and even as all three. You can also do it. Due to the involvement of many "task request / task response" cycles, processors 14, 16 and 18-23, and the network
50 are multiplexed between those tasks, provided that the multiplexing is based on time and also on a priority basis.

Example of a Complex Query In a relational database system, host computers 10, 12 are used and further define tuples and disjoint data subsets of primary and backup data. Complex queries are input to the system from the host computer 10 or 12 via the IFP 14 or 16 using a distribution method that distributes the relational database among the multiple disk drives 38-43 according to an algorithm. Is done. The input query message packet is first analyzed in detail by the IFP 14 or 16, which analyzes messages from the host computer to request the AMPs 18-23 to perform tasks. This is performed to convert the request into a task request. Upon starting its operation, the IFPs 14 to 16 send out a request packet for extracting information from one or more specific AMPs, which is necessary for detailed analysis of the message from the host computer. It may be necessary to obtain in-system data. Once you have the data needed to process the request from the host computer, IFPs 14-16
Several "task request / task response" cycles can be performed with the MPs 18-23 and the data can be actually processed to satisfy the request from the host computer. In the above-described processing sequence, the cycle including the task request and the task response described above is used, and the cycle can be continued for an arbitrary length. continue,
IFPs 14 through 16 communicate with a host computer via an IFP interface. This response to the host computer may simply be to provide the data that the host computer 10 or 12 needs to generate the next complex query.

(Stand-Alone Multiprocessor System) The basic embodiment of the system according to the invention described above in connection with FIG. 1 comprises a host computer as well as software for the host computer currently in use.
9 illustrates an example of a post-processor (back-end processor) that can be used in combination with a package. However, as already mentioned, the present invention can be used in a wide variety of processing applications, and especially in those types of processing applications in which processing tasks can be easily subdivided and distributed without the need for large amounts of central processing power. , With particular advantages. FIG. 20 shows an embodiment of a simple configuration of a stand-alone (stand-alone) multiprocessor system according to the present invention. In FIG. 20, a plurality of processors 300 are all connected via an interface 302 to an active logic network 304, which is a network similar to that already described. Active logic network 30 with redundancy to enhance data integrity
4 may be adopted. Also in this embodiment, a 16-bit microprocessor chip can be used for the processor 300, and a main RAM memory having a sufficient capacity can be incorporated. Only nine processors 300 are shown in this figure, and each of those processors has a different type of peripheral connected to it to illustrate the versatility of the system. is there. In practice, this system is much more efficient by having more processors in the network, however,
Even with a relatively small number of processors, there are particular advantages in terms of system reliability and data integrity.

In this embodiment, the plurality of processors 300 can be physically separated from each other by a sufficient distance without inconvenience, assuming that the data transfer rate is the same as that described for the previous embodiment. The maximum spacing between them can be as much as 28 feet (5.5 meters), so multiple processors in a large array do not unnecessarily jam on one floor or several adjacent floors of a building It can be installed and used in such a way.

In a stand-alone system, much more types are used for the peripheral controller as well as for the peripheral itself, as compared to the post-processor embodiment described above. Here, for convenience, the individual input / output devices are:
It is assumed that each is connected to a separate processor.
For example, an input / output terminal device 310 having a keyboard 312 and a display 314 is connected via a terminal controller 320 to a processor 300 for the terminal device 310.
However, in the case of a terminal device having a relatively low operating speed, a terminal device network of a considerable scale is connected to one 16-bit network.
It is not impossible to control with a processor. The illustrated input / output terminal device is merely an example of how a manual operation input processing device such as a manual operation keyboard is connected to the system. Processor
Utilizing the processing power of 300, the terminal device 310 can be configured as a word processor, and the word processor can communicate with a database or another word processor or various output devices via the network 304. it can. For example, a high-capacity secondary storage device such as a rigid disk drive 322 can be connected via a disk controller 324 to a processor for the storage device. Also, as will be readily appreciated, larger systems require more disks / disks.
A drive or a different type of mass storage device may be used. Output devices such as printer 326 and plotter 330 interface to a processor 300 for those output devices via a printer controller 328 and a plotter controller 332, respectively. Interactions with other systems not shown occur via the communication controller 338 and via the communication system 336, which may be, for example, a teletype network (TTY) or a larger system. One of the networks (eg Etherne
t)) etc. are used. Some of the processors 300 are simply connected to the network 304 without connecting peripheral devices.
(Not shown).

Two-way data transfer can occur
Tape drive (tape drive mechanism) 340 and tape
For example, when the drive controller 342 is used, and when the floppy disk drive 344 to which the controller 346 is connected is used. In general, tape drives not only provide a large storage capacity when used in an online connection, but can also be used for backup of disk drives. For the purpose of this backup, tapes are used to store data stored up to a certain point in a sealed rigid disk drive. Such backup operation is
Network 304 can be used to perform long "streaming" transfers, since it typically occurs during light load times (eg, nights or weekends). In addition, the floppy disk drive 344 may be used to enter programs during system initialization, so some of the network time will be spent in this "streaming" mode. Can transfer a significant amount of data. The optical character reader 350
It serves as a source of further input data, which is input to the system via its controller 352. A peripheral device simply described as "other device 354" can be connected to the system via the controller 356 so as to perform other functions as needed. .

Send respective message packets from different processor modules at the same time to each other and make a priority decision on those message packets to
An individual processor that is on-line because it uses a scheme that allows one or a common top priority message packet to be simultaneously broadcast to all processor modules within a certain fixed time. Are equally accessible to other processor modules in the system. This global semaphore system, utilizing a prioritized transaction number and readiness status indication, and a destination selection entry included in the message, allows any processor to act as a controller. Therefore, this system can operate in a hierarchical system or a non-hierarchical system. It is also very important that the system can be scaled up or down without requiring software review and modification.

Even if access is required to a message that is much longer than the message length already described, but is still of relatively limited length, such access can be performed. For example, a complex computer
With respect to graphics devices (not shown), it may be necessary to access only certain parts of a vast database to create sophisticated two-dimensional and tertiary graphics. Also, for word processing systems, only a small sequence of data at a time may be required from the database due to the slow operation speed of the operator. In these situations, and similar situations, the system's ability to handle variable length messages, as well as the ability to prioritize continued messages, would be beneficial. Circumstances that require centralized processing or transfer of extremely long messages limit the use of this system, but in other situations the system can perform very well. I do. The dynamic situations involving the manipulation of various different data formats and the attendant sorting or merging functions all correspond to situations in which the present invention can be used to advantage. Business decision making, including collecting, collating, and analyzing complex data is one example of such a situation, and the creation and editing of video and graphical inputs for periodicals is also an issue.
This is one example.

Conclusion As will be apparent to those skilled in the art, the system of FIG. 1 allows the number of processors contained therein to be any number (but determined by the data transfer capacity) without the need to modify the software. It can be extended (to the practical limit). It is also evident that the system shown in the figure is used for checking the status of each processing unit, setting tasks and priorities of processors, and ensuring efficient use of the processing power of the processors. It significantly reduces the need for management and overhead software.

The obvious benefit comes from database systems and other systems where it is appropriate to subdivide an entire task, like a database system, into subtasks that can be processed independently of each other. And so on. For example, in relation to a relational database, if the capacity of the secondary storage device is significantly increased, it is only necessary to appropriately integrate a further database into a data structure composed of primary data and backup data. is there. In other words, the network can be extended indefinitely, which is possible because the standardized intersection devices or nodes are connected in a binary-evolving connection scheme, This is because the functions executed in those individual nodes are not changed by the extension. Furthermore, a setting processing sequence and an external control for the operation of the node are not required. Thus, when the system according to the present invention is connected to function as a back-end processor for one or more host computers, as shown in FIG. Optionally expand (or shrink) the database without changing the operating system software or application software
can do. Host processor system (=
From the host computer's point of view, this backend processor is "transparent" regardless of its configuration, because the backend processor and host This is because there is no change in the manner of interaction with the processor system. This backend processor has another host
To switch to do the work of the processor system, IFP simply requires that the new host processor
All you need to do is properly communicate with the system's channel or bus.

According to the configuration of the network in an embodiment of a real machine, a single array can be used without causing a significant delay in message transfer in the network and without an unreasonable delay due to contention between processors. Ten
Up to 24 microprocessors can be included and used. It will be apparent to those skilled in the art how to extend the embodiments described herein to include more than 1024 processors. When 1024 processors are used in one system, the maximum line length between active nodes is
It has been found to be 28 feet, and this line length does not pose a problem in constructing the array.
The delay time due to the network is a fixed time 2τN for any message, where τ is the interval between byte clocks and N is the number of layers in the hierarchy. Obviously, doubling the number of processors by adding one more layer will only increase latency slightly. Since a data message is essentially a long message (about 200 bytes long), the priority judgment for all competing messages transfers the data along the network. Because of this, the network is able to transfer data messages much more efficiently than conventional systems.

Among the important economic and operational features of the system are the fact that standardized active logic circuits are used in place of software and even firmware in network systems. There are features. That is, due to this fact, it is possible to incorporate a highly reliable circuit at a relatively low cost with respect to the total cost including the cost of the processor and the cost of the peripheral device by using the technology of modern LSI and VLSI. It is possible to do.

The time and expense spent on software is limited to only those important parts, such as those involved in task-related tasks such as database management. For example, the configuration of the system allows all of the functions required to maintain the integrity of the database to be performed within a range based on the configuration of the message packets and the configuration of the network. ing. Functions such as polling, status change, and data recovery are performed inside the system.

Yet another important consideration is that the high speed data transfer performance of the network of the present invention is sufficiently superior to that of conventional ohmic wiring buses. Since multiple message packets are sent simultaneously to each other and priority is determined while they are being transmitted, the status
This is because the delay associated with the sending of the request and the response thereto and the determination of the priority is avoided. Furthermore, even if the number of processors is enormous, the length of the connection structure between nodes can be suppressed to a predetermined length or less, so that the propagation time in the bus is a constraint on the data transfer rate. Nothing.

The system has been found to be near optimal in terms of microprocessor and network utilization. Important in these respects is to ensure that all microprocessors are kept busy and that the network is fully utilized. "IFP-Network-AM
The composition of the "P" makes them possible in effect,
The reason for this is that a microprocessor that has sent a message packet out of competition for priority will only have to retransmit at an appropriate time as soon as possible, which results in a high bus duty cycle level. Because it is maintained at. Fast random access memory also contributes to this effect because it stores both input message packets to be processed and output message packets to be sent out inside. Because each processor can always obtain the backlog of the work, the network can also obtain the backlog of message packets. When all the input buffers are full, the processor sends an indication on the network to indicate this fact. Also, when the input buffer used for receiving the message from the host computer used for the IFP becomes full, an indication to that effect is sent out on the channel. Thus, the system is self-starting, both internally and externally.

The system is configured to perform many other functions required for a general purpose multiprocessor system by utilizing the architecture and message organization as described above. For example, in the prior art, great attention was paid to schemes for assessing and monitoring changes in the status of global resources. In contrast, in accordance with the present invention, only the parity channel is provided and used as a means of communicating both the occurrence of parity errors and the fact of changing processor availability. If one or more processors shut down, the shutdown is communicated to the system substantially simultaneously with its occurrence, so that execution of the interrupt sequence can begin. I have. Because multiple responses are sorted according to priority, if a global capability change occurs, the nature of the change will be much greater than in the past. It can be specified by small-scale circuits and system overhead.

The global response achieved through a single query and priority determination, achieved by employing a global semaphore and an active logic network, has very deep system implications. Broadcasting queries in this manner provides unambiguous and unambiguous global results, eliminating the need for complex software and overhead. Status setting operations such as distributed update can be performed even when a large number of simultaneous operations are being executed by a plurality of different processors.

Further, the present system exerts an excellent ability regarding work distribution and processing result collection in a multiprocessor system by using the above network, transaction number and transfer destination selection word. Different multiprocessor modes and control messages are available, and different levels of priority can be easily set and changed by simply manipulating the priority protocol. .
The combination of the ability to broadcast to all processors simultaneously and the ability to sort messages in the network allows any processor group or any individual processor to be the destination. In addition, the processing results can be extracted in an appropriate order. Thus, when a complex query to a relational database system is entered, it initiates any processing sequence required for database operation.

Yet another advantage of the present system is that redundancy can be easily introduced into multiprocessor systems, such as relational database systems. Having a dual network and dual interfaces provides redundancy so that the system can continue to operate if one network fails for any reason. Since the databases are distributed in disjoint temporary and backup subsets, the probability of data loss is reduced to a minimum level. In the event of a failure or modification, the integrity of the database can be maintained due to the availability of a variety of versatile control functions.

[Brief description of drawings]

FIG. 1 is a block diagram of a system according to the present invention including a novel bidirectional network. FIGS. 2 and 2A to 2J are successive series over time showing the manner of transmission of data and control signals in the network of the simple structure embodiment shown in FIG. FIG. 2 is a diagram showing a state before the start of signal transmission, and FIGS. 2A to 2J show ten successive positions from t = 0 to t = 9, respectively. It is a figure corresponding to one of the time samples at the time point. FIG. 3 is an explanatory diagram showing the structure of a message packet employed in the system shown in FIG. FIG. 4 is a block diagram showing further details of the active logic nodes and clock circuits used in the novel bidirectional network shown in FIG. 1; FIG. 5 is a state diagram showing various operating states inside the active logic node. FIG. 6 is a timing diagram for explaining an end-of-message detection operation performed inside the active logic node. FIG. 7 is a timing waveform diagram for explaining the operation of the clock circuit shown in FIG. FIG. 8 is a block diagram of a processor module including high speed random access memory that can be used in the system shown in FIG. FIG. 9 is a diagram showing the state of address allocation inside the main RAM of the microprocessor system shown in FIG. FIG. 10 is a block diagram of the high-speed random access network shown in FIG.
FIG. 3 is a block diagram of a data arrangement mode inside one reference portion of a memory. FIG. 11 is a chart showing a message priority protocol used in the system. FIG. 12 is an explanatory diagram illustrating the word format of the transaction number. 13 and 13A are block diagrams of an interface circuit used for each processor module provided in the system shown in FIGS. 1 and 8, and FIG. FIG. 13A is a diagram that leads to one sheet by placing FIG. 13A. FIG. 14 is a timing diagram illustrating various clock waveforms and phase waveforms used in the interface circuit of FIG. FIG. 15 is a block diagram showing further details of a memory configuration and one type of mapping for performing mapping based on a transfer destination selection word. FIG. 16 is a simplified flowchart showing a status change upon receipt of an input data message. FIG. 17 and FIG. 7A are flow charts showing changes in status when a message is being received, and are diagrams in which FIG. 17 is brought into contact with the upper edge of FIG. Is. FIG. 18 illustrates the relationship between the various primary messages and the various responses generated thereto, as well as the relationship between the various primary messages and the actions performed in response to them. It is a table shown. FIGS. 19 and 19A are flow charts showing the status change when a message is being transmitted. It is. FIG. 20 is a block diagram of a stand-alone system according to the present invention. FIG. 21 consists of FIGS. 21A and 21B and shows the messages stored in the high-speed random access memory. FIG. 22 is a simplified schematic diagram showing one possible distribution scheme for distributing portions of a database among different processors in a database system. 10, 12 ... Host computer, 14, 16 ... Interface processor, 18-23 ... Access module processor, 24 ... Microprocessor, 26 ... High-speed random access memory, 28 ... Control logic ,
32 …… Disk controller, 38 ～ 43 …… Disk ・
Drive, 50 ... Active logic network structure, 54
...... Node, 56 …… Clock source, 120,120 ′ ……
Network interface, 103 ... Microprocessor system.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor David Henri Hartuk, Los Angeles South Geneva 1427, California, United States of America 1427 (72) Inventor Litchard Clarence Stutskton, North Ritz, Merrion Drive, California, United States 19005 (72) ) Inventor Martin Quimeron Watson North Lithuania Kyabrian Avenyu, California 11112 (72) Inventor David Kronshio Trans Towers Street, Calif. United States 5635 (72) Inventor, Jayak Everd Siemer, Los Angeles, Calif.・ Angels Auciano Dry U.S. Pat. No. 4,251,879 (US, A) IBM Technical Disclosure Bulletin 22 (12) P. 5450-5452 (1980)

Claims (7)

(57) [Claims] 1. A multiprocessor system for processing a plurality of tasks using distributed processor resources for executing subtasks of the tasks, the identification information unique to each task to be executed. And at least one processor means of the first type for creating a plurality of subtasks to be distributed and processed.
A kind of processor means sends out the assignment of work for a plurality of subtasks in the form of message packets, executes the subtasks and sends reply messages to the message.
A plurality of second type processor means 2 for sending in the form of packets, both of the first and second type processor means for sending message packets synchronously; And an active bus means for interconnecting the processor means of the second kind, said active bus means receiving a plurality of message packets sent in synchronization between the plurality of message packets competing with each other. For determining the priority of each of the processor means and transmitting one priority message packet to all of the processor means at the same time, so that many subtasks can be processed simultaneously by using the plurality of processor means. Processor system. 2. The active bus means has a plurality of nodes, and based on the contents of a plurality of competing message packets at each of the nodes, determining priority among the competing message packets. A multiprocessor system according to claim 1 including means for performing. 3. The first-type processor means includes interface processor means including means for merging processed subtasks based on the unique identification information, and the second-type processor means includes processing means. An access module processor for issuing a completed subtask in response to a request from the first type processor, the access module processor having a uniquely distributed data memory resource and receiving 3. The multiprocessor system according to claim 2, further comprising means for recognizing whether or not each subtask is a subtask that requires access to the data memory resource allocated to itself. 4. At least one host computer system having a system channel and submitting tasks on the system channel, and connecting the system channel to different individual terminals of the active bus means. At least one interface processor comprising: means for sending a plurality of message packets to said active bus means in response to a message packet received from said system channel, A multi-processor system as claimed in claim 3. 5. The active bus means comprises network means, said network means comprising:
Message transmission means for transmitting a message with a uniform transmission delay time between a processor means and said access module processor and between different access module processors, said processor transmitting 5. The multi-processor system of claim 4 including means for terminating the transmission in response to the failure of said transmission and means responsive to receiving the transmission. 6. The interface processor means includes an interface microprocessor,
The interface microprocessor is connected to the host computer system as well as to the terminals of the active bus means,
The multiprocessor system according to claim 5, which controls transmission of tasks to and from the system. 7. The interface processor means of claim 6 wherein said interface processor means includes a channel interface connected to said system channel and a further interface connected to said active bus means. Multi-processor system.