JPH0426726B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial application field) Data transmission system and clocking system
It is related to. (Prior technology) Highly reliable electronic computer (electronic computer)
Since the advent of the computer
This system has been carefully considered by people working in the technical field of
system that uses multiple computers
, and those computers are mutually related.
By operating while maintaining
I have a system that allows the whole screen to run.
Ru. For such multiprocessor systems
In some systems, one large computer
However, with its own superior speed and capacity,
In addition to executing complex parts of the program, the complexity
for less demanding or less urgent tasks.
then convert it to a small, slow satellite processor.
delegate (assign) and thereby
The burden on the computer and the burden on this large computer
There is a method that reduces the amount of requests.
Ru. In this case, a large computer can perform subtasks
Allocating small processors (=
Satellite processor) must be kept in working condition at all times.
The usability and operating efficiency of these small processors
to ensure that uniform results are obtained.
shall be in charge of ensuring that the Another type of multiplayer that uses a different method than the above.
Some processor systems contain many
A system using a bus and one common bus system
stem and those multiple processors have a book.
Systems with qualitatively equivalent functionality
There is a problem. In this type of system, it is often
For example, a control computer independent from other parts.
or control system to perform a given subtask.
availability and processing of individual processors for
Monitoring performance and inter-processor tasks
and control the information transfer route.
ing. Also, the processor itself
monitoring the status and availability of Setsa;
Determining the transmission route for messages and programs
The configuration and operation of each processor
Some of the works are set. The above various scenarios
A major drawback common to stems is overhead
Software is used to perform functions and maintenance functions.
It is said that
In particular, and thereby achieving the original purpose.
This will affect implementation. Determining the transfer route and
The amount of work related to
increases as a quadratic function of the total number of processors
In particular, due to overhead functions,
Efforts may become expended. The following several patent publications provide examples of prior art.
It is. U.S. Patent Publication No. 3962685 - Belle Isle No. 3962706 - Dennis et al. No. 4096566 - Borie et al. No. 4096567 - Millard et al. No. 4130865 - Hart (Heart) et al. No. 4136386 - Anunchiata
(Annunziata et al. No. 4145739 - Dunning et al. No. 4151592 - Suzuki et al.
(using parallel-connected processors) or
When various systems similar to this were in use.
Since then, multiprocessor systems have already been equipped with redundancy.
It provides the ability to perform
significantly improves the overall reliability of the system
It was recognized that it was something to be gained. fruit
When configuring a multiprocessor system
So far, considerable progress has been made in
Constraints exist, but they are primarily software
This is due to the fact that toeware has become enormous.
This is a constraint. Nevertheless, for example, real
System downtime, such as time usage, etc.
There are various situations where downtime is unacceptable.
In situations where multiprocessor operation is particularly
Due to its advantages, various multiprocessing
The tusa system has been developed, but
Although these systems work well,
Software and operating time for bar head?
It is something that you have to allocate a certain amount of money to.
Ta. Such conventional systems are described in U.S. Pat.
No. 3445822, No. 3566363, and No. 3593300
A specific example is shown in the issue. These patent publications
All information is shared between multiple computers.
access one main memory shared by
This is about a system designed to
The system further divides tasks into individual processes.
Processing capacity and processing requirements are
It is now possible to compare the required quantity. Further examples of prior art include U.S. Pat.
There is No. 4099233. In the system of this bulletin,
Multiple processors share one bus,
In addition, a control module with a built-in buffer register is also available.
The sender miniprocessor and receiver microprocessor are
The transfer of data blocks to and from the Niprocessor is
It is done. The concept of this system is
used in a decentralized mail sorting system in
ing. U.S. Patent Publication No. 4,228,496 was commercially successful.
It concerns multiprocessor systems.
In this system, there is a
Multiple buses installed connect to a bus controller.
The bus controller is connected to the
Monitoring of data transmission status and communication between processors
Determines priority for multiple data transfers.
It's on. Additionally, each processor has multiple
to control one of the side devices
It is now possible to connect. Xerox, Heuretsu Pats Card, and
Ether, which is jointly promoted by Intel
“Ethernet” system (U.S.
Patent Publication No. 4063220 and Patent Publication No. 4099024) are
Intercommunication between multiple processors and peripheral devices
suggest yet another way to deal with the problem
There is. All units (=processors and peripheral devices)
etc.) are multiple access points shared among those units.
access network, and
Those units compete with each other for priority.
It will match. Collision detection is performed using a time-first method.
For this purpose, global processing power is required.
controlling, coordinating, and clarifying
It is no longer easy to grasp it accurately. The various systems explained above are explained in detail.
In order to fully understand the
Detailed analysis of patent publications and other relevant references
There is a need. However, the division of tasks is
If the system is
Determination of priority for data transfer and selection of processor
A huge amount of interaction and management control to make choices.
It is only a simple overview that
You will be understood if you just do that. Expand your system
What if you want to include more processors?
Problems like this occur on different systems.
It is not uniform because each person is different, but
However, none of the above systems
Expansion can improve system software and application programs.
logging, hardware, or all three
Everything will become more complicated. Also, some thoughts
It is understood by the observer that one or two
A group of logically passive ohmic buses are adopted.
Because of its inherent limitations, multipro
imposed on the size and capacity of the Setsa system.
It is. Making it easier to communicate with each other
There are various techniques that can be employed to
One example is the recently issued U.S. patent
As shown in Publication No. 4240143, the sub
It is called grouping systems into global resources.
However, there are many techniques.
Naturally, when Rosetsusa is used,
However, the amount of traffic that can be used has reached its limit.
Also, if the delay time takes various values,
This creates problems that are difficult to overcome.
Ru. One or more processors can lock
The condition of being in a deadlock or deadlock state.
situations may occur, and how to deal with such situations.
further circuits and solutions to solve the problem.
software is required. From the above, the process
Set the number of tusa to 1024, for example.
It has traditionally been impractical to significantly expand
It is clear that this is the case. In many different applications, the
Escape from the limitations of existing techniques and use the latest techniques.
It is hoped that it will be used as a maximum resource. Currently hiring
The lowest cost technique possible is
Microprocessors being produced and large capacity
A technique based on a rotating disk type storage device.
Examples of such storage devices include sealed
between the head and the disk inside the case.
Winch-S with very small spacing
There are devices made by Ta Technology. multi pro
When expanding the Setsa system, the software
system without unduly complicating the software.
It is desired to be able to expand the system, and furthermore,
As software expands, it becomes more complex.
I would like to be able to extend it so that there is no
has been done. Furthermore, the entire functionality may be restricted to
or multiple processing tasks that are performed repeatedly
Characteristics that have a distributed structure that can be dynamically subdivided into
The ability to handle computer problems with specific characteristics is required.
It is. Almost all database machines are
belongs to such a problem field and also
The problem areas also include sorting, pattern recognition, and
and correlation calculation processing, digital filtering processing
physics, large-scale matrix calculations, and physical systems.
Other typical problems such as simulation, etc.
Examples are also included. If any of these processes are performed
Multiple tasks handled individually, even in situations where
Keep the tasks relatively simple, yet
It is required to widely distribute the
The instantaneous task load becomes large. Like that
This situation is common in traditional multiprocessor systems.
The reason for this was that it was accompanied by great difficulties.
In such a situation, overhead is
software for time and overhead.
having a tendency to increase the amount of
However, there are practical difficulties in configuring the system.
It's about coming. For example, a passive shared bus may be adopted.
If used, propagation velocity and data transfer
The amount of time it takes to process a transaction
constitutes an absolute barrier to the possible processing speed of
Ru. Therefore, database machines are multiprocessing
of the need for improvements to the tusa system.
This is a good example. Configuring large database machines
Until now, there have been three basic methods for
The following methods have been proposed: hierarchical method,
Network method and relational method
be. Of these, relational data
A database machine represents relationships.
By using tables, users can easily understand complex systems.
for easy access to given data in
This type of machine has a powerful latent
It is recognized that the company has the ability to child
Representative publications explaining the prior art of
For example, the IEEE Computer Magazine
DCP published on page 28 of the March 1979 issue.
Smith and JM Smith's ``Relayoner''
A paper entitled ``The Database Machine''
(article entitled “Relational Data Base
Machine”, published by DCP Smith and J.
M. Smith, in the March 1979 issue of IEEE
Computer magazine, p.28), U.S. Patent Publication No.
No. 4221003 and various theories cited in the bulletin
There are sentences etc. In addition, the sorting machine
Improving the ing architecture is needed.
This is a good example of this. sorting machine
An overview of the theory can be found in ``Search'' by DE Knuth.
Pages 220 to 246 of ``Ning and Sorting''
(“Searching and Sorting” by DEKnuth,
pp.220−246, published (1973) by
Addison Wesley Publishing Co., Reading,
Massachusetts). In this literature
is disclosed by various networks and algorithms.
and understand the constraints that come with each of them.
In order to do so, we must consider them in detail.
No, but there are some general things that can be said about them.
That is, all of them have a special feature called sorting.
in a characteristically complex manner that is oriented solely toward specific objectives.
It means that there is. As yet another example, L.
Presented by A. Mollaar (LA Mollaar).
There is a
'On Computer', Volume C-28, No. 6
(June 1979), pp. 406-413.
"Structure of list merging network"
Article entitled “A
Design for a List Merging Network”,in
the IEEE Transactions on Computers,
Vol.c−28 No.6, June 1979 at pp.406−413)
It is described in. The topics proposed in this paper
Network merging and
A method is adopted in which the elements are controlled externally.
This network also has special
Requires programming to perform functions
ing. Executed by a general-purpose multiprocessor system
There are various functions that must be able to
A function to distribute subtasks according to the method, subtasks
Check the status of running processors
Functions, merging and sorting of messages
functions, the ability to correct and change data;
and how resources have changed (e.g.
When does a processor go online?
There is a function to check whether the device has returned online.
Ru. In order to perform the above functions,
So what about excessive software for overhead?
It was necessary to use hardware and equipment. For example, a database manager
In multiprocessor systems such as
specifies the route for transferring messages between processors.
When transferring a specific processor to
or belong to one class
You can select multiple processors or even
Rather than specifying the rosette itself,
The data distributed to the processors by
transfer by specifying parts of the database.
Choosing a first processor is often
It becomes necessary. Some known systems include front-end communication systems.
There are some products that use
a sending processor and one or more specific
Establish linkage with receiving processor
That's what I do. To establish this linkage
sends requests and acknowledgments over and over again
Destruction that must and may occur
Further hardware alignment to overcome the situation
software must be used to Preposition
In systems that do not use communication sequences,
by one processor or by bus control.
Control is carried out by rollers, and this control
indicates that the sending processor is in the ready-to-send state.
This means that the sending processor is ready to receive.
Is there a linkage between these processors?
and other processors are locked out,
and that no irrelevant transmissions are being made.
This is for confirmation. Also in this case,
Reliance on overhead and deadlock
In order to avoid this, it has to become complicated and
Extend the system (e.g. by
(increase the number of sensors to 16 or more)
It expands to an inappropriate extent. required by modern multiprocessor systems.
As yet another example of the requirement that one or more
subtasks executed by processors
To ensure that the system can determine the status of
There are some things related to the method of basically requested
for a given processor.
Inquire about the status of Rosetsusa
This means that they must have the ability to
Moreover, the status of the inquiry
to avoid being influenced and to respond.
In order to avoid ambiguity in the content of
that an inquiry must be made
be. Suspend testing and setting of status display
Characteristically represents functions that are performed as a series of operations without
Currently, in this industry, the term
The term "semaphore" is used
ing. This feature of semaphore is
However, if this characteristic
When incorporating, please be aware that execution efficiency may decrease and overhead
This must be done in a way that does not increase the load on the tube.
No. Determination of such status is further
Sorting/mapping in multiprocessor systems
is extremely important when performing page operations.
However, it is a complex task contained within a large task.
Combine the processing results of several subtasks
In order for those subtasks to complete processing properly
can be combined into one only after
Because I can't. A further requirement is that the process
Tsusa must be able to report its "current" status.
The tasks that must be performed and the execution of subtasks are
Interrupts the multiprocessor operating sequence
Even if and changes are repeated, they are done only once.
There are times when you have to make sure that the
In most existing systems, the processor's execution
This is a problem because the
A serious problem has arisen. i.e. easily understood
However, multiple processors may
I am running multiple related subtasks.
In such cases, those individual processors'
degree of ines state (= what kind of movement is possible)
Inquiries regarding the degree of
The operation sequences involved in the response to the
bar head may be required, and
The dedicated overhead for
As the number increases, it becomes increasingly inappropriate.
increase (Problem to be solved by the invention)
Typical disadvantages in the Rosetsusa system are
It is related to the problem of so-called "distributed update",
This problem means that each of the plurality of processing devices
A copy of the stored information needs to be updated.
This means that Information here refers to data.
The information may consist of data records;
Information used to control system operation
In some cases. What is the control of the operation of this system?
For example, a required step was inadvertently executed twice.
so that it doesn't run at all
processing is started, stopped, restarted, and
If the time is interrupted or roll back or roll
control such as ensuring that the information is forwarded
That's true. In traditional systems, distributed updates
Each of the various solutions to a new problem requires considerable control.
It was accompanied by a promise. Among those solutions
targets only two processors at a time.
There are some things that are nothing more than Yet another solution
A number of devices use mutual communication protocols.
However, these protocols are very complex.
Therefore, even today, these protocols are not appropriate.
We need to prove with mathematical rigor that
This is accompanied by great difficulties. What makes these protocols so complex?
are the uninterrupted
All processes can be completed in one motion without being interrupted.
After being “tested and set” at the
It is necessary to provide a control bit with the external properties of
The reason is that there is. If such control bits are
provided inside a number of separate processors,
Moreover, it is accompanied by communication between those processors.
Unavoidable incompleteness due to varying delay times
Noise can be caused by communication channels that can cause
occurs, and the error rate also increases.
It turns out. Therefore, “one uninterrupted
One of the features is
The multiple parts that make up the movement are
diverse and interruptible;
cannot be accessed at the same time, and even more so.
These may cause problems between accesses.
If it is difficult, it may be difficult.
This will be readily understood by those skilled in the art. (Means for Solving the Problems) To summarize, the present invention provides
to multiple nodes in a network with nodes.
time skew during the data flow
Master Cloth Connected to Pex Node
disk source and the mask provided on each node.
A unique
using multiple clocks set up, and
It is possible to exist by returning the lost clock.
By correcting possible errors,
We provide a system that eliminates time skew.
It is something that (Example) Examples of the present invention will be described below with reference to the drawings.
do. (Database management system) The system shown in Figure 1 is the main
Applying the concept of invention to database management
This is shown as a specific example. Explain in more detail
, the system can host one or more hosts.
Works with computer systems 10 and 12
are configured and their host computers
The data system is, for example, the IBM 370 family.
– or belongs to the DEC-PDP-11 family
This specific example is a computer system, etc.
Existing common operations to meet the objectives of
operating system and application software
It's becoming like that. According to IBM nomenclature, a host
storage computer and database computer
The main intercommunication line network between
The same thing is based on DEC nomenclature.
If so, ``unibus'' or ``masbus'' or
It is called by a slightly modified term. Below
Any of the above computer systems
Whether used or other manufacturer's main
Regardless of whether a frame computer is used, this
channel, or bus, to which the database
The owner where tasks and subtasks are dispatched
A logical transfer path, i.e. a logically passive transfer path.
It is a road. The specific example in FIG.
Back-end processor complex combined with 2
It shows merging. The system in this diagram is a task
and subtasks from the host system;
Corresponding part of the huge amount of database storage information
and the appropriate processed message or
is to return a response message, and that
Their operation is based on this back-end processor complex.
Regardless of body composition, it is not very advanced.
host system, except for management by software.
system is now executed in a way that is not required.
It's on. Therefore, it is necessary to update the user's database.
Configured as a multi-processor system
This multiprocessing
In the TUSA system, data can be
Relational data that can be extended to
can be organized as database files,
What's more, this extension
Internal operating system
No need to change systems or existing application software
It is now possible to do this. Independent system
As a stem (stand alone system)
See Figure 20 below for a specific example of the configuration.
I will explain as I go along. As will be understood by those skilled in the art, the relayer
There is one operational function related to file database management.
the entire operational function of the other, at least temporarily.
into multiple processing tasks that can be processed independently
It is an operational function that allows you to The reason
The reason is not remembered in a relational database.
If multiple data entries in the address point
Are they interdependently connected by interfaces?
It is et al. Further, as will be understood by those skilled in the art,
In addition to regional database management, limited
dynamically
The method of subdividing into smaller parts and processing them independently is used.
There are many possible data processing environments.
There is. Therefore, when explaining specific examples of the present invention,
There are particularly strong demands and frequently asked questions.
related to processing issues in database management.
However, as disclosed herein,
New methods and configurations for
It has many uses. Large data management systems require multiple processes.
When using Tsusa (multiple processor)
the potential benefits and inevitable attendant difficulties.
It will have both. Huge number of hundreds of millions
A number of entries (descriptions) are stored in the storage device.
Must be kept easily and quickly accessible.
Must be. On the other hand, relational database
If you format it as a base, you can use a wide range of data.
Simultaneous data entry and information retrieval operations
can be carried out in a specific manner. However, the vast majority of database systems
database integrity (integration)
maintaining the transaction
Processing data quickly is just as important.
ing. Data integrity depends on hardware failure
power outages, and other disasters related to system operation.
If it is not maintained before and after the harm
No. Furthermore, the database system
Bugs in application software code
Clean up any initial user errors.
restore the database to a previous known state in order to
must have the ability to do so. deer
Even if data is accidentally lost or entered
This should not happen and the event should not be new.
Is it related to data or past
Is it related to error correction?
is also related to the proofreading of a part of the database.
related to a particular entry, depending on whether
all parts of the database are changed.
You have to become familiar with it. Therefore, for completeness, it is necessary to rollback the data.
Error detection and correction operations;
operations, as well as the status of individual parts of the system.
In addition to the operation of change detection and its compensation, furthermore,
Some degree of redundancy is also necessary for database systems.
It is essential. To achieve these objectives, the system
The stem can be used in many different specialized modes.
It may be necessary to do so. Additionally, modern systems have complex formats.
Inquiries with arbitrary content that tend to be
(discretionary queries) and the necessary
have the ability to respond in an interactive manner if
You are required to be on the same page. Even if the inquiry
access the system, even if it is complex.
The people trying to access the system are experts in the system.
If there is ever a time when you are required to do something
do not have. It may occur in connection with large-scale production operations.
Examples of arbitrary queries include:
be. A. The manager who manages production
If you only request a list of one item
production volume is at least 10% or more compared to the same month of the previous year.
Exceeding its monthly production of declining parts
Inventory inventory listing all parts in stock, such as
may call for a strike. B. A marketing manager
Inquire whether the account is 90 days past due.
In addition to living in particularly depressed areas,
For customers who have exceeded 120 days in the past.
Regarding this, we may request a uniform 90-day receivables.
unknown. C. An executive in charge of human resources spends two weeks in a given year
Make a list of all employees who have taken sick leave in excess of
In addition to asking for
For more than two years, during that fishing season.
Long-term employee with 10 years or more of sick leave for one week or more
Request a list of all continuous employees
Maybe. In each of the above examples, the user
Do not delete any information stored on your computer until then.
By relating things in ways that have never been done before,
Identify the real problems you face in your business
That is to say. to the field that is causing the problem.
If the user has experience with
If the user has intuition and imagination, the computer
Untrained experts can handle complex inquiries
freely create a database system that can process
It can be used. Modern multiprocessor systems use these
as many as, and often contradictory to each other
Carefully created overrides for requirements
- head software system and maintenance
by using software systems.
However, these software
Toware systems inherently facilitate systems
This is a hindrance to expansion. However,
However, the concept of scalability is a highly sought after concept.
The reason is that the business or business is growing.
and, along with that, existing database management systems.
It is desirable to extend the stem and continue using it.
In this case, the new system and software
I don't like being forced to adopt clothing.
It is from. Multiprocessor Array Referring to FIG. 1, a typical multiprocessor array according to the present invention
One specific example system is a system with many microprocessors.
and their microprocessor
There are two important types of books that are important.
In the specification, interface processor
(IFP) and access module processor
We will call it (AMP). In the figure, there are two
IFP14,16 are shown, each of them
Separate host computers 10 to 12 inputs
Connected to an output device. Many access modes
Juul processors 18-23 are also available on this machine.
In what can be called a multiprocessor array
include. The term "array" here
is a generally neat straight line or matrix
A set of processor units arranged in a row.
a set of processor units, or
refers to multiple processor units;
It is used in the sense of
meaning what came to be called "processusa"
It's not about doing it. The concept of this system is shown in the diagram.
Just 8 microphones to show a simplified example of
Loprosetusa is shown, but much more
IFP and AMP can be used and usually
will be used. IFP14, 16 and AMP18-23 are internal
Direct notes to bus and peripheral controllers
main memory that can be re-accessed.
Intel 8086 16-bit microprocessor
Built-in. A great variety of different manufacturers
microprocessor and microprocessor
Any of the stem products can be used. This “ma”
Microprocessor” cannot be used in this array.
A type of computer or processor that can
This is just one physical example, because this system
The concept of
For Nikon computers or large computers.
In some cases, you can use them to your advantage
It is from. This 16-bit microprocessor
has considerable data processing power and extensive
Variety of available hardware and software
A standard location that can be replaced with the option
A low-cost device with a replaceable configuration.
This is an advantageous example. IFP and AMP are similar active logic
and a control logic jump interface.
microprocessor, memory, and internal bus
These are shown in Figure 1 and Figure 1, respectively.
This will be explained later with reference to FIG. However, this
These two processor types are
The nature of peripherals related to the format and their surroundings.
The control logic for the side devices is different. Current
The different surroundings are easily understood by the trader.
Equipped with a device controller and assigned different functional tasks.
Other processor types given may be incorporated into the present invention.
It is also easy to get lost. Each microprocessor has a fast random access
Process memory 26 (described in connection with FIG. 8)
This fast random access
The bus memory is a buffer buffer for input and output messages.
unique to the rest of the system.
Message management by collaborating in a
Do this. Briefly, this high-speed lander
System access memory 26 has variable length input memory 26.
message (this input is called "reception").
Serves as a circulation buffer and sequentially
To output a message (this output is
Functions as a memory (called "transmission"), and
Used in user mapping mode and other modes
Incorporate the table index part for
messages and outgoing messages in an orderly manner.
Stores control information for handling. The memory 26 is
Furthermore, when selecting multiprocessor mode,
data, status, control, and response metrics.
Unique role when dealing with sage traffic
It is used to fulfill the following. will be explained in detail later
, those memories are further stored in the message.
based on the transaction identity of
Local and global status determination and control functions
are processed and communicated in a highly efficient manner.
It is said to have a unique structure. IFP14, 16 and
The control system provided in each of AMPs 18 to 23
Jitsuk 28 (Related to Fig. 13 will be explained later)
) is responsible for data transfer and override within the module.
Used to perform barhead functions. IFP14 and IFP16 are each interface control circuit.
This interface control
Circuit 30 has an IFP combined with the IFP.
Host computer 10 to 12 channels
or connected to a bus. In contrast, AMP
18 to 23, this interface control circuit
The device corresponding to is the disk controller 32.
Yes, this disk controller 32 is a general
It may have a similar structure, and AMP18-23
, they are individually combined with magnetic disks
interfaces for drive drives 38 to 43, respectively.
It is used for Magnetic disk drives 38-43 store this data.
A secondary storage device, i.e. a large capacity storage device, is used in the database management system.
Provides quantity storage. In this example
For example, those magnetic disk drives are
Winchester Technology
It is made from commercially available products with a proven track record, such as
Therefore, the cost per byte will be
Extremely inexpensive, large capacity, highly reliable storage device
I'm trying to get that. These disk drives 38-43 include
Relational databases with distributed storage
This is briefly shown in Figure 22.
It is shown in converted form. Each processor and
For disk drives combined with
is a subset of the database.
This subset is called the “primary” part.
subsets, and their linear subsets are mutually exclusive.
both a disjoint subset and a complete whole
It constitutes a database. Therefore n pieces
Each storage device will hold 1/n of this database. Each processor also has a
A subset of the data for pick-up is allocated,
Their backup subsets are also disjoint.
These are subsets, each of which constitutes 1/n of this database. As can be seen from Figure 22
, each of the primary files is
A processor different from the one in which the file is housed.
Backup files stored in Setsa
have been reproduced by
Each of the two distributed in the traditional distribution method is completely
A database has been obtained. In this way, one
Next data subset and data part for backup
This is because the sets are arranged with redundancy.
The integrity of the database
The reason for this is that protection is provided to prevent a single failure from occurring.
If so, multiple data over several large blocks
or multiple relationships in multiple groups.
It is unlikely that it would have any real impact.
It is. The distribution of the database is also shown in Figure 22.
The various file hashing operations are
It is related to the work of Hatsushi Matsupi.
embedding data into a message.
are related. contained in each processor.
files are shown as groups of binary sequences.
A simple hash bucket
bucket).
Therefore, the relationships specified by those buckets are
Based on the relation table,
relationships in a database system
(relationship) and tuple (tuple) should be placed.
The location can be determined. Hashing algorithm
This relational database can be
inside the base system, from the key to the bucket.
It has become necessary to allocate
Therefore, this database system will be expanded and revised.
Changes can be made easily. The storage capacity you choose depends on your device.
database management needs, transaction
amount, and the memory associated with that storage device.
Determined according to the processing power of the chloroprocessor
It is. Combine multiple disk drives into one
Connect to AMP or connect to a single disk file
It is also possible to connect a device to multiple AMPs
However, such modifications are usually limited to special applications.
It will be done. Database expansion is typically
One example is a multiprocessor array.
number of processors (and combinations of processors)
Expand the number of installed disk drives
It is done by Active logic network provides an orderly flow of messages and packets
The purpose of
The purpose is to create a new active logic network.
A unique system architecture centered on the construct 50.
Adopting architecture and message structure
This is accomplished by This active logic network
The network structure 50 includes a plurality of microprocessors.
For multiple outputs of a server, it is possible to
Multiple
bidirectional active logic nodes
active logic node) 54
Ru. These nodes 54 have three ports.
This bidirectional circuit consists of two-way circuits.
A road is a tree network.
forming a network with a branch-like structure
and in that case, the base of that tree structure
The microprocessors 14, 16 and
and 18-23. As will be understood by those skilled in the art, a node is a
If the number of Tsuk sources exceeds 2, e.g. 4 or
8, and in this case, at the same time
Also, there is the problem of having a large number of source inputs.
Convert to a problem of adding more combinatorial logic
You can do it. For ease of reference in the diagram, all nodes
Among (N), those belonging to the first layer are
is represented by the prefix “I”, and the second layer
Those that belong to it prefix it with ""
The same applies hereafter. belong to the same hierarchy
The individual nodes in the subscript ' ₁ , ₂ ...”
Therefore, for example, in the fourth node of the first hierarchy
If so, “IN” _Four ” can be expressed as of the node
On the up tree side (i.e. upstream side) there is a “C port”.
It is equipped with one port named
and belongs to a higher layer adjacent to this C port.
of the two down tree ports of the node
are connected to one side of the
- Ports are "A port" and "B port" respectively.
It is named. These multiple hierarchies are
It converges to the part node, that is, the vertex node 54a.
This vertex node 54a is directed upstream.
Flow of Message (Up Tree Message)
Reverse the direction of the tree and move it downstream (down the tree)
as a means of convergence and turning towards
It is functioning. Two tree networks 50
a, 50b are used, and those two sets of nets
Nodes and interconnections in a network
The parts are arranged parallel to each other, and
This provides the desired redundancy for large-scale systems.
Ru. Nodes 54 and their networks
The links are identical to each other, so their
It is sufficient to explain only one of the two
be. To make the explanation easier to understand, please understand first.
What I would like you to keep in mind is the format of the serial signal string.
A large number of message packets are
Active logic can be realized by connecting multiple microprocessors.
simultaneously sent to the network 50, or
It is said that it is possible to send out at the same time.
That's true. The plurality of active logic nodes 54 are
Each of them operates on a binary basis and the two each operate on a binary basis.
The priority between colliding message packets in a colliding relationship is
A determination of priority is made, and this determination of priority is based on the
using the data content of the message packet itself.
It is done. Furthermore, within one network
All nodes 54 of
56, and this clock
The base 56 arranges the sequence of message packets at the vertex nodes.
You can proceed synchronously towards Do 54a.
combined with those nodes 54 in such a manner.
ing. In this way, in a serial signal train
The incremental segment of each successive byte etc. of
The progress of this byte is advanced to the next level.
the byte corresponding to that byte in the message of
follows another route within this network 50.
It will be done at the same time as the same progress. Give priority between competing signal trains
The sort for is moved in the up tree direction.
This is done for message packets that are
Eventually, downstream from the vertex node 54a
a single message string to be redirected towards
is selected. The system is configured as described above.
Therefore, it is difficult to determine the final priority.
At one particular point within the sage packet
There is no longer a need to
two mutually running nodes 54
Binary-based determination between colliding packets
of messages without the need for anything outside.
Transfers can now be made continuously.
Ru. As a result, this system
to select messages and transfer data.
However, the bus support is
take control of the sending or receiving processor.
to identify processors or handles between processors.
For the purpose of performing doshaking operations,
There is no delay in message transmission. Furthermore, there are a few things that I would like you to be aware of.
A few processors produce exactly the same bucket at the same time.
If the transmission was successful,
Same as if all of those sending processors were successful.
This means that the same thing will happen. This property is time
Large multi-pro
Extremely useful for effective control of the Setusa complex
It is. Node 54 also operates in a bidirectional manner so that
Unimpeded downstream message
This makes it possible to distribute the packets. given no
In the board 54, the
downstream message received on port C
is provided on the down-tree side of this node.
distributed to both port A and port B, and
Belongs to an adjacent lower hierarchy connected to this node.
is forwarded to both of the two nodes. common·
The message packet is processed under the control of clock circuit 56.
The threads are synchronously advanced down the tree,
and blow to all microprocessors at the same time.
It is broadcasted, and
Thus, one or more processors
be able to perform a processing task, or
Be able to accept responses. The network 50 has a data transfer rate of
Compared to microprocessor data transfer speeds
faster, typically more than twice as fast
It's fast. In this example, the network
50 is a 120 nanosecond byte clock interval
The data transfer rate is micro
It is five times faster than a processor. Each node 54
has each of its three ports connected to that node.
Ports of nodes belonging to adjacent hierarchies that are
or connected to a microprocessor.
This connection is connected to one set of data lines (in this example
(10 lines in this example) and control lines (10 lines in this example)
(2 control lines) and 2 control lines.
The input signals are the clock signal and collision signal, respectively.
emergency signal). data line
and the clock line are wired in pairs.
and up-tree direction and down-tree direction
and are considered to be separate lines. Collision
Lines only propagate down the tree
It is something. The above connection structure is full-duplex data.
It forms a route, and each line has its own
No delay required to "reverse" drive direction
It's becoming like that. Next, to explain about Figure 3, the 10 data
The data line is represented by bits 0-7.
contains bit bytes, and they are divided into 10 bit bytes.
It occupies eight of the data lines. Table with C
The other line that is connected is the control line.
This line handles message packets in a specific way.
control symbols used to specify different parts of the
transport the kens. The 10th bit is in this example.
is used for odd parity. Current
As the trader understands, this system
may increase or decrease the number of bits in the data path of
It works easily even if you change the number of bits that way.
can be set. A byte sequence is a series of
Arranged to form multiple fields and base
Basically, the command field, key field
field, destination selection field, and data field.
It is divided into fields. will be explained in more detail later
As in the message, there is only one message.
It may also use a detectable
Exit with "Do of Message" code
It's becoming like that. “A” intervening between messages.
idle field (play field)
"Do)" is a cut on the C line and lies 0 to 7.
It is represented by a series of ``1'' without any
If you are in a state where you cannot even receive message packets.
This is always forwarded. parity la
In addition, changes to the status of individual processors are
It is also used to convey information in a unique way. The “idle state” is a
A state that exists between two messages.
Therefore, it is not part of the message packet.
Message packets typically contain two bytes, including a tag.
Starts with the command word for the
message is a data message.
It is said to be in the form of a number (TN).
and the message is a response message.
If so, it is in the form of an originating processor ID (OPID).
There is. The transaction number is
It has various levels of significance within
and form the basis for many types of functional communication and control.
It functions as a device. The packet is
This command word is followed by a variable length key.
Field and fixed length destination selection word
(destination selection word: DSW)
can include either or both, and these are variable
The first part of a long data field
It is. The key field is
Messages do not interact with each other in areas other than the field.
If the messages are exactly the same,
provide criteria for sorting between
It serves this purpose. DSW has many
It provides the basis for the special features of
Also, along with TN, it deserves special attention.
Ru. This system is compatible with word synchronized
Now it works using interface.
and all protocols attempting to send packets.
The setter sets the first byte of the command word
It now sends out to network 50 at the same time.
It's on. The network consists of the following
At each node, using the data contents of the field.
Sorting is done on a binary basis, and this sort
Teing is given when priority is given to the lowest number.
It is done in this way. consecutive data bits
Considering bit C to be the largest amount,
If we consider bit 0 to be the smallest quantity, then
The sorting priority is as follows. 1 the first one sent to the network 50; 2 the first command code (command word) sent to the network 50;
3. The key field has the smallest value. 4. The key field has the shortest value. 5. The data field (including the destination selection word).
6. The data field is the shortest. For the purpose of providing an overview here,
It should be noted in particular that node 54
If priority is determined in
Yon display (= collision display, hereinafter referred to as Acol or Bcol)
) was defeated in this priority determination.
This means that the sender's transmission is returned to the receiver's route.
That is. This collision display allows you to send
The microprocessor running the network
50 is used for higher priority transmissions.
has stopped its own transmission, and
and then try sending again later.
can be recognized. Simplified examples are shown in the various diagrams in Figure 2.
has been done. In this specific example, the network 50
Tree using 4 separate microprocessors
Fast random access memo arranged in structure
It is designed to operate in cooperation with the
These four microprocessors will be explained in more detail.
Then, IFP14 and three AMP18, 19 and
and 20. Total of 10 sub-figures 2A, 2B,...2
Each of J is continuous from t=0 to t=9
corresponds to one of the 10 time samples
and this net at each of those times.
from each microprocessor in the network.
Different simplifications (4 sentences)
distribution of serial messages (consisting of letters)
and port numbers at their various times.
indicates the status of communication between the host and the microprocessor.
are doing. A drawing that simply says Figure 2
indicates the state of the system before the start of signal transmission.
ing. In each of the above figures, the null state
(null state: zero state) i.e. in idle state
In order for this to happen, the transmission represented by “□” must take place.
It is a must. the minimum value
There is an agreement that the data content taken has priority rights.
Therefore, it is sent from AMP19 in Figure 2A.
The message packet “EDDV” was the first
Message packages transmitted through this system
Becomes a butt. Each message in the diagram will be explained later.
As explained in further detail, the microprocessor
High-speed random access memory (HS)
(sometimes called RAM)
ing. HSRAM26 is schematically shown in Figure 2.
It has the input area and output area shown.
Therefore, at time t=0, the packet is
The output area is FIFO (first in, first out).
are arranged directly side by side, thereby allowing the transfer
In this case, the information written to HSRAM26 in the figure is
cursor arrow as directed.
It is now possible to get out. at the time
, all transmissions in network 50
The transmission indicates a null state, that is, an idle state “□”.
There is. In contrast, t=1 shown in FIG. 2B
At the time of each message packet,
The first bytes are sent to network 50 at the same time as each other.
sent out, at which time all nodes 54 are still
The idle status display is returned, and the first layer
All transmission states above are also idle.
ing. during the first clock interval
The first byte of each message is the lowest node.
dein ₁ and IN ₂ is set inside of , and at t=2
(Figure 2C) the conflict is resolved, and
Both upstream and downstream transmissions continue.
will be executed. Node IN ₁ is both input points.
“E” is received at the
forwarding towards the next layer in the direction, and downstream
In the direction, the undetermined
Displaying the status. However, this same floor
Node IN belonging to layer ₂ Is it processor 19?
between “E” from the processor 20 and “P” from the processor 20
In the event of a collision, priority will be determined in the direction of "E".
It is determined that the port has priority, and
One that connects port A to port C on the up tree side.
On the other hand, return the Bcol signal to the microprocessor 20.
ing. Bcol signal goes to microprocessor 20
When returned, IN ₂ The node is effectively
The port is now locked to the C output port.
Thereby, the command from the microprocessor 19 is
Real signal sequence is transmitted to vertex node N1
It becomes like this. IN ₁ In a node, the first two characters are
are also “ED”, so as shown in Figure 2C.
Therefore, this node makes a decision at time t=2.
It has become impossible to bring it down. Furthermore, three
Sent from microprocessors 14, 15 and 19
The common first letter "E" that was
It reaches the N1 vertex node at the time shown in Figure D), and
This letter "E" is also used for all those messages.
The second letter “D” common to ji is at this apex.
When the data is transferred to the card N1, the direction of the transfer is
is reversed and directed downstream. at this point
is node N ₁ is still in a state where it is not possible to make a decision.
However, at this time, a series of micro
respective third processors from processors 14, 18 and 19;
The th characters "F", "E" and "D" are in this node
N ₁ is being sent to. microprocessor
20 receives the Bcol signal.
Setsa 20 loses the race for priority.
This means that the process has been
Tusa 20 becomes idle if it receives the Bcol signal.
Sends out the display “□”, and from then on this id
Only the ``□'' symbol is sent. Each output buffer
Each cursor arrow written in
The chloroprocessor 20 has been returned to its initial state.
However, other microprocessors are
This shows that the characters are being sent continuously. obey
Important events at time t=4 (Fig. 2E)
The thing is, node N <sub>1</sub> A determination regarding the port is made.
and that the first letter (“E”) is
Directs to the first layer node layer through all lines.
The signal is then transmitted in reverse. t=5 (2nd F
The second collision is displayed at the time shown in the figure), and this time
, node N <sub>1</sub> B port wins the competition,
Acol is generated. During the next few clock times, the serial
The downstream broadcast of the signal train continues.
At time t=6 (Fig. 2G), the
The first character of the tsage is all HSRAM26
It is set in the input area. even here
Another thing to keep in mind is that the node
N <sub>1</sub> The priority determination made earlier in
It means that it is invalidated at that point in time.
The reason is that the third number sent from the processor 18
The eye letter (“E”) is from microprocessor 19.
Loses the competition with the third character sent (“D”)
When the node N1 of the higher hierarchy
This is because Acol is displayed. Figure 2H
As indicated by the cursor arrow inside,
The microprocessors 14, 18 and 20 are
It has been returned to its initial state, and the winning My
The processor 19 transmits all its transmissions at t=4.
has already been completed at the time of. Figure 2H, Figure 2I
As can be seen from Figure 2 and Figure 2J, all input bars
Priority messages “EDDV” are sent one after another into Tsuhua
will be loaded. t=8 (Figure 2I)
Well, this message has already flowed out from the first layer.
and the vertex node N <sub>1</sub> is t=7
has already been reset in
However, it is the last step toward the microprocessor.
When downstream characters are transferred, they are already idle.
This is because only the two signals are competing with each other. t
At time =9 (Figure 2J), belonging to the first layer
Node N <sub>1</sub> and N <sub>2</sub> has been reset.
and the defeated microprocessor 14,
18 and 20 are all connected again.
The first sentence of the message when indicating dollars
on the network by sending
There will be another competition for priority
Become. In fact, as explained later, the winning team
The response signal is transmitted to the microprocessor.
However, this makes the invention as general as possible.
It is not necessary for those who do. In this way, the message
After being broadcast to Rosetsusa, this message
Tsage will update those microprofessions as needed.
by any or all of them
used by. how many microprocessors
The mode of operation and execution
They differ depending on the function being used.
There are many variations in their operating modes and functions.
exists. (Global Intercommunication and Control) One of a group of mutually competing messages
network gives priority to messages
The specific example above of how to
This example concerns the transfer of data messages.
Ru. However, complex multiprocessor systems
The stem has the good efficiency and versatility that is currently required.
In order to provide long-term versatility, many other
It is necessary to utilize many types of communications and commands.
Ru. The main functions that must be provided
In addition to primary data transfer,
It can be called a multiprocessor mode in taste.
response to a message, a stator
It includes a status display as well as control signals. below
The chapter explains how the various modes and messages
sorting and communication for priority assignment
sorting, communication, and
A global perspective on how to collaborate with networks.
from the perspective of a multiprocessor system
The purpose of this paper is to present an overview as described above. More details
For detailed understanding, please refer to Figures 8 and 13,
Please refer to the explanations below for those figures.
stomach. Broadcast mode
, the message is one or more specific messages.
All receiving processors are
simultaneously delivered to the processor. This mode is
To take a typical example, it is possible to
answers, status inquiries, commands, and control functions
Regarding. If the receiving processor needs to be specified
in the message packet itself.
The forwarding destination selection information contained in
Accept locally (=in each processor)
provide criteria for deciding whether to
It is becoming more and more like this. For example, the receiving process
Interior interface of the Tusa module
Jitsuku is the matsu that is stored in high-speed RAM26.
According to the packet information, the data of that packet is
Specific devices that incorporate interface logic
Is it included in the scope of involvement of processors?
Identify whether or not. Map bits in high speed RAM
Various selection methods can be created by setting
Judgment criteria can be easily set and their
Selection methods include, e.g.
selection, stored data (by “hashing”)
select part of a database, perform logical processes
selection of class type (“class”), etc. Bu
Local access control (= individual program access control)
access control (performed in the access processor)
It is used in database management systems.
It is particularly beneficial to use small over
Widely available, requiring only head software
Any distributed relational database
parts and multiple globally known logics.
Distributed of any of the local processes
Because the local copy can be accessed
It is. Therefore, this system
Specify one destination processor as the destination.
You can also select and belong to one class.
In addition, high-level database queries
is often used between separate parts of the database.
Cross-reference and consistency for a given task
reference (identification information) is required.
Transaction number embedded in message
Although TN has various characteristics,
Among other things, such global transactions
Yong's identity (identification information) and Lehua
It provides a lot of information. many tasks,
Local processes that run asynchronously to each other
local processor module
can be processed concurrently by
Each task or service is
Butask is made to have a suitable TN.
TN, DSW (destination selection word) and command
By using various combinations, substantially
Endless flexibility is becoming possible. So
The allocation and processing of
Extensive sorting/marking for many tasks at once
applying sort/merge poeration
I am becoming able to do this. Regarding TN,
It is possible to allocate and relinquish it.
and the start of the merge operation.
and stop are possible. some kind of message
For example, continuous messages, etc.
have priority over the transmission of messages.
It can be done. TN and that TN
Local processes that update the status of
By using the service, only one query
global resource status for a given TN
It has become possible to determine the minutes
Distributed updates can also be achieved with a single communication
It's summery. The system of the present invention accomplishes all of the above.
Features may extend or override the software.
be carried out without significantly increasing the burden on the
The purpose is to ensure that As a result, if the present invention is used, the conventional technology
The number of microprocessors normally seen in surgery
Equipped with far more processors than
How to adapt a multiprocessor system to problem tasks
and can be operated very effectively.
Ru. Nowadays, microprocessors are becoming cheaper.
High performance in the problem domain due to
system, even if it is simply “raw” power
The system is not only high performance (power).
can be realized. All message types and various subtypes
A consistent priority protocol that encompasses
However, the various meth- ods supplied to the network
It is designed to cover all aspects of the page. Response
response messages, status messages, and
Control messages are primary data messages.
These messages are in a different format than the
Similarly, network conflict/merge behavior
(contention/merge operation).
and thereby the right of priority while being transferred.
receive a grant. Response message in this system
This is either an affirmative response (ACK) or a negative response (NAK).
or the processor processes the message.
have the resources to meaningfully process
A message indicating that the processor is
(not applicable processor) - NAP).
A NAK response indicates a lock condition, an error condition, etc.
or overrun condition.
any of several different types shown
It's okay if it's hot. There is only one source processor.
There may be multiple sources, but the source process
After finishing sending the message,
response message requires a specific response.
Higher priority than primary data message
A ranking is given. This system also sends a SACK message (status
Status response message: status
acknowledgment message) is used.
The SACK message of
A local professional regarding Zaxion
Setusa's readiness state (what kind of actions are possible)
Displays readiness state
It is something to do. The contents of this SACK response are local
(=in each processor, i.e. local
(in the file processor) and
remain accessible from the network.
Ru. Such a SACK response is
a given task by being combined with an action.
i.e. by a single query on a transaction.
global status reporting.
Ru. Status responses follow priority protocol
Therefore, regarding one transaction number,
The response with the smallest data content among the responses
priority, thereby ensuring that at least
readiness state as a global system state.
1, which is confirmed and will not be interrupted.
It is carried out by the movement of times. Furthermore, something like this
The SACK indication is a type of primary message.
Sometimes used together, thereby
For example, system initialization, lockout operation, etc.
Various protocols are configured. Priority settings for different message types
First of all, let's talk about command codes.
is defined, and this commad code is the first
At the beginning of each message and response as shown in Figure 1.
The first 6 bits of the command word
I am using it. This determines the type of message.
and subtypes can be well distinguished.
However, there are more levels of differentiation.
It is also possible to attach it. 11th
As can be seen from the figure, in this example
In this case, the SACK response has seven different status levels.
to distinguish between bells (and also to determine priority).
It also provides standards for Reply mail
In the case of tsage, after the above 6 bits, 10
A tag in the format of bit OPID follows (Figure 3).
reference). Both TN and OPID require further sorting.
can serve as a criterion for
The reason is that these TN and OPID are tags
Does the area have different data contents?
It is et al. Each primary message
After the data is transmitted, all processors install
Even if the Turf Eighth Club is NAP
Either way, a response message is generated. that
Their response messages are also sent to each other over the network.
Contest and thereby win a single or common victory
The response message sent to the processor is then broadcast to all processors.
You will be crushed. The defeated message packet is
Simultaneous transmission will be attempted again later, but this
The second simultaneous transmission of the
network, thereby making the network virtually continuous.
It's like being used. multiple processes
If Tsusa sends out ACK responses, those
ACK responses are sorted based on OPID
It turns out. As a result of using the present invention, the task
starting, stopping, controlling, and querying tasks.
by a large number of physical processors,
Moreover, it can be executed with little overhead.
It becomes possible. This means that many processors
raw power to handle problem conditions.
It is possible to use it effectively for
Then, out of this low power, the code of the system
Dedicated to coordination and control.
This is because the amount lost is extremely small.
Coordination and control overhead is
The effectiveness of any distributed processing system
This constitutes a fundamental constraint on the rate. Aiming for global control (i.e. network control)
various types of control communications when targeted
is used. Therefore, "Stop Merge", "Status"
Messages ``Task Request'' and ``Start Merge''
or a message sequence for assigning a certain task.
The message for abandoning the task in
It is said to be in the same format as the data message.
, and therefore those messages are also included here.
We will call this the primary message. So
These control messages also contain TN.
and appropriate place in the priority protocol.
It is located at More on this later
10 and 11 will be explained below.
do. It is called a “global semaphore buffer system.”
The first use of the term was the height shown in Figure 1.
Fast random access memory 26 and control logic
The switch 28 selects the multiprocessor mode and
Both status display and two-way communication of control instructions
It is said that it plays an important role in
Because there is a fact. This global semaphore
The Tsuhua system provides duality of access
This access duality means that the
Operating network structure 50 and slower speeds
Both the microprocessor and the memo
Messages, responses, controls, or messages within the
Display status without delay and on the network.
Requires direct communication between the microprocessor and the microprocessor
so that you can refer to it without having to
This means that To achieve this
Then, the control logic 28 inserts the memory 26 into the
interleaved woed cycle
Time multiplexing
Connect to network 50 and microprocessor
As a result, the memory 26 is
Separate ports that can be accessed in common
It has become the same thing as the
Ru. global resources, i.e. networks 50 and multiple
A microprocessor is a transaction processor.
of the transaction in memory 26.
To the section allocated for storing status
As an address locator that locates
can be used. local level (=individual
processor level), all kinds of
A given transaction that encompasses the available state of
The status of subtasks related to
Updated internally in memory 26 under processor control
and the control logic 28 controls the buffer
This is done by locking into the system.
Use one of seven different ready states.
By storing entries in memory 26 different
So that it can be conveniently removed from the ivy-specific part.
It's getting old. Receive inquiries from the network
If so, processor status communication is not performed.
(i.e. "semapho" is read), it
The determination of priority for
In that case, the readiness with the lowest degree of completion
The state is starting to get priority. The above structure
All processes for one query can be
Get quick hardware response from Tsusa
It's becoming like that. Therefore for a given task
All of the distributed subtasks have completed execution.
without delay and in software.
You can know this without using any clothing. Change
In this system, the processor and
Each module is a transaction number.
It is now possible to allocate a server, and this
Transaction number assignments are available for use.
Message the transaction number in the current state.
or each global semaphore
allocated for use within the system
It is an action. The identity of the transaction
It is recommended to use the integrated display and status display.
A preferred embodiment of the process includes a plurality of processes.
Each of the
be required to send out the pages in order.
There is a complex merge behavior. If the conventional technology
For systems related to
receives its own task, completes its processing, and
The result of that processing after the final merge operation is
transfer to some kind of "master" processor that executes
We will have to take the approach of obey
The master processor determines the efficiency of the system.
This poses a serious problem. Global readiness is the process of action.
that everything in the sa is in a state of readiness.
Once confirmed, each processor is provided with
The memory with the highest priority in memory 26
messages are sent to the network at the same time as each other,
And for those messages,
There is no priority determination while the merge is being performed.
It will be done. About messages in several groups
One retransmission attempt after another, resulting in multiple
message related to the transaction number.
Arrange them in order from highest to lowest priority,
The lowest priority comes at the end.
A serial message sequence is generated. Special
Following another command message, this system
The system allows you to stop the merge operation mid-way and
It is said that it is possible to restart from the inside, and that
Therefore, if multiple machines are in the middle of execution at the same time,
If the network operation is sharing this network 50,
It has become possible for there to be a situation in which
This allows for extremely effective use of the system's resources.
It is now possible to use Therefore, at any time, this network
An operating processor connected to the workpiece 50
all related to various transaction numbers.
actions related to multiple messages that are related to each other.
It is now possible to run synchronously. 1
same transaction by two status queries
Current number, i.e. “current” transaction
If a number reference is made, all processes
of the available status levels.
, and respond in synchronization with each other. example
"START MERGE"
A message is a transaction name.
Testing global semaphore specified by member
(=survey), and if the results of this test are
If the current global state is "ready", then
(i.e. “SEND READY” or
indicates “RECEIVE READY”.
If the current transaction is
present transaction number:
PTN) value in this "Start Merge" message.
is set equal to the value of the TN transmitted included.
Ru. (If the global state obtained as a result of the test is
If it was not in the "ready" state, the value of PTN would be
“TNO (This is Transaction Number (TN)
is "0")"
(will be returned). Furthermore, "STOP MERGE"
Sage also currently has transaction numbers.
Reset to "0". In this way "TNO"
is a process from one processor to another.
Message to Tsusa (Point to Point)
``day phono'' used for
used as the transaction number for the root value
has been done. In other words, this "TNO"
``non-merge'' mode
The behavior of the code is specified. This global intercommunication system
Regarding the configuration, 3rd A, 3rd B, 3rd C, and 3rd
The one shown in Figure 11 can also be used as a high-speed lander.
For details on the configuration of the system access memory 26, see Section 8.
The ones shown in Figures and Figure 10 are adopted.
Ru. A more detailed explanation will be given later in the fifth, seventh, ninth,
This will be explained in conjunction with FIG. As can be seen from Figures 3A to 3C and Figure 11.
, the command code used in response is 00 or
up to 0F (hexadecimal), and the primary
The command codes used for Tsage are 10 (16
decimal numbers) to larger values. Therefore, respond
The answer takes precedence over the primary message and
In the sorting order shown in Figure 11, the smallest value comes first.
It's like this. 1 inside the high-speed RAM memory 26'' (Fig. 8)
Dedicated storage area (“transaction” in the figure)
The 12th area is
The word format shown in the figure (the 7 types of formats mentioned above)
status, TN assigned status, and TN unassigned status
state). This message
Among the several other dedicated parts of Mori 26″ are:
Circular buffer for input (received messages)
and storage space for output messages.
ing. Another separate separation of this memory 26″
area is used as message completion vector area.
This area contains the output message that has been sent.
It also allows you to place a pointer on a page.
, and this allows the storage of the output message
Space can now be used more effectively. As understood from the above, the memory 26 and control
As for logic 28, those cue-in
queuing function and data buffering
Logging functions are certainly important, but they also
In this case, global transactions are processed by individual processors.
Multiple joint operations where processing is performed in a distributed manner
The work has become of unique importance. (active logic node) Two networks arranged with redundancy
In any of the
Each logic node 54 has the same configuration as the other.
However, with the exception of
Only the direction reversal node 54 at the top of the
It does not have a side port, but instead has a downstream port.
Provides a simple signal direction reversal path for reversing direction.
ing. As shown in FIG.
broadly divided into two groups based on function.
can do. their functional groups
One side is a message and a collision signal
(collision number), and the other
is related to the generation and retransmission of the common clock signal.
It is something that For clock signals, different
There is a gap between each clock signal at the node
So that you do not exist, that is, with zero skew.
Synchronization is achieved so that The above two functions
Groups are not independent of each other;
The reason is that the zero skew clock circuit transmits the signal.
This is because it forms an important part of the system.
Ru. Word clock (two serial bytes)
) and bite clock are used.
It will be done. In particular, I would like to mention that this active logic
Setting or resetting the state of the network node 54
Also when setting different operating modes
Also, this active logic node 54 can be accessed from the outside.
There is no need for, and indeed no such control
is never done. Furthermore, each node
54 have the same structure, recent ICs
technology to mass produce those nodes.
is possible, thereby improving reliability.
It is possible to realize considerable cost reduction while
can. Each “port” of A, B and C mentioned earlier
each of which has 10 input data lines and 10
output data lines. For example, A
At a port, the input line is denoted by A and the output
The line is represented by A0. for each port
the upstream clock line and downstream clock line.
Along with the Tsuku line, there is one “Collision” line.
lines (i.e. “collision” lines) are used (e.g.
For example, Acol is used for A port). Apo
The port and B port data lines are
It is connected to multiplexer 60, and this multiplexer
The lexer 60 recognizes two words that conflict with each other.
the preferred word or (their conflict)
the common word (if the words are the same)
is the data signal C0 at the upstream port (C port).
to the up register 62 connected to
Switch and connect. At the same time, more
Sent from a node in a higher hierarchy and received at the C port.
The downstream data taken is transferred to the down register 6.
Shifted in to 4 and shifted from there.
both A and B ports.
occurs as output. Serial upstream signal sequence consisting of bytes
One of them can be blocked, but
However, it also affects the upstream or downstream direction.
There is no extra delay towards
Multiple words are connected to the word clock and bytes.
under the control of the clock.
UP register 62 and down register
64. mutually supplied to A port and B port at the same time
Bytes that conflict with each other are stored in the first and second paris.
It is sent to the tay detectors 66 and 67 as well as the comparator 7.
0, and this comparator 70 receives 8 data
Based on bits and one control bit, the minimum
Priority is given in such a way that the data content of the value gets priority.
Determine rights. Professionals for this priority determination
In the system, the ``idle'' signal, i.e.
The signal is interrupted when sage is not present.
It is said to be a series of "1"s that continue without interruption. Parite
Errors are typical, such as the presence of excessive noise.
causes or other signal transmission or circuit operation.
may be caused by any factor that affects
It is. However, the system of this example
parity error display is another important
It is also used for various purposes. That is, a certain ma
When the microprocessor enters the inoperable state,
Each transition is marked and this map
-King has all exits including parity line.
The force line becomes high level (i.e. its value is “1”)
(to become), and therefore by it.
so that an odd parity error condition occurs.
It's getting old. This parity error display is 1
If one error occurs, you can
This marker is transmitted as a
Therefore, the system is
Identify what the change is and what kind of change it is.
start a procedure to determine whether
It is becoming possible to do this. A pair of parity detectors 66, 67 and a comparator 70
supplies a signal to the control circuit 72, and this
Control circuit 72 provides priority message switching.
A circuit 74 is included, and a priority determination is made.
Then, in response to the output of the comparator 70, the multiplexer
Load the sensor 60 into one of two states.
It is configured to
to generate and propagate collision signals to
It is configured. Transition parity error propagation circuit
The reason for the name 76 is that this circuit
Parity where all lines are set to 1 at the same time
force an error condition into the network.
This is because it is something that comes out. The reset circuit 78 is
This is to restore the node to its initial state.
end of message
message:EOM) detector 80. The functions explained above and the machines explained later
In order for the functions to be carried out, each active
The microprocessor at the logic node
to use chips to perform those functions.
However, as shown in Figure 5,
according to the state diagram and the logical formulas listed below.
update by ensuring that the functions of
can be easily executed. Figure 5
In the state diagram, state S0 represents the idle state.
Messages that are in conflict with each other
Connect one port to the other port to be identical
It also represents a state in which no decision has been made to give priority to
are doing. S1 state and S2 state are A port, respectively.
B port is prioritized and B port is prioritized.
It is in a state of being Therefore, the data content of B is
larger than the data content of A and parity to A
B. If no error exists, or B.
parity errors exist (these
It is said that there is no parity error in A of
condition and that there is a parity error in B.
The condition that BIPE and
is expressed by the state of the flip-flop.
port A is given priority. A
The opposite logical state (logical condition) with respect to and B
) is the state in which this device should transition to S2 state.
It exists as a (condition). higher level
A collision occurs in a hierarchy from a node in that hierarchy.
If an indication to the effect that
It is inserted into the downstream direction signal and is used as COLN.
It will be sent back. This device is
state, S1 state, and S2 state.
Even if the state is met, the system will transition to the S3 state,
This collision signal is then transmitted downstream to Acol.
and transfer as Bcol. S1 state or S2
state, this node has already made a decision.
Therefore, the collision signal is lowered using the same method.
In the flow direction, to (two) nodes in the lower hierarchy
At this time, the priority message
The switching circuit 74 connects the A port or
Or it is locked to the B port. Reset circuit 78 includes an EOM detector 80.
Using this detector 80, the S3 of the node
Then, a reset to S0 (FIG. 5) is performed. No.
In reset mode 1, as shown in Figure 6,
Terminate the data file in the immediate message.
End of Message (EOM)
It uses fields. one glue
Multiple flip-flops and multiple games
The following logical state is created using URINC・URC・URCDLY Here, URC is the control in the up register.
represents bits, and URINC is this up register.
The value of the control bit in the input signal input to the
and URCDLY is the up register delay.
C value in the extended flip-flop (= control bit
value). As shown in FIG. 6, in the control bit string,
A bit pair (bit pair) is a set of two consecutive bits.
tuto pair) makes certain fields explicit.
from one field to the next with
The transition is clearly indicated. give an example
and a system that is followed by only "1", which is used when idle.
From the control bit state, bit sequence of “0,1”
The transition to the bit pair is the opening of the field.
It clearly indicates the beginning. This “0,1” series
sequence identifies the start of the data field.
It is used for Subsequent “1,0” control
A string of bits is an internal field.
Ishi is displaying subfields and also
The address of message (EOM) is “0,0”.
Identified by a pair of control bits. "1,0"
A string of bit pairs followed by a “0,0” bit
The state in which the two pairs come is a state like no other, and it is easy to
can be identified. URINC signal, URC signal
and URCDLY signals are ANDed together (logical
product), and each of these signals is
There is a delay of one clock at a time. So
The waveform of the signal obtained as a result of ANDing these
is at a high level until message packets start.
At this starting point, the level changes to a constant level,
And this data (=message packet)
The waveform remains at a low level for the duration of the waveform.
This waveform shows the byte clock after the EOM occurs.
Return to high level after 2 locks have passed.
Ru. This waveform URINC, URC, URCDLY is correct.
EOM is detected by a transition that changes to . No.
As noted in Figure 5, this positive transition
The return operation from S1 or S2 to S0 is triggered.
It will be done. When a node in a higher hierarchy is reset,
This results in a state, which is a collision
Indicates that the condition has disappeared. This logical state is
Starts the return operation from S3 to the ground state S0
let What I would like you to pay attention to is this
In the N state, the end of the message is
``Run through'' the 50 floors of the arcade one after another.
As it propagates downward to those layers,
That's what I mean. As described above, each node
The code is self-responsive regardless of the length of the message.
It is now possible to set it. Please be more careful
What we want to do is determine the initial state of the network.
Regardless, if an idle signal is provided, all
This means that all nodes are reset to S0 state.
That is. Collision signals are generated by multiple processor modules.
It will be returned to the original level. Those modules are here.
Stores region state information and idle system
This ID returns to the operation of sending the
Transmission of Le Sequence Wins Competition
This is done while the processor continues transmitting.
Ru. The processor converts COLN to
A new transmission can be started as soon as a transition is detected.
It is made possible. In addition to this,
Rosetsusa uses N as the number of layers in the network.
over 2N byte clock times when
If the idle signal continues to be received, start a new transmission.
and it is possible to start
This situation is also the same as the former situation.
If the previous transmission is within this network,
Because it shows that there is nothing left.
be. Those who wish to enable these new transmissions
According to the latter of the equations, the network
Even the traffic of the participating processors is small.
message synchronization status with the network.
You can enter this program for the first time.
The processor communicates with other processors on this network.
another processor when initiating intercommunication between
No need to have polling from. The parity error state is shown in the state diagram in Figure 5.
is set according to the following logical formula.
It is something that PESIG＝AIPE・＋BIPE・
BIPEDLY If the logic state of this PESING is true, the
The input signal URIN to the input register is (URIN
0...URIN7,C,P=1...1,1,1)
Ru. In order to satisfy the above formula, the transition parity is
The A error propagation circuit 76 is for AIPE, that is, the A input
Flip-flop for power parity error,
Includes delayed flip-flop (AIPEDLY)
I'm here. The latter flip prop is AIPE's
According to the setting state, byte clock 1
The state is set with a delay of one minute. Therefore, regarding A input
In other words, the flip prop for AIPE is
When the state is set due to a tie error.
, the PESIG value remains high for one byte clock.
Therefore, this PESIG signal
is the first indication of a parity error.
It is propagated only once. multiple days
data bits, control bits, and parity bits
This is the same when all of the values are “1”.
A state arises, which is related to the state of global resources.
Occurs when the transition described earlier occurs in
state. This makes all lines high.
level and forcefully create a state where everything is “1”.
The total even number state (odd parity state) is
established, resulting in AIPE in the state described earlier
Flip flop and AIPEDLY flip flop
is set and displays a parity error.
Become so. The above configuration is for receiving at port B.
The message packet received has a parity error, or
or force a parameter to display a change in status.
The same method is used even if the property display is included.
Operate. Occurs due to noise effects and other variables
Parity errors that occur are usually caused by
It has no effect on operation and is due to redundancy.
Are you using a dual network with long-term security?
It is et al. For monitoring and maintenance,
Using an indicator light (=indicator light: not shown)
to display the occurrence of a parity error.
Ru. However, only one message indicating a change in status will be sent.
For parity errors that may occur,
routines for assessing the significance of changes
is started. As shown in FIG.
The clotting system that is
Regardless of the number of hierarchies used within
between the clocks in the node elements of
In order to ensure that the skew of
In other words, to maintain a zero skew condition.
It provides a unique means of clock
Circuit 86 includes first and second exclusive OR gates 8
8 and 89, indicated by A and B, respectively.
The outputs of those exclusive OR gates are added to the adder circuit
92, there is a subtraction between them (i.e. "B-
A) are combined so that the operation
The output of this adder circuit 92 is sent to the low-pass filter 9.
After being passed through 4, in the phase lock loop.
The output from a certain oscillator (PLO) 96
Controls the phase. First exclusive OR gate 8
The input to 8 is the output of this PLO96 and the adjacent
Isolated drive circuits from higher-level node elements
97 and a downstream clock supplied via 97.
Ru. This line of clocks has the word "word clock" on it.
This word clock is
After a known delay τ from the neighboring higher hierarchy
and this same clock belief.
The number is connected to the adjacent one via another isolated drive circuit 98.
to be returned to that node in a higher hierarchy than the one it touches.
It's getting old. to the second exclusive OR gate 89
Inputs are connected to this word clock and the adjacent
Clocks and feedback from lower levels
Similarly, this lower hierarchy consists of this PLO9.
The signal is being received from 6. The word clock line above is the third
connected to the two inputs of the other OR gate 100
and both their inputs are directly connected
is connected via the τc delay line 101.
It is with what is there. This allows you to
This word clock has twice the frequency of the clock.
Part-time job/crotch at the right time
I am getting a clear signal. The operation of the clock circuit 86 described above is similar to that of the clock circuit 86 shown in FIG.
This can be better understood by referring to the timing diagram.
I can figure it out. Clock out signal (clock out signal)
force signal) is the output of PLO 96. This black
The primary purpose of a networking system is to
What are the clock output signals for all nodes in the clock?
Maintain zero time skew between cows
Naturally, since there is a
Their clock output signals are at their nominal frequency.
The numbers must also be the same. node
The delay τ due to the transmission line between
However, the value of this delay is itself a given value.
Set the time to a long time within the range that does not exceed the maximum delay time of
It is also possible to set People disclosing here
If the method is adopted, the network and node
byte clock speed in an actual system.
At the adopted speed (nominally 120ns),
Can be as long as 28 feet (8.53m)
It is. As will be readily understood by those skilled in the art, possible
The largest number of processor modules available
For networks that are not specifically implemented,
By adding more layers, these 28
It is easy to obtain a length that is an integer multiple of . So
, the corresponding waiting time, i.e. the net
The transmission time for transmissions made through networks increases.
make it big The wave just below the clock out signal in Figure 7
Higher than the adjacent one, as indicated by the shape.
The word clock obtained from the rank hierarchy is
It has the same waveform as the checkout signal, but only
is delayed by τ. This word clock is
A fundamental timing standard common to all nodes
But is such a thing possible?
The leading edge of each clock out signal is
can be controlled inside the tract, and their
By having the leading edge precede the word clock.
to keep all nodes in sync.
This is because it can be done. Waveform A and wave
As can be seen with reference to form B, the first OR gate
Pulse A generated by 88 is the pulse A of the word clock.
terminating at the leading edge, while the second OR
The leading edge of pulse B generated by pulse 89 is
It coincides with the leading edge of De Klotsk. This B pal
The trailing edge of the
at the start of the feedback pulse from the
and this feedback pulse is only τ
Because of the delay, the B pulse has a uniform duration.
It has become fixed. The clock circuit 86 receives the pulse A
Keep the duration of pulse B the same as that of pulse B.
Why does it work like this?
advances the phase of PLO96 to increase the probability of synchronization.
As the output signal of the adder circuit 92 increases, the output signal of the adder circuit 92 increases.
signal (signal after subtraction “B-A”) is close to zero.
Because I will follow you. In fact, it is indicated by a dashed line.
It may also be ahead of the preferred position, as shown in
Adjustment for the leading edge of the A signal, which may be delayed
The leading edge of this A signal is the word clock.
so that it is at a position that precedes the leading edge of by a time τ
do. Clock out on all nodes
so that the leading edge of the signal is located in this preferred nominal position.
If so, there will be a zero shift between word clocks.
A queue condition will exist. Therefore, net
Each processor connected to the workpiece
The entire path from one processor to another
Although it is freed from constraints regarding length, it is
The fact that delays do not accumulate and that during propagation
This is due to the fact that there is no difference between
Ru. To generate a double frequency byte clock
In order to
The word clock is duplicated and this delay
The line extension 101 also supplies a signal to the gate 100.
Ru. Therefore, it is indicated as bite clock in Figure 7.
As you can see from the waveform shown, the word clock
has a duration τc at both the leading and trailing edge positions of
A byte clock pulse is generated. this
Pulse generation occurs at each word clock input.
It occurs twice during Tabal, and all
generated at the node in synchronization with the word clock.
It's working. In the above explanation, nodes and node
The delay caused by the transmission line between
Which direction is the transmission direction from layer to layer?
are almost identical, so in effect this system
All word clocks and byte clocks in the system
If the clocks are kept in a stable phase relationship with each other,
That is a natural premise. therefore local
Bytes generated internally (=inside an individual node)
The clock is set at each node.
2-byte word (= 2 bytes) of the page
word) for its individual bytes.
It offers king functions. More than one active logic node can be dispatched at the same time.
prevent contention between sent message packets.
The decision is made based on the data content of
There are potential benefits whenever
Ru. In contrast, for example, the issue dated February 17, 1981
U.S. Patent No. 4,251,879 “Digital Communication”
speed-independent arbiter for network
Speed Independent Arbiter Switch
for Digital Communication Nbiworks)
The majority of publicly known information, including those
The system determines which signal was first received in time.
The aim is to determine whether the
It is also possible to use a processing circuit or control circuit installed in the
It has become a (Processor module) Illustrated in the schematic diagram of the entire system in Figure 1.
The individual processors
Eighth Processor (IFP) 14 and 16 and
Process module processor (AMP) 18
This is shown as a specific example of ~23, and this
These processors roughly reprocess multiple key elements.
It is divided. These processor modules
(IFP and AMP) configuration
The example is between the general functional reclassification in Figure 1.
However, if
It also shows quite a few further subdivisions.
Become something. As used herein, "Professional"
The term “setsa module” is illustrated in Figure 8.
It refers to the entire assembly that is
This assembly includes the optional requirements described below.
IFP or AMP can be
It will be able to function as either one.
Also called a "microprocessor system"
The term refers to a system with a built-in microprocessor 105.
This refers to the stem 103, where the micro
The processor 105 is, for example, an Intel 8086 type processor.
(Intel 8086) 16-bit microprocessor, etc.
It is. The address of this microprocessor 105
The microprocessor path and data path
Inside the Tsusa system 103, for example,
General peripheral systems such as in-RAM107,
and peripheral device controller 109.
Ru. This peripheral device controller 109 is a
Tsusa module is an AMP and a peripheral device
Can be used when is disk drive 111
This is shown as an example. In contrast to this
This processor module can be used as an IFP.
If the
As shown, this controller or interface
interface, for example, a channel interface.
You can replace it with IFP for such a specific example
is connected to the host system channel or bus.
It will be used for communication. This microprocessor
The Tsusa System 103 has conventional general controls.
Can use rollers or interfaces
So those controllers and interfaces
There is no need to explain it in further detail. One device per microprocessor
Using a hard disk drive improves both cost and performance.
Being able to show that you have an advantage in terms of
It should be noted that Such a method is advantageous.
This is common when it comes to databases.
However, sometimes one
microprocessor accesses multiple secondary storage devices.
configuring the microprocessor for access.
Sometimes it is beneficial to In the schematic diagram,
To simplify the diagram, other commonly used
Regarding the inclusion of subsystems
is not shown. This omitted subsystem
The system is, for example, an interrupt controller, and
The controller is made by a manufacturer that manufactures semiconductors.
for use in combination with their own in-house systems
It is supplied to In addition, the present invention provides
Achieving the maximum possible redundancy and reliability
Supplies power to processor modules that can
The importance of taking appropriate measures to
However, it will be understood by those skilled in the art. In the microprocessor system 103
Peripheral controls shown as optional elements
Roller 109 and channel interface
is the IFP interface and disk in Figure 1.
This corresponds to a network controller. this
On the other hand, the high-speed RAM 26 in FIG.
First HSRAM26' and second HSRAM26''
and each of them has a time mark.
By multiplexing (time multiplexing)
From above, it becomes a de facto 3-port device.
and one of those ports (indicated in the diagram) is
via the micro port (port marked “C”).
Connected to the processor's bus system.
Each of the HSRAMs 26' and 26'' has a first
Second network interface 12
0,120', thereby each
1 and 2nd networks 50a and 50b (this
These networks are not shown in Figure 8.
), input (reception) port A and output (transmission)
Communication is now performed via port B.
Ru. In this way, two systems with mutual redundancy
system, so a second network
Interface 120' and second HSRAM2
You only need to explain 6″ in detail.Network
About Ku Interface 120, 120'
is shown and explained in further detail in connection with FIG.
However, if they are broadly reclassified, they are as follows.
It can be divided into the following four main parts. 10 input lines from the second network 50b.
interface data bus and
H. via the interface address bus.
The input register connected to the A port of S.RAM26''
register array/control circuit 122; The output line to the second network 50b is
interface data bus and
Face address bus and second HSRAM
Output resistor connected to 26″ B port
data array/control circuit 124. interface address bus and input
Turf Eighth Data Bus and HSRAM2
Connected to 6″ A port and B port,
Microprocessor bus interface/
Control circuit 126. Receive word clock from network,
and for controlling the interface 120'.
multiple objects that are synchronized with each other and have an appropriate phase relationship
A clock generation circuit 12 generates a clock of
8. Second network interface 12
0' and HSRAM26'' are microprocessor
By collaborating with the service system 103,
Networks that operate faster and more
Transfer data to and from processors that operate at low speeds.
coordinate, and furthermore, their differences.
Natsuta system (= network system and program)
messages exchanged between
It also serves the function of creating a queue. My
Chloroprocessor bus interface/con
Troll circuit 126 is a microprocessor system.
In cooperation with the stem (read/write function: R/W
function)
This microprocessor system can
at least if it is an Intel 8086 type)
Ability to write data directly to HSRAM26″,
The ability to receive data from this HSRAM26″
It is equipped with The structure of IFP and the structure of AMP are related to their actions.
are similar to each other, but
, the internal input message status of HSRAM26″
Storage area size and output message storage area size
There is a considerable difference between IFP and AMP in terms of
There may be differences. relational day
In database systems, IFP
of the host computer by constantly using the work
In order to meet the requirements, HSRAM2
New features from high-speed network are installed inside the 6″
A large input message box for receiving messages.
It has storage space. The opposite is true for AMP.
It can be said that it is transmitted to high-speed network.
For processed message packets that
More storage space is becoming available.
This is because it has to be done. HSRAM26″ is
Maya in the microprocessor system 103
It also operates in cooperation with the RAM 107.
Main RAM 107 is for each network
Equipped with a message buffer section.
Ru. For microprocessor system 103
The system address inside the main RAM 107
The aspect of space space allocation is shown in FIG.
Let me briefly explain this. General method
Storage capacity for random access according to
Leaves space for expansion to be used if the
The system random access function
and the /0 address space
and functions of ROM and PROM (including EPROM)
also has an address space allocated for
It has become a Additionally, the system address space
some parts of the first and second parts, respectively.
Messages sent from high-speed RAM 26', 26''
packets and send them to high-speed RAM.
allocated for message packets
ing. This provides great flexibility in system operation.
The microprocessor
The server 105 addresses HSRAM26″
Even if it is possible, the main RAM 107
Through the function of software and hardware,
Is it possible to become less constrained by the interdependence of
It is et al. I will explain about Figure 8 again, but I have already mentioned it.
It can be accessed from two directions.
HSRAM26″ is in multiprocessor mode
control, distributed updates, and message packets.
performs the core function of managing the flow of
It is configured to These purposes and further
In order to achieve the purpose of
It is divided into a different number of internal sectors. 8th
of the relative placement of the various sectors shown in the figure.
The aspect is that the individual processors in this system
This is used in all modules.
and also specifies the boundaries of those sectors.
The specific address is based on an actual system.
This indicates the address being used.
Please note that these notes
The size of re-sectors and their relative placement
can vary greatly depending on the specific system situation.
This means that it is something that In the example shown, 16 bits
memory words are employed. selection map
and the response directory is set once during initialization.
A dedicated lookup of the kind that you only need to write
table, while the transaction number
The bass section can be dynamically revised (= movement
You can change the contents as many times as you like
(I made it like this) by providing a table
There is. The memory section of the selection map is located
However, in this specific example, the basic
Basically, inside this memory section, there are four
Different maps have come to be used.
and those maps can be used in an interrelated manner.
It is something that will be done. in the message packet
The included destination selection word (destination
selection word: DSW) is in HSRAM26″
used in conjunction with the dedicated selection map of
It will be done. This destination selection word has a total of 16 bits.
and 12 bit positives of which
Map address and 4 others occupying the area
map selection data occupying bits of
It is said that The first 1024 16 bits of HSRAM
The pine memory words each have four pine
Contains the drop address value. specified in DSW
one memory to HSRAM according to the address value
All four masters can be accessed by simply performing memory access.
Map bits for the tup are obtained, while
And the map selection bit included in that DSW
now determines which map to use.
It's summery. Figure 15 shows the concept of the above map section.
The figure shows the structure of each
4096 x 1 bit as if the map were physically separated
shown as if it consisted of a single RAM.
It is. Taking into account the convenience of implementation,
As shown in Figure 8, all map data
data is stored in a single portion of HSRAM.
It is convenient to do so. DSW management section 1
90 (Figure 13) is one 16-bit HSRAM
The four maps in Figure 15 obtained from the word
, for 4 bits from each of them.
Controls plexing motion. Those skilled in the art will understand
As can be seen, the advantage of this method is that HSRAM
used to access other parts of
The processor initializes the map using the same means as
The point is that it can be configured. Furthermore, the transfer of three different classes (classifications)
The preselection word is used and correspondingly,
The storage location of the selected map is the hash selection.
part, class selection part, and destination processor identification
Other information (destination processor
indentification: DPID) divided into selected parts
There is. This DPID is determined by the processor 105.
the intended destination for the message packet.
It also specifies whether a specific processor is
It is. On the other hand, the class selection part
The processor receives the message packet.
Multiple processes belonging to a particular processing class to take
whether it is one of the tusa, i.e. the process
Specify whether or not you are a member of the Tusa Group
It is something that The hash value is a relational
There is a database inside the database system.
It is stored according to the distribution method when distributed.
This distribution method is adopted in the system.
Algorithms for specific relations
It follows the system and distributed storage method. child
The hash value in the specific example is
When setting the data, the processor
primary responsibility for data and backup responsibility.
Specify it as having either one of the following.
It is becoming possible to do this. Therefore, more than one
HSRAM26″ can be directly selected by the selection map of
whether the processor is the destination or not
I am now able to use the method of determining
Ru. This feature allows messages that have been given priority
all network interfaces 120
The method of broadcasting to
It is a complementary function and does interrupts.
Status of microprocessor 105 without
Functions that allow local access to
There is also. Independent from other parts of HSRAM26″
one section that has been created is globally distributed.
A central location for checking and controlling various activities.
It functions as a means of As already mentioned,
Also, as shown in Figure 3, the network
50b, and this network 50b
For each of the various processing received from
Zaxion number (TN) is assigned.
Ru. TN is included in the message
is received by each processor system 103.
when executing subtasks independently from each other.
Global transaction identity
(transaction identification information).
Multiple available transistors in HSRAM26″
for storing the address of the number
Dedicated blocks perform those subtasks.
When the microprocessor system 103
locally controlled and updated status
Contains entries (=already stated items about status)
are doing. TN is used when intercommunication functions are performed.
, a variety of different sources exist both locally and globally.
Used in usage. transaction number
calls the data to identify the subtask.
Message flow for giving commands
to control the dynamics of global processing as well as
Used to identify the type of food. Tran
The execution number is assigned during global communication.
can be applied, abandoned, or changed.
Wear. These features are described below.
This will be explained in more detail below. Perhaps the most complex feature of TN is
The most effective feature is the sort net
network (network with sorting function)
for a given control process by cooperating with
related local processors (=individual processors)
Enables decentralized updating of the status of
It is the ability to do something. Each control process
(i.e. task or multiprocessor sliding)
has its own TN. Readiness state (how the processor operates)
The value of H.
Transaction number section of S.RAM26″
It is designed to be held in the
The value of the state of the microprocessor
locally under the control of the system 103 (=individual processes
inside the Tusa module). microphone
The processor system 103 is configured as shown in FIG.
the appropriate entry in the answer directory (e.g.
SACK/Busy) (address is "050D (hexadecimal)")
can be initialized, and thereby
By transferring the image exactly as it was duplicated.
Therefore, the HS of this SACK/Busy status
Input to RAM26″. A certain TN address (=
(Storage location corresponding to transaction number)
The entry entered in is HSRAM26″
through the A and B ports of the
- network 5 via face 120'
It is now possible to access from 0b.
Inquiries can be made using status requests (status
request) command code (see Figure 11) and
"Status request" message including TN
This is done using a page. interface 12
0' is stored in the TN address of the specified TN.
Please write in the appropriate format using the content provided.
The reply date containing the received reply message.
refer to the directory. global space for a given TN
Status queries are sent to a second network interface.
If the face 120' is received,
direct control that is only under hardware control.
A response is elicited. No prefix communication is required.
Also, the microprocessor system 103
be interrupted or affected
Nor. However, the "lock" display is
by being transferred to interface 120'.
If the status is set by
The microprocessor system 103 disables interrupts.
The interface 120' also
Lock word obtained from the base “0501 (hexadecimal)”
continue to communicate until its removal occurs at a later date.
Ru. The readiness word format is
“Busy: state in progress” in Figure 12
7 from ``initial (initial state)''
Fig. 12 shows the actual situation.
One useful example adopted in the system
An example is illustrated. More readiness
Examples of changes such as classifying into types or fewer types
Although it is possible to change the classification to
By using seven types of states, many
A wide range of control can be achieved to suit the application.
Status level of individual TN in HSRAM26″
(= Entries stored in individual TN addresses
Inherit the level of readiness indicated by
Continuously updated, thereby making use of subtasks
Possibilities and progress of processing subtasks are reflected.
It is important to keep the microprocessor
It is considered the responsibility of the system. updates like this
Using the format shown in Figure 12,
Write to TN address in HSRAM26″
It can be easily carried out by In Figure 10, each status response (status
response) is a number from “05” to “0D” (hexadecimal).
For all objects, the first part is stamped.
Status response command code (status
acknowledgment command code: SACK)
It's starting. Those sent to the network
The SACK response is actually the command in Figure 10.
code and word format in Figure 12
and the source processor D (OPID)
This is shown in Figure 11.
As shown below. Therefore, those SACK responses
The answer is based on the overall priority convention shown in Figure 11.
Internally, a set of priority subgroups
forming a loop. OPID is related to priority convention
The reason why it has meaning is, for example, if multiple
The processor is working on one TN
However, none of them are in a "busy" state.
If so, choose the best broadcast
The destination message is judged based on this OPID.
This is because you will be killed. Transfer and system
Coordination of the program is also based on this data.
(OPID). Superior to SACK messages (=SACK responses)
There are rules for seniority and multiple My
Simultaneous response from the processor system 103
is sent, and network 5
0b dynamically (= while transmitting)
This is due to the fact that the determination of prior rights is carried out.
for a given task compared to traditional systems.
Determining the status of global resources related to
It is now being done in an improved way.
The resulting response is unique and regulated.
It never represents an undefined state, and
is a local process with no software required.
time for each processor (=individual processor module)
It doesn't make you waste your money. Therefore, for example, task
due to frequent status requests that prevent the work from running.
Never do anything that would cause a deadlock.
do not have. At various status levels,
You can take advantage of the chip processor's many optional actions.
I can do it. local processors
can continue to operate independently and in a single
A single global priority can be determined by querying
What does it mean that a given response is elicited?
It was an unprecedented thing. Regarding the series of states shown in Figure 12,
It may be helpful to explain this in some detail here.
Probably one. “Busy” state and “waiting”
(waiting) state means that the assigned
Delegated sub-tasks will be completed over time.
We will now proceed to a stage close to completion.
If you are in "waiting" state, please update
state that requires a communication or event
It represents. These “bizui” and “wazai”
The status of ``eating'' is higher than the status of TN.
Rise to a higher level and finally the TN
Send or receive messages/packets related to
I want to reach the status level that I can.
This is an example of level increase. On the other hand, sending or receiving message packets
In addition to the above, there are other characteristics of TN.
The ability of TN in message control is demonstrated.
It will be. microprocessor system
103 now has a message to send
, the status display will be "Ready to send".
ready)”. microprocessor system
The system 103 participates in updating the status display.
Then, using the word format shown in Figure 12,
Set the value of "Next Message Vector" to HS
Input to RAM26″.This input entry
The corresponding output message is sent to HSRAM2.
6″ from which location should I take it out?
It is clearly stated. This vector is
Combine multiple output messages related to TN into one
In order to throw (= chain),
At the work interface 120'
For internal use. Functions related to the above functions are displayed as "Ready to receive".
(receive ready) state. this
In the “Ready to receive” state, the storage location of the TN is
MicroPro
Input data obtained from the setsa system 103
The page count value is now retained.
This input message count value is
Messages that can be received related to TN
This is a value related to the number of . This count value is
As input messages are transferred one after another,
It may be decremented and eventually reach zero.
be. If it becomes zero, there will be more messages
overrun.
The status will be displayed. As above
and connect network 50b and my network using TN.
of transmission between the processor system 103 and
The speed is adjustable. Local (= for each processor) station
In terms of aspects, individual processor
If the process is being performed, the TN will
The entire system is displayed in messages and received messages.
It is held as a constant and unchanging standard that is valid in
Ru. The “TN0” state, that is, the default state, is
You should use tsage in non-merge mode.
A local command to indicate the fact that
It also functions as a card. To explain from a more global perspective, “TN0”
and various values with “TN>0” that are different from each other.
By distinguishing it as a property of
Of the multiple command functions that use TN,
One command function is defined. In other words, that
By distinguishing TN like
Characteristic description that indicates either "merging" or "non-merging"
(Characterization) is the message of each person.
The packet will be accompanied by
priority determination and sorting for multiple messages.
The dominant way the system works is to
The formula has been obtained. Similarly, "Assign
"Assigned",
“Unassigned”
"Non-processor state)", "Non-processor state"
Participant)” and the string “Initial”.
Global intercommunication and control functions using status
is now being carried out. “Unassign
The 'do' state indicates that the processor has previously abandoned the TN.
and therefore it re-tns
Receive new revitalizing primary messages.
This is a condition that needs to be taken. If the status display is
When the processor should have been ``signed,'' the
If you are viewing “Assigned”, this is the TN
was not entered properly.
Therefore, corrective action must be taken.
No. If TN should be "unassigned"
If it is set to "assigned" when
This could be due to an incomplete transfer or
Between two processors in search of a new TN
is an indication that a conflict is taking place in
There is. These “assigned” and “unassigned”
Both are treated as readiness states.
The reason is that they are not labeled.
At this stage, the processor still has no knowledge of the TN.
This is because the work to be done has not yet begun. Furthermore, the ``initial'' state and the ``uninvolved process''
The "tsusa" state is also important in relation to global resources.
A processor attempting to go online will immediately
First, you must complete the procedure to join this system.
The processor must be in the “initial” state.
This condition means that this processor cannot be brought online.
Administrative steps must be taken to
It represents that. Regarding a given task
A processor in the "non-participating processor" state is
No need to perform any processing locally
However, I decided to track and monitor this TN.
If this TN is inadvertently used inappropriately,
It is necessary to make sure that this does not happen. To explain about Figure 10 again, HSRAM
26″ dedicated directory or reference section is:
In addition to the types explained above, hardware
The priority used to generate a response to
Multiple other types of messages granted with
It also includes ji. NA (not assigned)
The entry ``has not been received'' is used for future
prepared for use and kept in a usable condition
It is. Three different types of NAK responses
(Overrun, TN error, Locked)
each NAK response) whose data content is the smallest
value and therefore has the highest priority
But it seems that those NAK responses have an error condition.
This is because it shows. after multiple SACK responses
ACK response, and NAP response (non-applicable processor
responses), and their priority decreases.
arranged in order. In this specific example configuration,
Two response command codes are assigned functions.
(i.e. NA), they are
It is kept ready for future use.
Ru. The directory explained above is the software
It can be initialized by
A wide range of different responses can be utilized by the air
What kind of message text
However, it should occur quickly and flexibly.
I can do it. From other parts of the above directories
uses one independent part that is independent,
TOP, GET, PUT, and BOTTOM
address, i.e. the circular bar for the input message.
Pointers about Tsuhua's features and completion outputs.
A pointer to a message is stored.
Each of these pointers manages input messages.
and the management of output messages.
Functions in conjunction with each dedicated sector of S.RAM26″
It has come to fulfill its purpose. For input message
A circular buffer method is used for this purpose.
If HSRAM26″ directory
“TOP” stored in the input message
variable address that specifies the upper address location for the
It's becoming a dress. Same directory sexy
The PUT address stored in the
Where should the circuit store the messages to be transmitted?
This specifies the address location. GET
The address is blanked out by the software.
The hardware recognizes the address location being processed.
The software allows you to
It is set and continues to be updated. To manage input messages and buffers, use PUT.
Set to the bottom address of the buffer.
and the GET address is equal to TOP
This is done by starting from a state where
Ru. Operationally determined by the software
The rule is that GET is set equal to PUT.
This means that if such a situation occurs,
If set to
This may result in the occurrence of
Ru. The input message is input in HSRAM26''.
When a message is input to the message buffer, the message is
message length contained within the message itself
The value determines the starting point of the next incoming message
and then stored in the directory
The next input message for the PUT address.
The storage location within the buffer that should accept the page.
Changes are made to display the text. More than
Microprocessor system
103 uses the input menu when their work ability allows.
To be able to take out the tsage
It's summery. Output message storage space in HSRAM26″
The data stored in the
Output media held inside the circular buffer
Tsage completion vector and HSRAM26″
used with the next message vector in
It will be done. Editing (assembling) individual messages
and storage at any location.
You can also create multiple messages that are related to each other.
messages, send them over the network.
The process of making connections (chains) to
I am becoming able to do this. HSRAM26″
In the directory section of TOP,
BOTTOM, PUT, and GET addresses
input and updated as previously described.
The output message completion bar is
Dynamic current information about locations within Tsuhua
The mark is maintained. The message completion vector is
Messages stored in the output message storage space
sage and has already been properly forwarded.
This is indicated by the response received.
Configure an index address to point to the page.
has been completed. As explained later, this system
is output by the microprocessor system 103
Makes it easy to enter messages.
On the other hand, this microprocessor system 1
03 organizes complex concatenated vector sequences
We have made it possible to handle it in a different way, and by doing so,
Output message storage space is used efficiently and messages
Enables tsage chain transfer.
Ru. The prototype of Figure 11, discussed earlier in connection with the response.
The call follows the response to the primary message.
It is also stipulated that Multiple types of response messages
The pages are arranged consecutively to each other, and the hexadecimal
Command codes are illustrated in ascending order. plastic
Within the group of immediate messages, merge
Stop message (This message is used for basic control
A non-merge control message that is a message.
), but the data content is the minimum value.
and therefore has the highest priority. This message
The network and processor module
Control to exit merge mode in a tool
constitutes communication. With so many different types of primary data
Use data messages in ascending priority order
and they also have application requirements.
priorities based on
Classification regarding ranking can be added. mentioned earlier
A sequence that follows another message, as in
For subsequent messages, the preceding message
to maintain continuity from the sage packet.
Make sure to give it a high priority in order to
can be done. The first message consists of four types of primary messages.
The bottom group in Figure 11 has a high priority.
Get status response from lower to lower
The only type of status message that requires
Status/request/message
page, requesting “TN Waiver” and “TN Assignment”
each control message, and also the priority
Contains a low “merge start” control message.
Ru. The above configuration is a more detailed example that will be explained later.
As is clear from
This makes it possible to processor module
Currently the transaction number (Present
transaction number (PTN)
In this case, the PTN is
partially specified by instructions from the network.
It also performs continuous movements, even if
It must have been generated internally while the
Both are the same thing. merge operation is performed
When the processor module is in the global
references, i.e. transactions, ideas.
(to identify transactions)
information) to perform the operation.
This transaction identity is
Defined by TN. Opening a merge operation
Start, stop, and resume with simple message changes
It is done using only The subtask is
If you don't need to merge the sage
or have a particular relationship with other messages.
In cases where a message packet is generated that is not
If so, those messages will be sent to “TN0”.
to create a queue for output.
and currently the transaction name
basic state, or default state, determined by the
While the root state (which is 0) maintains the true state
The transfer will take place. This “TN0” state is
When page mode is not used,
queuing messages for transfer.
It makes it possible to (Network Interface System) From now on, we will explain about Figure 13.
is an interface suitable for use in the system of the present invention.
- Showing a specific example of a face circuit in more detail
It is. This “network interface”
The explanation in the chapter ``Systems'' will help you understand the invention.
The above includes a number of detailed features that are not necessarily required.
However, their characteristics may vary depending on the actual system.
It is built into the system, and therefore the book
Clarify the position of various specific examples with respect to the gist of the invention.
I decided to include it in the explanation for clarity. concrete
configuration and detailed structure for gating
However, it is not the subject matter of the present invention, and is not a subject matter of the present invention.
When it comes to stages, there are a wide variety of alternative configurations.
It is also possible to adopt
I decided to simplify it. Figure 13 is Figure 8
The second network interface shown in
Detailed drawings of Ace 120' and HSRAM 26''
be. Each interface for the two networks
- Faces 120 and 120' have the same system
therefore, we cannot discuss only one of them.
It is enough to clarify. In FIG. 13A, the interface of the same figure is
active logic network connected to
The input from network 50 is connected to multiplexer 142 and
Through the intellectual parity check circuit 144,
Supplied to the network and message management circuit 140
has been done. The multiplexer 142 also has a microphone
connected to the data bus of the processor system.
This allows the
to access the message management circuit 140.
is now possible. This feature allows the microphone
Loprocessor system provides interface
Runs in step-by-step test mode.
It has become possible to make this
The interface is connected to the network as if it were an open network.
the device as if it were connected in line.
Data transfer is now taking place. Netsu
Input from the network is sent to the receiving network data.
data register 146;
input to the first section of the connector register 146
Byte data to be sent and byte buffer for reception
is input to this register 146 via the register 148.
Byte data for reception
Fur 148 sends the byte data to the first section.
After the data is input, the own byte data is
data into another section of this register 146.
Strengthen. This allows each word received to
Both of the two constituent bytes are
network data register 146;
and be kept there, available.
become. The output message to be transmitted is
input to network data register 150.
In addition, the inside of the normal parity generation circuit 132
A parity bit is added at . Metsuse
The network message management circuit 14
0 to the network connected to it
or (test mode is used)
microprocessor system device)
data bus. This interface
For the purpose of internal message management,
stored in random access memory 168.
The format of the sent message is
It shall include identification data as well as identification data.
It is. As can be seen in Figure 21A, the command
This includes all codes, tags, keys, and DSWs.
combined with the primary data transmitted from
You can keep it. The configuration shown in Figure 13A is essentially
The configuration is the same as that shown in Figure 8, except that
Figure 8 shows the interface data bus
and the interface address bus is H.
Input port A and input port B of S.RAM26″
connected separately and also connected to the microprocessor system.
The address bus and data bus of stem 103
connected to a separate C port.
Illustrated. However, in reality, the 13th
As you can see from Figure A, these mutually independent
This interface allows access from two directions.
In HSRAM26″, which is carried out inside
Time and minutes of input address function and output address function
This is achieved by split multiplexing.
Microprocessor data bus and address bus
buses through gates 145 and 149, respectively.
connected to each bus of the interface.
, which allows the microprocessor to run asynchronously.
can operate based on its own internal clock.
It is becoming more and more like this. The timing system employed is clock
Based on pulses, phase control waveforms, and phase subdivision waveforms.
This phase subdivision waveform is
Interface clock circuit 156 (13th
), and the type shown in Figure 14.
(see Figure 14).
(This will be explained later). interface
Lock circuit 156 connects the network from the nearest node.
I have received my work word clock and
Phase lock clock source 157 is
Zero tie as described above in connection with Figure 4.
Contains means for maintaining muscle spacing.
Ru. Nominal network in 240ns network
The clock word clock speed is
internally within the clock circuit 156.
It is subdivided and this is done by
Frequency multiplier held turned on (see details)
(not shown) defines a reference period with a duration of 40 ns.
high-speed clock (shown as PLCLK in Figure 14)
This is because it provides the following: Basic
The reason for determining the word period is that the total period is 240 ns.
In the figure, CLKSRA is reversed every half cycle.
This is a periodic signal written as . This CLKSRA
There are two other signals with the same frequency and duration as
is generated by frequency divider 158 based on PLCLK.
Each of these signals is connected to CLKSRA.
1 cycle and 2 cycles of PLCLK from
This occurred at a delayed time, and each
Given the names CLKSRB and CLKSRC
There is. Based on the above various signals, control logic 1
59 is "IO GATE", "RECV GATE", etc.
Timing waveform called “SEND GATE”
(hereinafter also referred to as gate signal),
These timing waveforms are word periods apart from each other.
Display each successive third interval.
It is something that These intervals include
``AIDS'', ``Receiving phases'', and ``Sending phases''.
The corresponding name has been given. Above gate signal
These phases defined by the
Each further has an "IO CLK" signal, "RECV CLK"
2 by the signal as well as the “SEND CLK” signal.
subdivided into two equal half-intervals.
These subdivision signals are the second half of each phase.
The part is determined. Bite closing function
The “BYTE CTRL” and “BYTE CLK” signals
It is managed by the No. The above IO phases, RECV phases (receive phases)
AIDS), and SEND phas (send phas)
is random access memory 168 and microphone
The processor system bus is time-division multiplexed.
(time multiplexed)
It provides the foundation for making the hair grow.
be. The interface is connected to a high-speed network.
1 word per word period between
cannot receive or send data, and it is obvious that
In fact, receiving and transmitting are never done at the same time.
stomach. performed between the microprocessor system and the microprocessor system.
The speed of the transfers that are
Although the transfer speed is considerably lower than that between
Even if both speeds are equal, the interface
This may place an excessive burden on the capacity of the face circuit.
There is no such thing. The system structure of this interface
The configuration is a download to random access memory 168.
Most operations are performed through direct access
internal processing.
so that very little software is required
It's summery. Therefore, this system
cyclically repeats multiple consecutive phases in a cycle.
As time passes, multiple words appear one after another,
Moreover, those words can be used without colliding with each other.
along predetermined multiple signal paths for
and perform various functions.
The sea urchin is sleeping. For example, a message to a bus
The output of the message is from the microprocessor.
be done between page pickups, and
each of them also occupies a different portion of memory 168.
can be used alternately.
Ru. Microprocessor system data bus
and the network interface.
Communication is carried out by the IO management circuit 160 (read about this IO).
Also called Read/Write.
It is carried out within the Microprocessor
Gating the words sent from the stem
write gate 162 for
System for sending words to the Tusa system
Microprogram read register 164
Losetssa bus and network interface
connection between the bus interface and the
It is. Additionally, memory address register 165 and
The check generator/check circuit 166 is
integrated into the network interface subsystem.
It is. In this specific example, the high speed memory (=
HSRAM) is a 4K word x 17 bit random
It consists of an access memory 168, of which
How to repartition internally and what happens inside this memory
Use of multiple dedicated memory areas provided
The law has already been explained. child
Random access memory size (=capacity)
amount) to suit the needs of the specific individual application.
can be easily scaled down and expanded.
Wear. The received message buffer management circuit 170
connected to the microprocessor's data bus
and even the memory 168 address bus.
It is connected. "received message"
The term "messages" is used to describe
It is called "PUT" in the circulation buffer.
Refers to messages entering a storage location.
It is also used to indicate
After the input, enter into the circular buffer in that way.
Transfer the input message to the microprocessor
However, it is used to refer to that transfer.
Sometimes it happens. This transfer to a microprocessor
When the transfer takes place, the value of ``GET'' is
Received messages to be transferred to the processor system
How does the system perform the message extraction?
Continuous extraction operations should be performed from one location to another.
Specify the strength. Random access memory 1
Multiple address values used for 68 accesses
But GET register 172, TOP register 17
4. PUT counter 175 and BOTTM register
data 176 respectively. PUT counter
175 is specified by BOTTOM register 176.
Increment by 1 from the specified initial position
updated by TOP register
174 also gives an indication of the boundary on the other side.
It is. What is the value of TOP and BOTTM?
can also be operated by software control.
and thereby reduce the received message buffer.
Size and absolute storage location in HSRAM
It is now possible to change both the
The contents of the PUT register are equal to the contents of the TOP register
If the error occurs, the PUT register is reset.
is made equal to the contents of the BOTTOM register, and it
This buffer can be used as a circulating buffer.
It is now available for use. Get more Regis
data, TOP register, BOTTOM register, sequence
The PUT counter is a circular cross for input messages.
both the buffer and the output message completion cycle buffer.
is used to manage. Input to the GET register 172 is done by software.
It is carried out under the control of
Messages being handled at the time in the country
Depending on the length of
This is because the response (response) is determined. GET register
172, PUT counter 175, and TOP register
Comparator circuit 1 connected to each output of star 174
78 and 179 detect and display overrun conditions
is used to. The overrun condition is
GET value and PUT value are set to equal values
or set the GET value to a value greater than the TOP value.
the condition that arises when an attempt is made to
It is. In either of these cases, the overrun
status display will be sent out, and only
This status display also indicates that the overrun condition has been corrected.
It will continue to be sent until the Configure and operate a “received message” circulation buffer
The continuous method described above when
This method is particularly suitable for the system. Collision
This enables mutual checks to avoid
By setting "PUT" to the hardware
and dynamically manage “GET”
It is becoming possible to do this. However, this
Adopting a buffer system other than
is also possible. However, in that case, it is likely that
some redundancy in terms of road and software.
This will add to the burden. Here, Figure 21B
To mention, the data stored inside the memory 168
The format of received messages stored in
map results, data length, and key length.
Contains shape identification data, and these data
I will explain later how this can be obtained.
Ru. The DSW management section inside this interface
190 is the transfer destination selection word register 1.
92, and this destination selection word register
From now on, the data will be transferred to address bus 192.
A destination selection word (DSW) is input.
Dedicated DSW section of memory 168 using DSW
When you address the memory 168,
The output sent on the data bus returns data,
Based on this data DSW management section 19
0 indicates that the message packet is
to determine whether the forwarding destination is
It is becoming possible to do this. It can be seen from Figure 13A
The destination selection word is a 2-bit pine
nybl address and 10-bit pine
4 for map word address and map selection
It consists of bits. Of these, “nib”
address is the address of the word from memory 168.
Used to describe a bussection. Ma
The 4 bits for map selection are the map result comparator.
194, which comparator 194
from memory 168 via lexer 196
Map data is being received. Machiplexer 1
96 receives 16 bit data, and this 16
The bits included in the DSW are
specified by the 10 bits of the program word address.
Four different maps stored at the address
Represents a data nibble. memory 1
68 is, for ease of comparison made here,
Its dedicated map section is particularly suitable for comparison.
It is structured in a form. To multiplexer 196
inside the DSW, which is supplied for its control.
The remaining 2 bits give 4 map nibbles.
One of the corresponding map nibbles is selected.
It will be done. A comparison was made and the result of the comparison was
Map code goes to map result register 197
input and is input to memory 168
inserted into the input message. If this ratio
As a result of the comparison, there are no
It turned out that the "1" bit did not exist.
If a “reject” signal is generated and the
The setsa module is the message packet
It appears that it is not intended to receive
shown. To explain Figure 15, there is a memo in the figure.
Subdivide the dedicated destination selection section of 168
It is the preferred method for
A preferred method for making the comparison is illustrated schematically.
It is. Each map is 4096 words x 1 bit
It consists of
Sector, sector for class ID, and hashing
It is subdivided into sectors (see Figure 8). 12 pieces
Address bits (10-bit map address
and 2-bit nibble) to create a common map
Once a dress has been selected, it will
A 1-bit output is obtained from the tap. (Main in Figure 13)
The multiplexer and its nibbles are shown for clarity.
(not shown in Figure 15 for convenience). those four parts
The parallel bit output is from four AND gates.
In the AND gate group 198 consisting of
It becomes possible to compare with the first 4 bits.
If the result is one or more matches,
, the output of OR gate 199 goes to the “true” state.
Become. This map result is the map result shown in Figure 13A.
can be input to the result register 197, and
Therefore, the message is accepted into memory 168.
You will be able to do it. If different from the above,
messages will be rejected and a NAK will be sent.
It becomes. Command word management section 200
command register 20 for receiving command words;
Contains 2. Command word TN fee
The address bus is accessed using the
By accessing the indicators and
The received TN is checked and an appropriate response method is determined.
The sage is determined (see Figure 18). Furthermore,
When the "Start Merge" command is being executed
TN field to PTNR (currently transacted)
data transfer to (number register) 206
The transmission route is secured, and this means "Start merging"
PTN (current transaction
This is to allow you to change the value of
be. The input message input to the memory 168 is
Regarding Figure 21, the address vector
data feed to make it available.
field or key field is used.
also includes the length values of those fields.
It's on. Their length values are the received data length count.
counter 210 and reception key length counter 211.
each of these counters is
Fields corresponding to each counter from the power source
included in those fields when the code is provided.
learn to count the number of words in a sequence
ing. Additionally, an outgoing message management section 220
is used, and this section contains the processed
Accepting packets for storage in memory 168
functions and their stored packets later.
It includes the function to send to the network. this
Section 220 includes the send transaction
data counter 222, transmission data length counter
224, and a transmit key length counter 226.
These counters are connected to the data bus with dual
directionally connected. Send transaction
The vector counter 222 is connected to the address bus.
connected, while sending data length counter
224 is connected to address generator 228.
This address generator 228 further generates an address.
connected to the bus. Output buffer/sexy
and output message completion vector sexy in Figure 8.
The method uses both the circulation buffer and the
The message is sent. However, this specific example
In this example, multiple message packets are input sequentially.
after they are defined by the vector.
They are taken out in the order in which they are placed. Inside this interface, an independent
The respective operation phases are mutually exclusive times.
It is now being executed at times like this.
By adopting the partitioning method, the memory capacity is 168
is the network clock speed
receive and supply message packets from
and perform internal operations efficiently and at high speeds.
with its own slow clock speed.
A microprocessor system that is in continuous operation
It is possible to communicate with
There is. Messages for various counters and registers
To control the gating behavior of the
The control circuit is operating in response to the control bits,
The control bits are command, DSW, data, and
Others indicate individual fields within the message.
It generates a signal. Transmission state control circuit
250, reception state control circuit 260, and R/W
(read/write) state control circuit 270
field in the data.
identify, send, receive, and processor
data while the clock is running.
It controls the sequencing of the flow. The control of this interface is in three finite states.
machine (FSM) and those FSM
each of which has transmission phases, reception phases, and
and processor (R/W) phase.
be. Those FSMs are programmable logic
block array (PLA), status register, and
Configure in a general manner using a cushion ROM
has been done. Each FSM is a network
Each lock cycle advances to the next state.
I can't stand it. Due to the large number of control signals that must be generated,
The output of PLA is further coded by action ROM.
coded. As easily understood by those skilled in the art
necessarily necessary for the operation of the network.
written for FSM mode and hence general
Translation of control sequences with detailed structures and actions
is a simple task, although it requires a lot of work. The state diagrams in Figures 17 and 19 and
The matrix diagram in Figure 18 is attached.
Included here are the
Regarding the internal structural design features that can be used
This is to present comprehensive details. 17th
The figure shows the reception phase, and Fig. 19 shows the transmission phase.
Diagrams related to AIDS and used in these diagrams.
This notation is used in this specification and drawings.
It corresponds to the notation used in the location.
For example, the following terms are: RKLC=Receive Key Length Counter (Receive Key Length Counter) RDLA=Receive Data Length Counter (Receive Data Length Counter) RNDR=Receive Network Data Word
Register (receiving network data word register)
PUTC = Put Counter (PUT counter) GETR = Get Register (GET register) Therefore, the state diagram is as shown in Figure 13 and details.
If you refer to it in comparison with the book, it will make sense even without a rough explanation.
can be understood. their state diagram
is used for complex message management and processor interaction.
In between, there are various sequences and conditional statements related to communication.
is shown in detail. In Figure 17 (Figure 17A)
``Generate response'' and ``Decode response''
and each state where the label is written, as well as
Each conditional statement indicated by a dashed rectangle is
It is described in the matrix diagram in Figure 18.
specified response and behavior.
Ru. Figure 18 shows the primaries for a given TN.
Any combination of message and readiness state
Responses generated and actions taken in response to
It shows both. it is natural
but during normal system operation
Although there is a certain degree of message rejection,
Error conditions occur infrequently. In both Figures 17 and 19, the conditions
Regarding judgments, many of them involve multiple judgments.
It is now possible to run them simultaneously
However, on the other hand, the state step is one step at a time.
Things are starting to change. In either case
Even in
Proceeds at a set speed without the need for control.
The structure of the message is
As already explained, the network and the way the network works
This is because they are getting used to it. A typical processor system or multiprocessor
The many features employed in the Tusa system are:
The characteristics may not be closely related to the present invention.
Therefore, we will not specifically describe them.
stomach. Among those characteristics are parity error times.
circuit, interrupt circuit, and watchdog timer
to monitor the sliding of extremely diverse test functions, etc.
There are various means etc. (Specific example of system operation) The following will be explained in Figures 1, 8, and
A system that integrates Figure 13 is a network and
internally in various operating modes in cooperation with HSRAM.
Here are some concrete examples of how it works.
Ru. Specific examples of these are the priority provisions and here
The addressing method and transaction
Interrelationship between the cussion and identity
But how can local control and global intercommunication be achieved?
This indicates whether the
Ru. Transmitting and Receiving Primary Data Messages In addition to the other figures, we will also refer to Figure 16.
Although I will explain this in detail, Figure 16 shows the primary
the conditions involved in the final acceptance of the message,
This is a simplified state diagram. message
Even if the data is received in buffer or memory, the illustrated
Acceptance (acceptance) is disabled until the logical condition is satisfied.
septance) has not been achieved. figure
In this example, events are shown as a serial sequence.
However, originally multiple judgments were performed in parallel and immediately.
These are now being carried out at the same time, and that is,
The conditions may not be related to each other,
or intermediate steps to reach a certain operational stage.
This is because the jump is performed by a circuit.
be. The message on the network in Figure 1 is
Receive Network Data Register in Figure 13A
146 until the EOM condition is identified.
When the message is passed and the condition is identified.
It is recognized that the message has been completed. "Lock"
(LOCK) condition exists, the system
The response delay time in HSRAM26'' in Figure 8 is
NAK/LOCK rejection message
Send the message. If not, i.e. a “lock” condition exists.
If not, the system will compare maps.
This check is shown in Figure 13A.
DSW management section 19 in the interface
Executed inside 0. Display with "map output = 1"
If appropriate comparison results exist,
, the system will continue to receive the message.
I can do it. No such comparative results exist.
If not, the message is rejected and the NAP
is sent. Once the corresponding map has been determined,
and the system is ready to check the TN status.
Now that everything is in place, this TN status check is
See the TN directory shown in Figure 8.
(here the TN stage is
Strictly speaking, a task is a processor related to a given TN.
, and therefore the status in HSRAM.
Depending on the entry stored in the TN address of
).
To explain in more detail, this TN status check
The check is based on the local status (=individual processor
module status) is "Ready to receive"
This is done to determine whether or not there is. here
is determined by the preceding primary message.
Assuming the TN allocation has already been made
There is. As a result of this check, the TN is "done".
state, “uninvolved processor” state, or “initial processor” state.
be in one of the following states:
is found, a “NAP” rejection message is sent.
transmitted (here, TN is strictly
is stored at the TN address in HSRAM.
However, below, there is a risk of confusion.
Unless otherwise specified, this entry will also be simply referred to as TN.
). If this revealed status is
If the condition is not specified, it will be rejected.
The final message is "NAK/TN error",
The above two types of rejection messages are also
It is retrieved from the response directory in Figure 8. Ste
If the status is "Ready to receive", then
Another determination will be made. This other judgment is "input overlap".
This judgment has already been explained.
As shown in Figure 13A, the input/output management buffer
Inside section 170, the GET address
This is done by comparing the address and the PUT address.
be called. Furthermore, the transaction number,
Is the value of Received Message Count not zero?
the count value is zero.
If there is, it will also display input overruns.
-ing An overrun condition exists
In this case, “NAK/input overrun” is sent.
and the message is rejected. If all the above conditions are satisfied,
From the response directory in HSRAM26″
The “ACK” message (back confirmation response message) is
data is exported and sent out onto the network, where it can be accessed by other
There is a possibility that priority will be disputed with Setsa Mojiyur.
It becomes. Those other processor modules
In the same way, for received messages,
Some may have sent a positive response. child
At this point, if the common response received from the network is
message (this "common" means merged
) is the "ACK" message,
Therefore, it is selected as the receiving processor module.
``All'' processor modules that have been
be able to accept messages received on
If specified, the received message
acceptance will be made. If this response is "ACK"
If the format is any other than
will be rejected by ``all'' processors. In this specific example of reception and response
after the primary message is received.
, all processors respond with ACK and NAK responses.
response, and one of the NAP responses.
I want to be noticed for what I do. The processor uses these
If you receive one of the response messages of
If so, immediately after that, the primary message
transmission can be attempted. (The processor
transmission attempts through the network.
is equal to or less than the total waiting time of
It can also be done after a larger delay, and
This has already been explained in the ``Active Logic Nodes'' chapter.
(as explained). I got your attention one more time.
The problem is that if several processors
If you send the “identical” message, the result will be
all of those messages are on the network
It is possible that you have won out over the competition.
That's what I mean. In that case, those transmission
“All” of Rosetsusa will receive an ACK response
Become. This will be explained in detail in the specific example below.
Broadcast (simultaneous transmission) and global sema
This is important regarding the operation of the FO mode. This is an example of the present invention actually used.
In addition to those described above, there are many more types
to perform various actions as well as respond to
It's summery. Figure 18 shows their responses and actions.
, LOCK, TN error, and overrun.
9 different pre-identified stages.
status level, and acknowledgment (ACK) and
and for non-applicable processor responses.
Each item is shown in a column. A processor module sends a message.
When you have completed the preparations for the
The PTN value stored in the star 206 can be used.
state and therefore what is needed is TN
The status is "Ready to Send"
Just a confirmation. As you can see from Figure 12,
The entry (description) “Ready for communication” is
Next Message Vector for Sage
Contains the address. The assembled output
The power message is sent out over the network and then
If you lose the competition, the PTN will change midway.
This send operation will continue until the transmission is successful unless changed.
The operation is iterated and receives a response if successful
It turns out. The transmission was successful and a response was received.
If so, the address vector is changed. nex
The message vector is currently in the message.
taken from the second word (Figure 21A) of
, this word is the send transaction vector.
Random access method from taakunta 222
The data is transferred to memory 168. Output message section
If the system is not in overrun, the PUT cowl will
The counter 175 is advanced by “1” and this overlap
state is caused by PUT being equal to GET.
will be displayed. In addition, the sending transaction vector
Next message transferred from counter 222
The tsage vector is the current traffic vector in HSRAM.
By the execution number register 206
Specified transaction number add
input to the reply. If this new TN
If the status is “ready for communication”, this input is
The value of the vector is again
The next message related to identity
Pointing to the storage location of (Next Message)
ing. Output memory stored in HSRAM
For the format of the tsage, see Figure 21.
Please refer. However, when sending a message,
Management includes internal and external sources of PTN.
Many different forms of behavior, including modification
can be included. error condition,
Depending on the balun or lock condition, the system
The transaction number is set to “TN0”.
This shift allows you to keep the shift
will return the system to non-merge mode.
return and check the status on “TN0”.
A “ready to send” state is identified or
continues until a new TN assignment is made.
It becomes. It can be applied to quite complex concrete examples.
The first example shows the possible states and conditions.
Please refer to the flowchart in Figure 9 (Figure 19A).
sea bream. Example of output message completion buffer Message transmission completion is “LOCK”
by any other response message except
If specified, the newly completed output message
The pointer pointing to the buffer is the HSRAM
Output message completion circular buffer section
(See Figure 8). This pointer is
Indicates the address of the output message buffer above.
It's just a 16-bit word. (Output message
The format of the page buffer is shown in Figure 21.
It is. The output message buffer includes
record the response messages received from the network
(note the location is included). The output message completion circulation buffer is
network interface hardware 120;
A monitoring program placed on the microprocessor 105
It performs the function of communication with the program.
Ru. This microprocessor contains
The program that will output the message
is stored in HSRAM. This is followed by the following example
As explained in detail in
They are connected together in a chain, and at that time,
Let TN be the pointer to the beginning of this chain.
This allows you to work with
complex sequences can be formed. So
Another feature is that the network can be
Multiplexing, or time division, between
(This will also be explained in detail later)
), various locations in the network
Output messages in various orders depending on the event
be able to. Furthermore, the occupancy is determined by successfully transmitted packets.
Quickly reclaim storage space in HSRAM that was previously reserved.
and thereby remove that storage space from now on.
Can be reused for another output packet
It is important to do so. Output message complete
The complete circulation buffer fulfills this function. Successful transmission of a data message
If you receive a response other than a "lock" response
For example, the network interface is
Stored in "0510 (hexadecimal)" in RAM
Advance the PUT pointer (see Figure 10) by 1.
Also, the output metrics that this transmission has just completed.
PUT register address of first word of sage
Store to the address in the data. (PUT pointer value
is the TOP point stored in "0512 (hexadecimal)"
The PUT pointer becomes larger than the value of the PUT pointer.
BOT pointer stored in "0513 (hexadecimal)"
(=BTTOM pointer)
). PUT pointer is GET pointer
(storage location "0511 (hexadecimal)")
If so, the circulation buffer may have overrun.
Therefore, the "error interrupt" is
Generated towards chloroprocessusa. The software running inside the microprocessor
Depending on the software, the GET pointer may
The output message buffer is examined asynchronously.
It will be done. The processor does whatever it is asked to do.
After completing the process, set the GET pointer to "1"
(this GET value is greater than the TOP value)
(If the value becomes too high, it will be reset to the BOT value). GET
= PUT, it must be processed.
No output messages no longer exist. So
If not, yet another output message is created.
Since the transmission has been successfully completed, those
Output messages must be processed. This process
To do this, empty the HSRAM output buffer storage space.
This includes returning to the blank space, and therefore the lever
space can be reused for other packets.
It can be done. The important thing to note here is that the output
Message completion cycle and input message cycle
Batsuhua are separate from each other and therefore
These two circulation buffers each have separate
PUT, GET, TOP, and BOT pointers
This means that they are managed. configuration of
Depending on the method, as shown in Figure 13,
Then, both of these circular buffers become circular buffers.
It is also possible to share the management hardware 170.
However, such a configuration is not required. Initial Setup Procedure Each processor module is
SaMojiur's own high-speed random access
Accessing TN inside memory 168 (Figure 13)
This memory 168 has a function to
of potentially available TNs, that day
Contains a directory. However, if assigned
A TN that is not associated with that TN
Transaction number stored in storage location
The value clearly indicates that it has not been allocated.
It is shown. Therefore, the microprocessor
Stem 103 is an unallocated transaction.
Identify the numbers and among them
one for a given transaction identity
With respect to other processors and modules
Select to use to initiate communication.
I can do it. The transaction number is local
Chloroprocessor (= in the processor module
localized under the control of a microprocessor).
applied and updated, but not all in the network.
Global control in the area is based on the “TN abandonment order” and
A primary control message called “TN assignment instruction”
This is done using a zigzag. Can request the same TN
Multiple processor modules potentially competing with each other
A deadlock condition may occur during the session.
The reason for this is that the network
For processors with smaller numbers,
This is because it gives priority. Trying to get that TN
did not get priority among the processors that
The remaining processors respond with “NAK/TN error”
This response will be sent to those professionals.
Unless Setsa tries to secure another TN
This indicates that this is not the case. obey
and those transaction identities.
Securing and verification of data within the system and centrally
You have complete flexibility when doing it locally.
It is being What I would like you to pay attention to is the repeated use of TN.
The basic transmission mode is “TN0” and the
To shift between merge modes greater than
This means that it is being carried out accordingly. accordingly
This system requires only one TN broadcast
The transmission of the
The nature of its movement can also be changed. Further information for communicating changes in global status.
Another and particularly useful scheme is with respect to FIG.
This is the forced parity error propagation described earlier.
Ru. This unique display method is unique during other transmissions.
An aborted system is transmitted if it is interleaved.
system resources are examined and appropriate action is taken.
That will happen. Processor-to-processor communication There are two special forms of processor communication.
One is a specific forwarding protocol.
The communication is directed towards Setsa, and the other is
Transfer multiple processors belonging to one class
This is a communication carried out as follows. Both of these types
All transmissions use DSW, and
Both of these transmissions are in non-merge mode
Broadcast. In particular, one source processor and one destination processor
When communicating with Rosetsusa, use the DSW
The destination processor identification information (destination
processor identification: DPID)
do. To explain with reference to Figure 8, this
Each receiving processor module uses the DPID value.
The selection map part of Yule's HSRAM26'' is activated.
address, the specific address it is intended to be forwarded to.
Only the processor module gives a non-deterministic response.
occur and accept the message. The back-determined response is
sent, and it is finally successfully received.
If the requested
is ready to perform any of its future operations.
Ru. A certain message is sent to a certain control program.
multiple processes belonging to one class that are related to
If Rosetsusa should receive, Matsu in DSW
By pnibble and mapp address, H.
The corresponding section in the selection map part of S.RAM
Yon is specified. And all receiving processes
sends acknowledgments to each, and those acknowledgments.
to reach the source processor module.
The round-trip transmission and reception for this communication is the final
It will continue until it is completed. Processor communication in global broadcast mode
is the primary data message, status
message, control message, and response message.
It can be used to communicate each message.
can. Priority protocols and
network with features that allow for
Depending on your ability, you can send messages from that species to other species.
can be easily inserted into a sequence of similar messages.
I'm starting to be able to do it. Processor selection for hashing mode is
data in a national database system.
When performing data processing tasks,
This is by far the most frequently used processor selection method. one
Secondary data (=main data not for backup)
data), disjoint (= identical elements)
multiple data subsets (not shared) and
Multiple disjoint data for tuple data
The subsets are determined differently according to an appropriate algorithm.
The data is distributed among multiple secondary storage devices.
One processor separates a subset of primary data.
A separate processor handles backup data.
Because they share a subset of data, those two
If the processors respond simultaneously, the primary data
Messages about data are given priority.
It will be done. To ensure that this condition is covered
is the higher priority command code (first
(See Figure 2). data
Maintaining the reliability and integrity of the base is also
By taking advantage of the multiprocessor mode
be achieved, depending on the particular circumstances that arise.
those modes are applied in the most advantageous way
It will be done. For example, some parts of primary data
If the secondary storage device that shares the subsets fails,
In some cases, special processor-to-processor communication may be used.
You can update it using error again
correction or rollback of part of the database
in a similar way, or in class mode
This can be done by operating with
Ru. Example of transaction number The concept of transaction number
New for controlling multiprocessor systems
A powerful hardware mechanism has been obtained.
In this system, transaction number
BA constitutes a "global semaphore", and
Send and receive messages to and from the network, and
For a given data distributed among several processors,
In each case of checking the readiness status of the school,
plays an important role. Transaction number (TN) is HS
Physically as a 16-bit word in RAM 26
has been realized. This word has various functions.
To achieve this, please use the format shown in Figure 12.
It is said to be Tsuto. TN is stored in HSRAM
The microprocessor 105 and network
Access from any of the Desk Interface 120
can be accessed. Global semaphore The term ``semaphore'' is a term used in computer science.
In the related literature,
points to variables used to control multiple processes
came to be commonly used as a term for
It's on. Semaphore is an uninterrupted one
“Test and set” it in one step.
It has the property of being able to As an example, "Unassigned"
(UNASSIGNED: The status has not been assigned.)
“Assigned” and “ASSIGNED”
It can take two states:
Let's consider semaphore variables. this
In this case, the test-and-set behavior is as follows:
Defined as: If the semaphore is "unassigned"
If the semaphore is in the "assigned" state,
INDIA” status to indicate success;
On the other hand, if the semaphore is already in the "assigned" state,
If so, set the semaphore to the "assigned" state.
Leave it as it is and display "Failed". obey
According to this semapho, the semapho test/
A process that successfully completes and sets its own task.
While you can proceed with it, the failed process
, the semaphore is returned to the "unassigned" state.
Either wait for it to be set or use another equivalent resource.
Test another semaphore that is controlling the source.
or try to set the
It is done without ceremony. Although it is easy to understand,
If the test and set operation is interrupted,
If such a thing is possible, there are two ways to do it.
There is a possibility of accessing the same resource at the same time.
This may result in unforeseen mistakes.
There may be consequences. Any multiprocessor system
To control access to system resources,
Concepts that can be equated with hardware
It is actually materialized by air. But long
In the conventional system, one copy of semaphore (=
A semaphore with one copy, that is, a semaphore that is set up in only one place.
(Semaphore) can only be maintained. So
Here, multiple copy semaphore (= semaphore with multiple copies)
Mafuo, i.e. semafuo set up in multiple locations)
maintain one copy on each processor.
If you do this, you can create a semaphore just for testing.
Reduce the number of times there is contention for access
multivalent for this purpose and other uses described later.
Both with the purpose of using the semaphore variable of
desirable for. The problem is that the large number of semaphore
Completely synchronized operations must be performed on
If this is not followed,
If so, semaphore is used to strengthen it.
Complete access to resources where provided.
Integrity will be lost. Multi-copy semaphore, or "global" semaphore
is provided by this system. Shown below
Tables can control global semaphore behavior with a single semaphore.
This is in contrast to Huo (1 copy of Semapho).
Ru.

【table】

[Table] In the system of this embodiment, the "TN assignment (ASSIGN TN)" command and the "TN abandonment (RELIN-QUISH TN)" command are used to test transaction numbers used as global semaphore. They each have an and set function and a reset function. Referring to Figure 12, a "NAK/TN error" response indicates a failure, while a "SACK/assign" response indicates a failure.
The response shows success. The characteristics of this network include the synchronous clocking method used to clock multiple nodes synchronously, and the broadcast operation that transmits the highest priority packet to all processors simultaneously. It forms the basis for the actual realization of concepts. Because this concept is implemented, the system controls the allocation, deallocation, and access of multiple copies of a desired system resource by simply attaching a TN to that resource. This can now be done by What is important to note here is that control of distributed resources can now be performed with approximately the same small amount of software overhead as with a single semaphore. This is a significant improvement over traditional systems, which either cannot manage distributed resources or require complex software protocols and create hardware networks. This is because it will either end up happening. Readiness status "BUSY", "WAITING", "READY" (ready for transmission and reception completed), "DONE", and "Non-involved processor (NON-)"
A set of values (12th
(see figure) provides the ability to quickly check the readiness status of a task assigned a certain TN. In this system, the meaning of each of the above states is as shown in the table below.

[Table] Using the "TN assignment" command, assign
TN is now assigned dynamically. A success indication (a "SACK/Assign" response to a "TN Assign" message) indicates that all operational processors have successfully assigned the TN to the task. It should be noted with respect to Figure 11 that the "NAK/TN Error" response has a high priority (small value) so that either processor's network interface 120 detects a conflict regarding the use of the TN. If so, all processors will receive a failure response. Additionally, the OPID (Originating Processor ID) of this failure response transmitted over the network.
The field will display the first processor (the one with the lowest assigned number) among the processors that caused the collision. This fact is utilized in diagnostic routines. Each processor uses software to process tasks, and to “visi” the TN.
The appropriate one of "waiting,""superstitionready,""receivingready,""end," or "non-participating processor" is set. Any processor, including the one that issued the first TN assignment, can issue a ``Status Request'' at any time.
By issuing a command or a "start merge" command, it is possible to easily check the status of the task (TN) to what extent it has been completed. A "status request" is equivalent to a single test of a multivalued global semaphore. As can be seen from Figure 11,
The status response (SACK) message with the highest priority wins the competition on the network, resulting in the lowest readiness status being displayed. Furthermore, the OPID field will display the identity of the first processor (the one with the lowest number) among the processors in the lowest readiness state. This latter characteristic can be used to "wait" for the completion of tasks distributed among multiple processors.
A "non-bysy" format is defined. The processor that first issued the ``TN allocation'' is said to be the first ``wait master.'' This processor then designates some other processor as the new "wait master" based on arbitrary criteria. Once this new ``weight master'' has reached the desired state of readiness, it will notify all processors by issuing either a ``begin merge'' or a ``status request.'' Make inquiries. If all other processors are in the standard completion state, SACK will indicate this. If some processors are still not ready, the SACK response
The OPID field will display the first of the least ready processors. The ``Weight Master'' commands its processor to become the new ``Weight Master.'' Eventually, all processors will reach the ready state, but until then the system simply attempts to query the status each time it is notified that at least one processor has reached the ready state. It is. The system is thus not burdened with periodic status queries that consume resources without producing results. Additionally, this scheme ensures that the system knows that all processors have completed their work at the exact time the last completed process ends. As will be understood by those skilled in the art, a wide variety of other forms of "waiting" may be employed within the scope of the inventive concept. The "Start Merge" command is a special type of test-and-set instruction. If the status of the global semaphore is ``Ready to Send'' or ``Ready to Receive,'' then the current transaction number register (PTNR) 206
(see FIG. 13) is set to the value of the transaction number in the "start merge" message (see FIG. 3), thereby setting the PTNR register. If any of the active processors are in a lower readiness state, the value of PTNR is unchanged. The ``stop merge'' command is a reset operation corresponding to the above operation, and unconditionally resets the PTNR of all operating processors to ``TNO.'' As explained below, the current global task specified by PTNR
Only messages related to globaltask are output from network interface 120. Therefore, the ``Start Merge'' and ``Stop Merge'' commands provide the ability to time multiplex the network between multiple tasks. These tasks can then be stopped and/or resumed at will. An important detailed feature of the present invention is that the network interface 120 allows access to the TN by commands from the network and access to the TN by the microprocessor 105.
There are some things that I try to never do at the same time. In this embodiment, this is accomplished by a signal being sent from the receive state control circuit 260 to the read/write state control circuit 270, which signals the network that may change the TN. It is always in the "affirmative" state when a command from is being processed.
During the short time that this signal is in the "affirm" state,
The processor is prohibited by control circuit 270 from accessing the HSRAM. As will be appreciated by those skilled in the art, a wide variety of alternative configurations may be employed in lieu of the above configurations without departing from the scope of the present invention. Reception Control A further function of the TN is the control of incoming messages. By using the "TN Assign" command, input message streams at multiple processors can be associated for a given task. The TN assigned to the task in a given processor is "ready to receive"
When the TN is set to
A count value representing the number of packets that the processor is ready to accept is also displayed (FIG. 12). Network interface 1
20 decrements this count value each time it successfully receives an individual packet (this decrement is done by subtracting ``1'' arithmetically from the word of TN); This continues until the value reaches zero. When the count value reaches zero, a "NACK/overrun" response is generated, which tells the processor sending the packet that the processor issuing the NACK response is ready to accept more input packets. You will be informed that you will have to wait until it is available.
Furthermore, as can be seen from FIG. 18, at this time, PTNR is also reset to "TNO". The above operating mechanism allows direct control of the flow of packets flowing through the network. It also ensures that a single processor is not overwhelmed with unprocessed packets and that the processor does not become a bottleneck for the system. Transmission Control To explain Figure 21A, as can be seen from the figure, each message stored in HSRAM is assigned a new TN vector (=Next Message
contains a field to accommodate the value of the vector). Once you have sent a message and successfully received a response to it, the new TN vector contained in the message you just sent is now H.
Stored (transferred from PTNR) to the address for storing the current transaction number in S.RAM. Therefore, the TN is updated each time an individual message is sent, and it is possible to automatically set the TN to the desired state when a message is successfully transmitted. There is. To explain Fig. 12, "Send preparation complete"
The TN format is 14-bit HSRAM
This address is used to point to the next packet to be output for a given task (TN). Therefore,
The TN stored in HSRAM also serves as a head pointer to the beginning of a first-in-first-out (FIFO) queue of messages for various tasks. Therefore, as far as a given task (TN) is concerned, each processor will attempt to send packets in the order determined by the chain of new TN vectors. By combining it with the mechanism for high-speed network multiplexing (multiplexing) between multiple TNs (tasks), as explained earlier,
It is clear that many sets of complex combinations of tasks distributed among many processors can be managed with very little software overhead. The structure provided by the collaboration of networks, interfaces, and processors allows copies to be distributed among hundreds or even thousands of processors. This is a preferred configuration for allocating and deallocating resources, suspending and resuming tasks, and performing other controls over resources and tasks that can be distributed. Example of DSW (Destination Selection Word) The Destination Selection Word (Figure 3) is used for DSW logic 190 (Figure 13) and HSRAM 26 (Figure 8).
By collaborating with the DSW section of
It provides multiple modes that allow you to: That is, these modes are those in which the network interface 120 of each receiving processor intends that messages being received be processed by the microprocessor 105 associated with that network interface. These are multiple modes that allow you to quickly make a decision as to whether or not something has happened. As already explained, the message contained in the received message
The DSW selects and compares the nibble stored in the DSW section of HSRAM. Processor Address As shown in Figure 8, the HSRAM
One portion of the DSW section is dedicated to storing processor address select nibbles. In this system, each of the 1024 processors that can be mounted is associated with one of the bit addresses contained in this portion of HSRAM. The bit of the bit address associated with the ID (identity) of the processor is set to "1", while all other bits in this section are set to "0". Therefore, each processor has only one bit in this section set to "1". Hash Maps Another portion of the DSW section of HSRAM is devoted to storing hash maps. In this system, two of the map selection bits are applied to those hash maps, resulting in two complete sets containing all 4096 possible values. In hashedmode, keys for records stored in secondary storage are set according to a hashing algorithm, which assigns a "bucket" between 0 and 4095. It is done. A processor in charge of a record contained in a given bucket has a bit set to 1 in the map bit whose address corresponds to the bucket number of that bucket. . Other bits are set to "0". A given processor can be responsible for multiple buckets by simply setting multiple map bits. In the configuration of this embodiment, as is easily understood, the map bits can be set in the following manner. That is, for a given map selection bit, each bit address is set to ``1'' in only one processor, and any bit address is always set to ``1'' in one processor. This method is set to "1" at As a direct result of adopting this method, each processor (AMP)
The system is designed to provide distinct and disjoint subsets of records in the database, yet for the system as a whole there is a complete set that includes all of the records. Although the above examples are explained using the relational database problem as an example, those skilled in the art will readily understand that disjoint subsets of the problem can be The same method can be applied to any problem area that can be assigned to individual processors. Yet another thing worth noting is that by having two complete maps, the scheme described above can be used to convert the buckets that are assigned to a given processor according to one map to the buckets assigned to a given processor according to the other map. This means that the map can be configured so that it can be assigned to a different processor. Now, if we say that one map is "primary" and the other map is "backup", then the direct consequence is that a record that is temporary on a given processor will be It can be ensured that it is backed up on another processor. Furthermore, there are no restrictions on the number of processors that can back up a given processor. As will be understood by those skilled in the art, the number of distinct maps that can be implemented within the scope of the present invention can be greater than two, and the number of buckets can be any number. Class In both the processor address and hash map cases described above, if we examine a given bit address for all processors, we can determine that the bit address is ``1'' only in one processor. It can be seen that the corresponding bit address in all other processors is set to "0".
However, it is also possible and useful to have corresponding bit addresses set to ``1'' in multiple processors. This method is called the "class address" mode. A class address can be thought of as the name of a procedure or function, copies of which exist in multiple processors. All processors equipped with the corresponding processing procedure or function have a "1" bit set in the corresponding bit address. To send a message to a class address, the appropriate class address in the DSW (Figure 3) is set. All operational processors that are indicated as ``belonging'' to the class by having a bit set to ``1'' in the appropriate location in HSRAM will - It will respond to the packet with "ACK". Processors that do not belong to the relevant class respond with NAP. DSW therefore allows the routing calculations necessary to control the flow of messages within a multiprocessor system to be performed by hardware. Also, the program can be made independent of knowledge of which processor contains the various functions of the system. Furthermore, because the map is part of the HSRAM and therefore accessible to the microprocessor 105, it is possible to dynamically relocate certain functions from one processor to another. Example of merging In a complex multiprocessor system, performing a series of multiple, interrelated operations
May be required by the task. This is especially true for relational database systems that handle complex queries, where data is assembled into files,
Moreover, references to multiple secondary storage devices may be required to form a file that, once assembled, can be redistributed to multiple processors in a particular manner. The example shown below is
The systems in Figures 1, 8, and 13 are TN
This article briefly explains how such functions can be easily performed by manipulating the DSW and the global semaphore. First of all, the merge coordinator (typically the merge coordinator is IFP14
to 16, but are not necessarily limited to AMPs belonging to one class that will be formed by merging one file (i.e., acting as a data source).
(among AMPs 18 to 23). One unassigned TN is selected and assigned to identify the data source function. A second step is to distribute or hash this file to another set of AMPs (which may be processors of the original data source).
A separate TN, which had not been allocated up to that point, is assigned to the main function of the TN. The coordinator for this merging function uses DSW to identify a plurality of processors belonging to a class that will perform merging of files related to the first TN. The participating processors involved in this merging task are
Increase the level of TN's status to "bizui" or "waiting" status,
Thereafter, control of the merge operation is passed to one of the participating processors involved in the merge operation (ie, the job of coordinator is delegated).
Each of the above plurality of participating processors (all other processor modules are non-participating processors with respect to their transaction numbers) receives a message packet regarding the merge task thus defined. After sending an acknowledgment, the processor proceeds with execution of its own subtasks, updating its status level accordingly. Then, once the processor to which the merge coordinator task has been delegated has completed its own task, it will notify all other participating processors of the status regarding that transaction number.
A status request may be sent and a response may be received indicating the least readiness of the participating processors. Control of the merge operation is passed to the processor with the lowest readiness state, after which
This processor will be able to poll all other participating processors when it has finished its work. The above process can be allowed to continue, if necessary, until a response is received indicating that all participating processors are ready. The processor acting as a coordinator at the time such a response is received then begins forwarding the message to the HSRAM 26, utilizing the DSW to identify the participating processors that belong to the class in question. As the message is transferred, the status level is updated to "ready to send" based on the corresponding output message vector information. If the subsequent polling shows that all participating AMPs are ready to transmit, the coordinator issues a merge start command for that particular TN. While a merge operation is being performed, processed data packets are directed and forwarded to multiple processor modules belonging to one class for distributing the results to secondary storage according to the relational database. will be done. Regardless of whether or not these multiple receiving processors are the same as the multiple processors that are the source at this time, the participating processors (i.e., the above-mentioned receiving processors) belonging to the class involved in this distribution
is identified by the DSW, and its transaction is identified by the new TN. This new TN will be assigned to all participating processors involved in this new transaction, and those participating processors will be
Their readiness level is increased to make them "ready for reception." This DSW
may be a hashing selection specification rather than a class specification, but in either case all participating processors must be able to receive the message being broadcast while the merge is being performed. It is placed. "Start merging"
is issued, a plurality of message packets are sent out onto the network simultaneously from each of the sending processors that are to be involved in the sending operation, and the message packets are sent out onto the network simultaneously. Priority determination is performed dynamically (=during transmission). Once each sending participating processor has completed sending its own set of messages, each sending participating processor has an ``end'' that is defined in some form.
An attempt is made to send an "End of file" message, which has lower priority than various data messages. All of the involved processors
This "end-of-file" message continues to lose out to data messages until it starts sending out "file" messages, and only after all participating processors have sent out "end-of-file" messages. , the transfer of an "end-of-fail" message is accomplished. Once this transfer is achieved, the coordinator sends an "End of merge" message and can also subsequently perform a "TN abandonment", which This transaction ends. Overrun, error, or locked conditions can be appropriately handled by merging or starting the transmission over again. Once the merge operation for a TN is complete, the system can shift to the next TN in the sequence of TNs.
Once each processor module has created a queue for multiple message packets that correspond to this new TN,
The module is then able to restart its approach to the network to perform the merge operation. In addition to the individually executed in-processor merge operations, this efficient use of intra-network merge operations makes this system a significant improvement over previous systems in terms of very large scale performance. It is now possible to perform sort/merge tasks. When the present invention is adopted, the time required to sort one file in the system can be expressed by the following formula when the number of records is n and the number of processors is m. . C ₁ n/m log ₂ n/m + C ₂ n In this equation, C ₂ is a constant and for this example is estimated to be approximately 10 microseconds if a 100 byte message is used;
C ₁ is a constant estimated to be approximately 1 millisecond if a typical 16-bit microprocessor is used. Approximate sort/merge times in seconds for various combinations of n and m are shown in the following table, assuming 100-byte records are used. be.

[Table] It is not easy to compare and evaluate the numbers of the specific examples shown in the table above with conventional systems. The reason for this is that two types of interrelated sorting processing sequences (sorting by the processor and sorting by the network) are involved, and also because there are almost no systems that have this capability in the first place. It is. Furthermore,
In contrast to this system, which sorts and merges messages that are long and variable in length,
Many general sorting abilities are evaluated for several bytes or several words. Another important factor is that the present system is a multiprocessor itself and is not a dedicated system for sort/merge processing.
The system can shift locally and globally between merge and non-merge operations with complete flexibility, and does so without any software penalty. This can be done without any problems or losses in system efficiency. Example of a Task Request/Task Response Cycle Referring to FIG. 1, each of the processors 14, 16, or 18-23 connected to the network 50 is configured to perform tasks for one or more other processors. task request,
It has the function of forming messages in the appropriate format in the form of message packets. In relational database systems, most of these tasks are performed by the host computer 10,
12 and input into the system via interface processors 14 and 16, although this is not a requirement. This message packet, formed in the appropriate format, is entered into competition on the network with packets from other processors, and the priority levels of other tasks and operations on this processor are determined. Depending on the level of your condition, you may sometimes get priority. A task may have its contents specified by a single message packet or by multiple continuation packets, but subsequent continuation packets do not contain data messages. It is assigned a relatively high priority level within the group (see FIG. 11), thereby ensuring that the delay in receiving subsequent parts is as short as possible. A message packet includes transaction identity (=transaction identification information) in the form of a transaction number. This transaction number distinguishes between non-merge mode, or default mode (``TNO''), which is the mode for extracting processing results, and merge mode (all TNs other than ``TNO''). , which inherently has the property of making distinctions according to selection. Additionally, the message packet contains a DSW. this
The DSW essentially specifies the destination processor and the mode of multiprocessor operation, and this specification can be made by specifying a particular processor, a class of multiple processors, or hashing. In this embodiment, the hashing is to a portion of the relational database. A message packet broadcast to a target processor (designated forwarding destination processor) via the network 50 is locally accepted by that processor (i.e., if the processor determines that acceptance by itself is appropriate). (by the processor itself) and acknowledgment of receipt is performed by an acknowledgment (ACK). All of the processors 14, 16 and 18 to 23 are
Following the EOM (End of Message), responses are sent simultaneously to the network 50, however, the ACK sent from the designated destination processor gains priority and is not received by the originating processor. That will happen. Next, the designated transfer destination processor stores the sent message in local HSRAM (=HSRAM provided in each processor module).
and the interface 120 (Figs. 8 and 13)
When the request packet (= sent message) is transferred to the local microprocessor via the without). When tasks involving relational databases are performed, the DSW typically specifies some disjoint subset of data that is stored on disk drives for that subset. However, sometimes tasks are performed that do not require reference to a stored database. Specific operations or algorithms may be executed by individual processors, and if multiple processors are designated as destination processors, each of those processors may perform disjoint processing of the entire task. It can be configured to perform work on a subset. The variable length message packet is configured such that the request message specifies the operation to be performed and the file to be referenced in the database system. It should be noted here that there may be a large number of message packets related to a given task, in which case the sorting discrimination performed within the network Key fields that can be optionally adopted to provide appropriate characteristics as a standard (Figure 3)
is becoming important. The task response packets generated by each processor attempting to respond are transferred from the microprocessor via control logic 28 of FIG. 1 to local HSRAM 26, where they are
The task response packet is stored in the outgoing message format of Figure 21A. If the task response requires the use of continuation packets, such continuation packets are sent out following the initial packet, but given higher priority for continuation. Ru. If the system is operating in merge mode and each processor is generating a large number of packets related to a certain transaction number, the packets are first localized (=individual processors (internally) in a sort order, and then by merging on the network 50, it can be arranged in a global sort order. The task result packet is sent to processors 14 and 16.
and 18-23 to network 50 in simultaneous packets, and one highest priority message packet is broadcast back to all processors after a predetermined network delay. Depending on the nature of the task, these task result packets may be forwarded to the source processor that originally sent the request message, or to one or more other processors. Furthermore, the transfer can be performed in any of the plurality of multiprocessor modes described above. The most common case in relational database systems is to use hashing to select the forwarding destination,
This means that merging and redistribution are performed at the same time. Therefore, as can be understood from this,
In the "task request/task response" cycle, each processor can act as a source processor, a coordinator processor, or a responder processor; It is also now possible to operate as both. Since many "task request/task response" cycles are involved, processors 14, 16 and 1
8-23 and network 50 are multiplexed among their tasks, but this multiplexing is done on a time basis as well as on a priority basis. Examples of Complex Queries In relational database systems, host computers 10, 12 are used to further define tuples and disjoint data subsets of primary and backup data. Complex queries are routed from host computer 10 or 12 via IFP 14 or 16 using a distribution method that distributes the relational database among multiple disk drives 38-43 according to a input into the system. The message packet of this input query is first sent to the IFP.
14 or 16, and this analysis is performed to convert the message from the host computer into a plurality of task requests for requesting the AMPs 18 to 23 to perform tasks. It is something. At the beginning of its operation, an IFP 14-16 sends out request packets to retrieve information from one or more specific AMPs, thereby providing information necessary for further analysis of messages from the host computer. In some cases, it may be necessary to obtain internal system data. Once we have the data we need to process the request from the host computer,
The IFPs 14-16 may perform several "task request/task response" cycles with the AMPs 18-23, and may also actually process the data and respond to requests from the host computer. can be satisfied. In the above processing sequence, the tasks listed above
A cycle of requests and task responses is used, and the cycle can continue for any length. IFPs 14-16 then communicate with the host computer via the IFP interface. This response to the host computer may simply be to provide the data that host computer 10 or 12 needs to generate the next complex query. (Independent Multiprocessor System) The basic embodiment of the system according to the invention described above in connection with FIG. This is an example of a back-end processor that can be used in combination. However, as already mentioned, the present invention is useful in a wide variety of processing applications, and particularly in those types of processing applications where processing tasks can be easily subdivided and distributed without the need for large amounts of central processing power. , which has particular advantages. 20th
The figure illustrates one embodiment of a simple configuration of a stand-alone multiprocessor system according to the present invention. In FIG. 20, a plurality of processors 300 all connect to an active logic network 3 via an interface 302.
04, this network is similar to that already described. An active logic network 304 with redundancy may be employed to enhance data integrity. In this embodiment as well, a 16-bit microprocessor chip can be used for the processor 300, and a main RAM memory of sufficient capacity can be incorporated. This diagram shows nine processors 300.
Only one processor is shown, and each of the processors has a different type of peripheral connected to it, to demonstrate the versatility of the system. In practice, the system becomes much more efficient by having more processors on the network, but even with a relatively small number of processors, the reliability of the system can be improved. A particular advantage is obtained in terms of data integrity. In this embodiment, a plurality of processors 30
0 can be physically separated from each other by a sufficient distance without inconvenience, such that the maximum separation between nodes is 28 feet (5.5 m), it is important to install and use multiple processors in large arrays on one floor or several adjacent floors of a building to avoid unnecessary crowding. This is because it can be done. In stand-alone systems, much more variety is used in the peripheral controllers, as well as the peripherals themselves, than in the post-processor embodiments described above. Here, for convenience,
It is assumed that each input/output device is connected to a separate processor. For example, an input/output terminal device 310 including a keyboard 312 and a display 314 is connected to a processor 3 for the terminal device 310 via a terminal controller 320.
Connected to 00. However, in the case of terminal devices operating at relatively slow speeds, it is not impossible to control a fairly large network of terminal devices with a single 16-bit processor. The illustrated input/output terminal device is merely one example of how a manually operated input processing device, such as a manually operated keyboard, may be connected to the system. This terminal device 310 can also be configured as a word processor by utilizing the processing power of the processor 300, and this word processor can be configured as a word processor.
It may also be possible to communicate with databases, other word processors, or various output devices via network 304. A large capacity secondary storage device, such as a rigid disk drive 322, may be connected to a processor for that storage device via a disk controller 324. Also, as is easily understood,
Larger systems may use more disk drives or different forms of mass storage. printer 32
6 and output devices such as plotter 330, respectively.
It interfaces to processor 300 for those output devices via printer controller 328 and plotter controller 332. Interaction with other systems (not shown) occurs via communications controller 338 and via communications system 336 .
For example, a teletype network (TTY) or one of the larger networks (eg Ethernet) can be used. Some of the processors 300
Simply network 3 without connecting peripherals
04 (not shown). Bidirectional data transfer may take place in the tape drive 34.
0 and tape drive controller 342, if used, plus controller 34
Floppy disk drive 3 with 6 connected
44 is used. In general, tape drives not only provide large storage capacities when used online, but can also be used for backup of disk drives. For this backup purpose, tape is used to save data stored up to a certain point in a sealed rigid disk device.
Because such backup operations are typically performed during periods of low load (eg, nights or weekends), network 304 can be used to perform long "streaming" transfers. Furthermore,
Because the floppy disk drive 344 may be used to input programs during initial system setup, some of your network usage time should be devoted to this "streaming" mode. It can also transfer considerable amounts of data. Optical character reader 350 serves as yet another source of input data, which input data is input to controller 352.
input into the system via Note that the peripheral devices simply labeled as "other devices 354" can be connected to the system via the controller 356 to provide other functions as necessary. It is. By sending respective message packets from separate processor modules simultaneously with each other and making a priority determination on the message packets, one or a common highest priority message packet is assigned a predetermined fixed number of message packets. It uses a method that simultaneously broadcasts to all processor modules within a time period of
Modules are now equally accessible. Prioritized transactions
This global semaphore system, which uses number and readiness indicators and forwarding selection entries included in messages, allows any processor to act as a controller; can operate in a hierarchical or non-hierarchical manner. It is also very important that the system can be expanded or contracted without requiring software scrutiny or changes. Even if access is required to a message that is considerably longer than the message lengths already discussed, but which is still relatively limited in length, such access can be performed. For example, for complex computer graphics equipment (not shown), access to only specific portions of a vast database is required to create elaborate two-dimensional and three-dimensional figures. There are cases. Also, with word processing systems, the slow operator speed may require only a small sequence of data from the database at a time. In these and similar situations, the system's ability to handle messages of variable length, as well as its ability to give priority to continuation messages, is beneficial. Situations that require intensive processing power or the transmission of extremely long messages limit the use of this system, but in other situations the system works to great advantage. do. Dynamic situations involving manipulation of a variety of different data formats and associated sorting or merging functions are all situations in which the present invention would be advantageous. Business decision-making, which involves collecting, collating, and analyzing complex data, is an example of such a situation, as is the creation and editing of video and graphical input for periodicals. This is an example. (Conclusion) As is obvious to those skilled in the art, the system shown in FIG. (up to a practical limit number to be determined). Furthermore, as is clear, the system shown in the figure is capable of checking the status of each processing device,
The need for administrative and overhead software for setting task and processor priorities and ensuring efficient utilization of processor processing power is greatly reduced. Obvious benefits are obtained for database systems and other systems where it is appropriate to subdivide a task into multiple subtasks that can be processed independently of each other. etc. For example, in the case of relational databases, even if the capacity of secondary storage increases significantly, additional databases need only be appropriately integrated into a data structure consisting of primary and backup data. be. In other words, it is possible to expand the network without limit, and this is possible because standardized intersection devices, or nodes, are connected in a binary evolving connection system. , because the functions performed on those individual nodes do not change due to the expansion. Furthermore, there is no need for a setting processing sequence or external control for the operation of the nodes. Therefore, when a system according to the present invention is connected to function as a back-end processor for one or more host computers as shown in FIG. without changing the operating system software or application software.
The database can be expanded (or contracted) arbitrarily. Host processor system (=
From the perspective of the host computer (host computer), this backend processor is ``transparent'' regardless of its configuration, because even if its configuration changes, the backend processor and host processor This is because there is no change in the manner of interaction with the system. To switch this backend processor to do the work of another host processor system, simply ensure that the IFP speaks appropriately to the new host processor system's channel or bus. good. Depending on the configuration of the network in one practical example, message transfer within the network 50 can be performed without significant delays or unreasonable delays due to contention between processors. Up to 1024 microprocessors can be contained in one array. The embodiments described herein are
It will be obvious to those skilled in the art how to expand to include more than 1024 processors. When using 1024 processors in one system, it is known that the maximum line length between active nodes is 28 feet in a practical example, and this line length poses problems when configuring an array. will not occur. The delay time due to the network is a constant time 2τN for any message, where τ is the byte clock interval and N is the number of layers in the hierarchy. Clearly, doubling the number of processors by adding one more layer only slightly increases the delay time. If it is a data message, it will almost inevitably be a long message (approximately
200 bytes long), and because the priority decisions for all competing messages are made while the data is being transferred along the network, this network is less effective than traditional systems. This allows data messages to be transferred with much higher efficiency. Among the important economic and operational features of the system is the fact that standardized active logic circuits are used to replace software and even firmware in network systems. There are some characteristics obtained by In other words, due to this fact, it is possible to use modern LSI and VLSI technology to create a highly reliable circuit at a relatively low cost compared to the overall cost including the cost of the processor and the cost of peripheral devices. It is now possible to incorporate it. The need to spend time and money on software is limited to critical areas such as those related to problem domain tasks such as database management. For example, the system configuration allows all functions necessary to maintain database integrity to be performed within the scope of the message packet configuration and network configuration. It's summery. polling,
Functions such as status changes and data recovery are performed internally to the system. Another important consideration is that the network of the present invention has high speed data transfer performance.
In some cases, it is so superior that it is comparable to the conventional ohmic wiring bus. Since multiple message packets are sent simultaneously and their priority is determined while they are being transmitted, in the conventional system, there is a This is because delays that were commonplace have been avoided. Furthermore, even if the number of processors is enormous, it is possible to keep the length of the connection structure between nodes below a predetermined length, so the propagation time within the bus becomes a constraint on the data transfer rate. Never. This system has been found to be near optimal in terms of microprocessor and network usage efficiency. The important thing in these respects is to ensure that all microprocessors are kept busy and that the network is fully utilized. The ``IFP-Network-AMP'' configuration effectively makes this possible, because microprocessors that lose out in the competition for priority for the message packets they send , it is only necessary to attempt the transmission again at the earliest suitable time, thereby maintaining the bus duty cycle at a high level. Fast random access memory also contributes to this effect, since it stores both the input message packets to be processed and the output message packets to be sent out. This is because each processor can always obtain a backlog of work, and the network can also obtain a backlog of message packets. When all input buffers are full, the processor sends an indication over the network to indicate this fact. Also, when the input buffer used by the IFP to receive messages from the host computer becomes full, an indication is sent out on the channel to notify this fact. The system is therefore self-paced both internally and externally. By utilizing the architecture and message configuration described above, this system is configured to perform many other functions required of a general-purpose multiprocessor system. There is. For example, in the prior art, great attention has been paid to methods for evaluating and monitoring changes in the status of global resources.
In contrast, according to the present invention, only a parity channel is provided and used as a means for communicating both the occurrence of a parity error and the fact that processor availability has changed. 1
When one or more processors shut down, the shutdown is propagated through the system at about the same time as it occurs, allowing interrupt sequences to begin executing. There is. Since a method is adopted in which multiple responses are sorted according to priority, it is possible to compare the nature of changes in global capacity when they occur. It has become possible to specify a much smaller circuit and system overhead. The global response obtained through priority determination with a single inquiry, which is achieved by employing global semaphore and active logic networks, has very deep systemic meaning. ing. By broadcasting queries in this manner, unambiguous, unambiguous global results are obtained, eliminating the need for complex software and overhead. Status setting operations such as distributed updates can be performed even when multiple simultaneous operations are being performed on different processors. Furthermore, by using the network, transaction number, and transfer destination selection word as described above, this system exhibits excellent ability to distribute work and collect processing results in a multiprocessor system. ing. Various multiprocessor modes and control messages are available, and various levels of priority can be easily set and changed simply by manipulating the priority protocol. There is. The ability to broadcast to all processors simultaneously, combined with the ability to sort messages across the network, makes it easy to broadcast to any processor group or any individual processor group or any individual processor. It is now possible to set the transfer destination as a transfer destination, and it is also possible to extract the processing results in an appropriate order. Thus, when a complex query is entered into a relational database system, it initiates any processing sequence necessary for database operation. A further advantage of the present system is that redundancy can be easily introduced into multiprocessor systems such as relational database systems. The dual networks and dual interfaces provide redundancy that allows the system to continue operating even if one network fails for any reason. Since the database is distributed into disjoint temporary subsets and backup subsets,
The probability of data loss is reduced to a minimum level. A variety of versatile control functions are available to maintain the integrity of the database in the event of failures or changes.

[Brief explanation of drawings]

FIG. 1 includes a new bidirectional network,
1 is a block diagram of a system according to the invention; FIG. Second
Figures 2A-2J are a series of successive chronological sequences illustrating the transmission of data and control signals in the network of the simple embodiment shown in Figure 1. It is an explanatory diagram,
FIG. 2 is a diagram showing the state before the start of signal transmission, and FIGS. 2A to 2J are respectively t
9 is a diagram corresponding to one of the time samples at ten consecutive points in time from t=0 to t=9. FIG. FIG. 3 is an explanatory diagram illustrating the structure of a message packet employed in the system shown in FIG. 1. Figure 4 shows the active logic used in the new bidirectional network shown in Figure 1.
FIG. 3 is a block diagram showing a more detailed structure of the same network in terms of nodes and clock circuits;
FIG. 5 is a state diagram illustrating various operating states within the active logic node. FIG. 6 is a timing diagram for explaining the end-of-message detection operation performed inside the active logic node. FIG. 7 is a timing waveform diagram for explaining the operation of the clock circuit shown in FIG. 4. FIG. 8 is a block diagram of a processor module containing high speed random access memory that may be used in the system shown in FIG. FIG. 9 is a diagram showing the internal address allocation status of the main RAM of the microprocessor system shown in FIG. 8. FIG. 10 shows the high-speed random access system shown in FIG.
FIG. 2 is a block diagram of how data is arranged within one reference portion of a memory. FIG. 11 is a chart showing the message priority protocol used in the system. FIG. 12 is an explanatory diagram illustrating the word format of a transaction number. 13 and 13A are block diagrams of interface circuits used in each processor module provided inside the system shown in FIGS. 1 and 8; 13A on the right side of the figure
It is a diagram that can be combined into one sheet by placing the figures.
FIG. 14 is a timing diagram illustrating various clock and phase waveforms used in the interface circuit of FIG. 13. FIG. 15 is a block diagram illustrating further details of the memory structure and one method of mapping for mapping based on destination selection words. FIG. 16 is a simplified flowchart showing the changes in status upon receiving an input data message. Figures 17 and 17
Figure A is a flowchart showing changes in status when a message is being received, and is a diagram that can be combined into one page by arranging Figure 17 in contact with the upper edge of Figure 17A. FIG. 18 illustrates the relationship between various primary messages and the various responses generated to them, as well as the relationships between various primary messages and the actions performed in response to them. This is a table showing 19 and 19A are flowcharts showing changes in status when a message is being sent, and FIG.
It is a figure which is connected to one sheet by arranging it in contact with the upper edge of the figure. FIG. 20 is a block diagram of a stand-alone system according to the present invention. FIG. 21, consisting of FIGS. 21A and 21B, is a diagram showing messages stored in the high speed random access memory. FIG. 22 is a simplified schematic diagram illustrating one possible distribution scheme for distributing respective portions of a database among a plurality of different processors within a database system. 10, 12... host computer, 14,
16...Interface processor, 18~
23...Access module processor, 2
4... Microprocessor, 26... High speed random access memory, 28... Control logic,
32...Disk controller, 38-43...
…disk drive, 50…active logic
Network structure, 54...node, 56...clock source, 120, 120'...network interface, 103...microprocessor system.

Claims (1)

[Scope of Claims] 1. Data from multiple data sources can be routed along a chain of nodes with zero time skew between data flows at each node.
A system for time-skewed transmission comprising a plurality of active circuits operable independently of each other arranged in a sequential array culminating in an apex node. nodes, the delay time in the connection between consecutive nodes is constant, and this connection is a connection that does not cause a delay time exceeding a predetermined maximum delay time, and the apex Master connected to the node
a clock source, a plurality of clock generation circuits operable independently of each other, each provided in a separate said node, each of said clock generation circuits having a frequency that is equal to the frequency of said master clock source; This circuit generates a clock signal that is substantially the same as the clock signal and whose control can be adjusted, and includes clock signal feedback means for connecting two consecutive nodes, and the clock signal feedback means generates a clock signal that is substantially the same as the clock signal from the successive adjacent node. Means for returning a clock signal to the source node that generated the clock signal, comprising error signal generating means provided in each of the nodes, and the error signal generating means is configured to return the clock signal from each of the clock generating circuits. Direct clock signal and
receiving a word clock signal obtained from a clock generation circuit of a node in a higher hierarchy adjacent to each of the nodes and the feedback clock signal; means connected to generate an error signal by comparing and contrasting the delay times of the clock generators, and controlling each of the clock generator circuits in response to the error signal, thereby controlling each of the clock generator circuits. maintaining a uniform temporal relationship with respect to said master clock. 2. The sequential array has a bidirectional tree structure, and data transmission is performed by message packets, and
The active circuit nodes are responsive to respective clock signals to bidirectionally synchronize message packets from the base of the tree structure, along the tree structure, and back to the base of the tree structure. Claim 1 comprising means for transmitting
System described. 3. Redividing the message packet sources connected to each node located at the base of the tree structure and the clock interval stored in each of those sources and applying a predetermined clock to that clock. 3. The system of claim 2 further comprising clock means for generating at least one further clock of higher frequency in phase relationship. 4. The system of claim 3, wherein said clock means for generating said clock signal at a higher frequency defines at least three signal phases within said clock interval. 5 Maintaining synchronization among messages from different message sources competing with each other in a network with nodes arranged in an array that converges on an apex node. A clocking system for clocking a clock signal of a given frequency connected to the apex node, wherein successive nodes of the plurality of nodes are connected with a fixed delay time, and the clock signal of a given frequency connected to the apex node is a plurality of independently controllable clock generation circuits each disposed in a separate node, each of the clock generation circuits having a frequency approximately equal to the frequency of the clock generation circuit; The circuit generates a signal equal to a given frequency, and includes clock signal feedback means for returning the clock signal from the next adjacent node to the source node that generated the clock signal in a convergence direction toward the apex node. , a local clock signal of the node provided in each of the nodes, a word clock signal obtained from a clock generation circuit of a node in a higher hierarchy adjacent to the node, and the feedback clock signal. an error signal generating means for generating an error signal by comparing the signals, and controlling each of the clock generating circuits in response to the error signal, thereby controlling all of the clock generating circuits to the master clock source. A clocking system comprising control means for maintaining a uniform temporal relationship between