JP2628811B2 - Task processing and message transmission / reception control method in a multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a task processing in a multiprocessor system and a method for controlling transmission and reception of messages between processors.

[0002]

2. Description of the Related Art Since the emergence of highly reliable electronic computers (electronic computers),
In addition to systems that have been considered by those skilled in the art, the use of a plurality of computers, which operate in a mutually related manner, allows the entirety of a given task to be completed. There is a system that is designed to be executed. In some of such multiprocessor systems, one large computer uses its superior speed and capacity to execute complex parts of a program, while performing low complexity tasks. And less urgent tasks are delegated (assigned) to smaller, slower satellite processors, thereby reducing the burden on the large computer and the amount of requests for the large computer. . In this case, the large computer is responsible for allocating subtasks, keeping the small processor (= the satellite processor) always active,
You must be responsible for verifying the availability and operating efficiency of these small processors and ensuring that they have unified results.

[0003] Among other types of multiprocessor systems adopting a different system from the above, some systems use a large number of processors and one common bus system, and the plurality of processors are essentially required. Some systems have functions that are equivalent to each other. Such systems often use a control computer or control system independent of the other parts to monitor the availability and processing power of the individual processors for a given subtask, and Tasks and information transfer paths are controlled. In some, the configuration and operation of each processor is set so that the processor itself can monitor the status and availability of other processors and determine the transfer path of messages and programs. . A significant drawback common to the various systems described above is that software is required and operating time is consumed to perform the overhead and maintenance functions, and thereby the performance of the intended purpose. Will be affected. The amount of work involved in determining and monitoring the transfer path increases with a quadratic function of the total number of processors involved in those tasks, eventually leading to inadequate effort being spent for overhead functions. There is also.

[0004] The following several patent publications show examples of the prior art.

[0005] US Patent Publication No. 3,962,685-Belle Isl
e) No. 3,962,706-Dennis, etc.No. 4,096,566-Borie, etc.No. 4,096,567-Millard, etc.No. 4,130,865-Heart, etc.No. No. 4,145,739-Dunning et al. No. 4,151,592-Suzuki et al. Early binacs ("Binac": using two processors connected in parallel with each other) and various similar ones Already in the early days of the system, it was recognized that multiprocessor schemes provided redundant execution capabilities and could significantly improve the overall reliability of a working system. It had been. So far, there are considerable restrictions on the actual configuration of multiprocessor systems, but these restrictions are mainly due to the huge amount of software. is there. Nevertheless, for example in real-time applications,
In various situations where system downtime is unacceptable, multiprocessor operation has been particularly advantageous, and various multiprocessor systems have been developed so far, however, While these systems performed well, the overhead required a significant amount of software and operating time. Such conventional systems are disclosed in U.S. Patent Publication Nos. 3,445,822 and 3,566,363.
And No. 3,593,300 show specific examples. Each of these patent publications relates to a system in which a plurality of computers access a single main memory shared between them, and furthermore, in this system, the tasks are preferably assigned to individual processors. In order to allocate, the processing capacity and the processing request amount are compared.

Another example of the prior art is disclosed in US Pat. No. 4,099,233. In the system of this publication,
Multiple processors share one bus, and
The transfer of data blocks between the transmitting mini-processor and the receiving mini-processor is performed using a control unit containing a buffer register. The concept of this system is used in Europe for distributed mail classification systems.

US Pat. No. 4,228,496 relates to a commercially successful multiprocessor system in which multiple buses between multiple processors are connected to a bus controller. The bus controller monitors the data transmission status and determines the priority order for a plurality of data transfers performed between the processors. Further, each processor is connectable so as to control a certain one of a plurality of peripheral devices.

[0008] Xerox, Hewlett-Packard,
An "Ethernet" system (U.S. Pat. Nos. 4,063,220 and 4,099,024), co-promoted by Intel and Intel, addresses the problem of intercommunication between multiple processors and peripherals. For this purpose, another method is presented. All units (= processors, peripherals, etc.) are connected to a multiple access network shared between them, and the units will compete for each other to gain priority. Collision detection is performed in a time-priority manner, which makes it difficult to control global processing capability, coordinate, and clearly grasp.

[0009] In order to fully understand the various systems described above in detail, it is necessary to analyze the patent publications and other related references mentioned above in detail. However, when tasks are shared, all of these systems require a huge amount of intercommunication and management control to determine the priority of data transfer and to select processors. Only a brief overview will be understood. The problems that arise when scaling up a system to include more processors are not uniform, as they will be different for each of the different systems, but none of these systems Such an extension would complicate system software, application programming, hardware, or all three. It is also understood by some considerations,
The use of one or two sets of logically passive ohmic buses places inherent constraints on the size and capabilities of multiprocessor systems. There are a variety of techniques that can be employed to facilitate intercommunication, such as the subsystem shown in recently issued U.S. Pat.No. 4,240,143. There is a technique of grouping the resources into global resources. However, when a large number of processors are used, the amount of available traffic naturally reaches its limit, and the The fact that time takes various values raises an insurmountable problem. In some situations, one or more processors may be locked out or deadlocked, and additional circuitry and software to solve the problem require additional circuitry and software. Needed. From the above, it is clear that it has not been practical in the past to significantly expand the number of processors to, for example, 1024.

[0010] In many different applications, it is desirable to escape from the limitations of the existing techniques described above and utilize the latest techniques as a maximum source. The least costly of the currently available techniques is based on mass-produced microprocessors and high-capacity rotating disk storage, examples of such storage. Includes a device manufactured by Winchester Technology, which has a very small space between the head and the disk inside the sealed case. In expanding a multiprocessor system, it is required that the system can be expanded without unduly complicating the software, and furthermore, the software does not become complicated as it expands. There is even a demand for expansion. Still further, there is a need for the ability to deal with computer problems having features such as having a distributed structure in which the entire functionality can be dynamically subdivided into a plurality of limited or repetitively executed processing tasks. . Virtually all database machines belong to such problem areas, which also include sorting, pattern recognition and correlation calculations, digital filtering, large matrix calculations. ,
Other typical problem examples, such as simulations of physical systems, are also included. In any of these processing situations, it is necessary to make a plurality of individually processed tasks relatively simple, and to distribute the tasks over a wide range, so that the instantaneous task load is large. It will be. Such a situation has led to significant difficulties in traditional multiprocessor systems because such a situation increases the amount of time spent on overhead and the amount of software for overhead. And there is a practical problem in configuring the system. For example, when a passive shared bus is employed, the propagation speed and the time required for data transfer form an absolute barrier to the possible processing speed in processing a transaction.

[0011] Database machines are thus a good example of the need for improved multiprocessor systems. So far, three types of basic methods for configuring a large-scale database machine have been proposed, which are a hierarchical method, a network method, and a relational method. Among these, a relational database machine uses a table showing relations to enable a user to easily access given data in a complex system. Are perceived to have strong potential. Representative publications describing this prior art include, for example, IEEE
E Computer Magazine, March 1979, Issue 28
D.C.P.Smith and J.C.
Article entitled "Relational Database Machine" by M. Smith
al Data Base Machine ", published by DCP Smith a
nd JM Smith, in the March 1979 issue of IEEE Com
puter magazine, p. 28), US Patent Publication No. 4,221,003.
And various articles cited in the publication.

[0012] Sorting machines are also a good example of the need for improved computing architectures. An overview of sorting machine theory can be found in "Searching and Sorting" by Knuth, pp. 220-246 ("Searching and S").
orting "by DE Knuth, pp.220-246, published (197
3) by Addison- Wesley Publishing Co., Reading, Mas
sachusetts). This document discloses a variety of networks and algorithms, which must be considered in detail in order to understand the constraints associated with each of them, but what can generally be said about them is: All of them are characteristically complex schemes, aimed only at the specific purpose of sorting. As yet another example, L.
Some are presented by A. LAMollaar, which is published in "IEEE Transactions on Computer," Volume C-28, Issue 6, June 1979, pp. 406-413. Article entitled "A Design for a List Merging Neighborhood"
twork ", inthe IEEE Transactions on Computers, Vol.
C-28 No. 6, June 1979 at pp. 406-413). In the network proposed in this paper, a method of externally controlling a merge element of the network is adopted, and the network requires programming to execute a special function.

The functions that a general-purpose multiprocessor system must be able to perform include the ability to distribute subtasks in various ways, the ability to check the status of the processor executing the subtask, and the merging of messages. And sort and data correction and modification, and when and how resources change (eg, when a processor goes off-line and comes back on-line), etc. There is. Until now, it has been necessary to use excessive software and hardware for overhead in order to execute the above functions.

As an example, in a multiprocessor system such as a database machine, for example,
When specifying a message transfer path between processors, a specific one processor is selected as a transfer destination, a plurality of processors belonging to one class are selected, and furthermore, a processor itself is not specified. Instead, it is often necessary to select a destination processor by specifying a portion of the database distributed to the processors by a hash method or the like. Some known systems utilize a forward communication sequence to establish a linkage between a transmitting processor and one or more specific receiving processors. Requests and acknowledgments must be sent over and over again to establish this linkage, and additional hardware and software must be used to overcome possible deadlock situations . In a system that does not use the prefix communication sequence, control is performed by a single processor or a bus controller. State that it is ready, that other processors are locked out of the linkage between these processors, and that no extraneous transmissions are taking place.
It is for confirmation. Again, maintenance functions as the system is expanded (eg, with more than 16 processors) by relying on overhead and having to be complicated to avoid deadlocks. Will expand to an inappropriate level.

[0015] Yet another example of a requirement for modern multiprocessor systems relates to a method by which the system can reliably determine the status of subtasks being executed by one or more processors. There is something to do. Basically, what is required is that a given processor must be able to query the status of that processor, and that status is affected by the query. That is, the inquiry must be made so as not to cause any ambiguity in the content of the response. The term "semaphore" is currently used in the art to characterize the ability to perform a status display test and set as an uninterrupted sequence of operations. It is desirable to have this semaphore feature, but incorporation of this feature must not cause a decrease in execution efficiency or an increase in overhead load. Such status determination is further performed by multiprocessor
It is very important when performing a sort / merge operation in a system, and it is necessary to appropriately combine the processing results of a plurality of subtasks included in a large task. This is because they cannot be combined into one until after the processing is completed. Yet another requirement is that the processor must be able to report its "current" status,
In some cases, execution of a subtask must be performed only once, even if interrupts and changes are repeatedly made to the operation sequence of the multiprocessor. Most existing systems pose a significant problem in this regard because the execution routines of the processor are interruptible. That is, as will be easily understood, when a plurality of processors are executing a plurality of subtasks related to each other, the degree of the readiness state of each individual processor (= what operation is performed) The sequence of operations involved in querying and responding to the query can require enormous overhead, and the dedicated overhead therefor increases as the number of processors increases. It will eventually increase to an inappropriate level.

[0016]

A typical shortcoming of the prior art multiprocessor system, which illustrates the above example, is related to the so-called "distributed update" problem, which is a problem that can be solved by using multiple Need to update the information whose copy is stored in each of the processing devices. The information referred to here may be information composed of data records or information used for controlling the operation of the system. The control of the operation of the system includes, for example, starting, stopping, resuming, suspending, or preventing a necessary step from being duplicated or executed at all. This refers to control such as roll back or roll forward. In conventional systems, the various solutions to the distributed update problem all have considerable limitations. Some of these solutions target only two processors at a time. Some further solutions use intercommunication protocols, but these protocols are so complex that even today they are mathematically rigorous to ensure that they are appropriate. It is very difficult to prove by using.

The cause of the complexity of these protocols is that they are "tested and set" in all processors by a single uninterrupted operation that constitutes a "global semaphore". That is, it is necessary to provide a control bit having an external property. Since such control bits are provided within each of a plurality of separate processors, and the delay times associated with communication between the processors are variable, noise caused by communication channels that can inevitably be imperfect. Is generated, and the error occurrence rate is further increased. Therefore, having the feature of "one operation that is not interrupted" means that the plurality of parts constituting one operation are various and can be interrupted, respectively. It is easily understood by those skilled in the art that they cannot be accessed at the same time, and that they can be difficult if they are prone to malfunctions between accesses. Let's do it.

[0018]

SUMMARY OF THE INVENTION The present invention, in summary, provides:
A message containing one or more of several types of transfer routing information in a form called a destination selection word is transferred to a different one of the plurality of processors or some of them. A system and method for transmitting to a combination of processors is provided. The processor has an interface that includes a memory and whether each processor should process or execute the data or instructions contained in the message based on the information contained in the message. The determination is directly and efficiently made.

[0019]

According to the above arrangement, it is possible to address only one processor at a time, or to set a plurality of processors at one address.
It is possible both to address as one class and to specify the portion of the database shared by the individual processors using the hashing mode. This feature is much more sophisticated and powerful than the traditional method, where the address is included in the message and each device identifies its own address contained in the message. It is.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

(Database Management System) The system generally shown in FIG. 1 shows a specific example in which the concept of the present invention is applied to database management. More specifically, the system comprises one or more host computer systems 10,
12, and the host computer system is, for example, a computer system belonging to the IBM 370 family or the DEC-PDP-11 family. It works with existing general operating systems and application software.
According to IBM terminology, the main intercommunication network between a host computer and a database computer is called a channel, and the same is also known as "unibus" or "mass bus" according to DEC terminology. "Or some modified version of those terms. Whether any of the above computer systems are used or a mainframe computer from another manufacturer, this channel, or bus, is where the database tasks and subtasks are sent. , That is, a logically passive transfer path.

FIG. 1 shows a specific example of a host system 10.
12 shows the back-end processor complex combined at 12. The system in this figure accepts tasks and subtasks from the host system, refers to the relevant portion of the vast amount of database storage information, and returns appropriate processed or response messages, and their actions. , Regardless of the configuration of the back-end processor complex, is executed in a manner not required by the host system, except for management by less sophisticated software. Therefore, it is possible to configure a user database as a new type of multiprocessor system. In this multiprocessor system, data is stored in a relational database file capable of greatly expanding the capacity. The extension can be made without changing the operating system or existing application software provided inside the user's host system. A specific example configured as an independent system (stand-alone system) will be described below with reference to FIG.

As will be appreciated by those skilled in the art, the operational functions associated with relational database management divide an entire operational function into a plurality of processing tasks that can be processed, at least temporarily, independently of the others. This is an operation function that can be performed. The reason is that relational
This is because a plurality of stored data entries are not interconnected by an address pointer in a database. Further, as will be understood by those skilled in the art, other than relational database management, it is possible to use a method of dynamically subdividing limited or repetitively executed tasks and processing them independently. Many data processing environments exist. Accordingly, when describing embodiments of the present invention, it will be described with reference to processing issues in database management, which are particularly demanding and frequently heard, however, the novel methods and methods disclosed herein. The configuration has a wide range of other uses.

Large data management systems will have both potential benefits and unavoidable attendant difficulties when using multiple processors (multiple processors). An enormous number of hundreds of millions of entries (entries) must be kept in storage for easy and quick access. On the other hand, if the relational database format is used, a wide range of data entry and information retrieval operations can be executed concurrently.

However, in the vast majority of database systems, maintaining the integrity of the database is as important as processing transaction data quickly. Data integrity must be maintained before and after hardware failures, power outages, and other disasters involving system operation. Furthermore, the database
The system relies on bugs (buds) in the application software code.
In order to clean up user errors such as g), the database must be capable of restoring to a previously known state. Moreover, data must not be accidentally lost or entered, and whether the event is related to new data or correction of past errors, All of the portions of the database associated with a particular entry must be changed, depending on whether it concerns the proofing of a portion of the database.

Therefore, for completeness, data rollback and recovery operations, error detection and correction operations are required.
In addition to the operation and operation of detecting and compensating for changes in the status of individual parts of the system, some degree of redundancy is also required for the database system. To achieve these objectives, the system may have to be used in many different special modes.

Furthermore, in recent systems, arbitrary contents queries (discretions) whose form tends to be complicated
ary query) and, if necessary, the ability to respond in an interactive manner. Even if the query is complex,
The people who try to access the system must not be required to be experts in the system.

Examples of arbitrary queries that may occur in connection with large-scale production operations include:

A. Not only does the production control manager request a list of one of the items in stock,
An inventory list may be required that specifies all parts inventories that have exceeded their monthly output, with parts whose output has decreased by at least 10% over the same month last year.

B. The marketing manager not only asks if a particular account has a 90-day delinquency, but also has a 90 You may require a day receivable.

C. The HR executive is 2 per year
Not only do we require all employees who have been sick for more than a week to be listed, but also have been sick for more than one week during the fishing season for at least two of the last five years. You may want to list all long-term employees who have worked for more than a year.

In any of the above examples, the user
By associating the information stored on computers in a way never before done, they seek to determine the real problems facing the business. If the user has experience in the area in which the problem is occurring, and therefore has the intuition and imagination, an expert without computer training can
You can use any database system that can handle complex queries.

Modern multiprocessor systems have developed elaborate overhead and maintenance software systems for these many and often conflicting requirements.
While trying to respond by using systems, those software systems inherently hinder the easy expansion of the system. However, the concept of scalability is a strongly sought-after concept, as the business or business grows, as it is desired to extend and continue using existing database management systems. Become
In this case, it is not desirable to be forced to adopt a new system and software.

Multiprocessor Array Referring to FIG. 1, one exemplary embodiment of the system of the present invention includes a number of microprocessors, of which there are two important types. , They will be referred to herein as an interface processor (IFP) and an access module processor (AMP), respectively. In the figure, two IFPs 14, 16 are shown, each of which is connected to an input / output device of a separate host computer 10-12. Many access modules
Processors 18 to 23 are also provided in this multiprocessor
It is included in what is also called an array. As used herein, the term "array" refers to a set of processor units arranged in a generally neat, linear or matrix fashion.
A unit, an aggregated processor unit, or a plurality of processor units, used in a general sense, and thus has recently been referred to as an "array processor."
It does not mean what has come to be called. In the figure, only eight microprocessors are shown to show a simplified example of the concept of this system,
It is possible to use much more IFPs and AMPs and it will be used normally.

IFPs 14, 16 and AMPs 18 to 23
Incorporates an Intel 8086 16-bit microprocessor having an internal bus and a main memory for direct memory access to peripheral controllers. Any of a wide variety of microprocessors and microprocessor system products from various manufacturers are available. This "microprocessor"
This is only a specific example of one type of computer or processor that can be used in this array, because the concept of this system is that the computational power required by the application is that of a minicomputer or a large computer. Because they can be used successfully with them. This 16-bit microprocessor has significant data processing power and is a low cost, standard replaceable configuration that can be replaced with a wide variety of available hardware and software options. It is an advantageous example of the device of the above.

The IFP and the AMP employ similar circuits, including active logic, control logic, and an interface, a microprocessor, a memory, and an internal bus, as shown in FIGS. 1 and 18, respectively. Will be described later with reference to FIG. However, these two processor types differ in the nature of the peripherals associated with each processor type and the control logic for those peripherals. As will be readily appreciated by those skilled in the art, other processor types with different peripheral controllers and different functional responsibilities may be readily incorporated into the present invention.

Each microprocessor has a high-speed random
An access memory 26 (described in connection with FIG. 18) is provided which, in addition to buffering input and output messages, provides a unique method to the rest of the system. By cooperating with, message management is performed. In short,
The high-speed random access memory 26 serves as a circular buffer for variable-length input messages (this input is referred to as "reception"), and sequentially outputs messages (this output is referred to as "transmission"). ), Incorporates a table lookup portion for use in hash mapping mode and other modes, and stores control information for orderly handling of incoming and outgoing messages. The memory 26 is further used to perform a unique role when selecting a multiprocessor mode and when handling data, status, control, and response message traffic. As will be explained in more detail below, those memories also store the transaction
The arrangement is such that local and global status decisions and control functions are processed and communicated in an extremely efficient manner based on the identity. IFP14, 16
And the control logic 28 (to be described later with reference to FIGS. 23 and 24) provided in each of the AMPs 18 to 23 is used for performing data transfer and overhead functions in the module.

The IFPs 14, 16 each include an interface control circuit 30, which connects the IFP to a channel or bus of a host computer 10-12 associated with the IFP. On the other hand, in the AMPs 18 to 23, a device corresponding to the interface control circuit is the disk controller 32, and the disk controller 32 may have a general structure.
The MPs 18-23 are used to interface with the magnetic disk drives 38-43 individually associated therewith.

The magnetic disk drives 38 to 43 provide the database management system with a secondary storage device, that is, a mass storage device. In the present embodiment, the magnetic disk drives are composed of proven commercial products such as Winchester technology, so that the cost per byte is very low, large capacity and high reliability. Sex storage device.

In these disk drives 38 to 43, relational databases are stored in a distributed storage system, which is shown in a simplified form in FIG. Each processor and its associated disk drive is assigned a number of records that form a subset of the database, the subset being the "primary" subset and the primary subset thereof. Is a disjoint subset and constitutes a complete database as a whole. Therefore, each of the n storage devices will hold 1 / n of this database. Each processor is further assigned a subset of the data for backup, and these backup subsets are also disjoint subsets, each constituting 1 / n of this database. FIG.
As can be seen, each of the primary files is duplicated by a backup file contained on a different processor than the processor containing the primary file, thereby providing a different distribution of the files. A complete database of each of the two distributed in a manner is obtained. As described above, the integrity of the database is protected by the redundancy of the primary data subset and the backup data subset. This is because of a single failure. If there is, it is impossible to have a substantial effect on a plurality of data over a large number of blocks or a plurality of relations forming a plurality of groups.

The distribution of the database has implications for the hashing operation of the various files, as also shown in FIG. 35, and also has implications for incorporating hash mapping data into the message. Have. The files contained in each processor are 2
It is specified by a simple hash bucket shown as a group of hexadecimal sequences. Thus, based on the relational tables specified by those buckets, it is possible to determine where relations and tuples in the relational database system should be placed. Using the hashing algorithm, inside this relational database system,
The assignment of buckets is required from the key, so that the database system can be easily expanded and modified.

The size of the storage capacity to be selected depends on the database management needs, the amount of transactions, and the processing power of the microprocessor associated with the storage device. Connect multiple disk drives to one AMP,
It is possible to connect a single disk file device to multiple AMPs, but such modifications would typically be limited to special applications. Database expansion is typically performed by expanding the number of processors (and the number of disk drives associated with the processors) in a multiprocessor array.

Active Logic Network The purpose of providing an orderly flow of message packets and the purpose of facilitating the execution of tasks is to provide a unique system centered around the novel active logic network construct 50. Achieved by employing an architecture as well as a message structure. The active logic network construct 50 comprises a plurality of bidirectional active logic nodes that form an ascending hierarchy of outputs of a plurality of microprocessors, converging the outputs ascending the hierarchy. logi
c node) 54. The nodes 54 consist of a bidirectional circuit with three ports, which is a tree network (tree).
network: a network having a dendritic structure), in which case the microprocessors 14, 16 and 18 are provided in the base part of the tree structure.
To 23.

As will be appreciated by those skilled in the art, a node is:
The number of logic sources exceeds two, for example four or eight
In this case, at the same time, the problem of increasing the number of source inputs can be converted to the problem of adding additional combinational logic.

For ease of reference in the drawing, of all nodes (N), those belonging to the first hierarchy are represented by a prefix “I”, and those belonging to the second hierarchy are represented by “I”. It is represented by the prefix “II”, and so on. Individual nodes belonging to the same hierarchy
.., So that, for example, the fourth node in the first hierarchy can be represented as "IN4". On the up tree side (ie, upstream side) of the node, there is provided one port named “C port”, and two down tree trees of nodes belonging to a higher hierarchy adjacent to the C port. The ports are connected to one of the ports, and their down tree ports are named "A port" and "B port", respectively. These hierarchies are represented by a top node or vertex node 54a.
This vertex node 54a reverses the direction of the flow of the message (up-tree message) directed upstream to the downstream direction (down-tree direction).
It functions as a means for converging and turning. Two sets of tree networks 50a, 50b are used, the nodes in the two sets of networks and their interconnections being arranged in parallel with each other, thereby obtaining the desired redundancy for large systems. ing. Since nodes 54 and their networks are identical to each other, it is sufficient to describe only one of the networks.

For the sake of simplicity, it should first be understood that a number of message packets, in the form of a serial signal stream, can be connected to active logic by many microprocessor connections. -It is possible to transmit to the network 50 at the same time, or to transmit at the same time. The plurality of active logic nodes 54 each operate on a binary basis to determine a priority between two conflicting conflicting message packets, the priority being determined by those message packets. It is performed using its own data contents. Further, all nodes 54 in one network are under the control of one clock source 56, which synchronizes a sequence of message packets toward vertex node 54a. The nodes 54 are combined in such a way that they can proceed. In this way, an incremental segment, such as each successive byte, in the serial signal sequence is advanced to the next layer, and the progress of this byte is determined by the byte corresponding to that byte in another message. This is done at the same time as following another route in the network 50.

Sorting for giving priority between competing signal sequences is performed on message packets moving in the up-tree direction, and ultimately downstream from vertex node 54a. A single message sequence to be diverted to is selected. Since the system is configured as described above, it is not necessary to determine the final priority at a specific point in the message packet.
The transfer of the message can be continued without requiring anything other than a binary-based determination between the two conflicting packets being executed at the individual nodes 54. . As a result, the system spatially and temporally selects messages and transfers data, provided that it gains control of the bus and identifies the transmitting or receiving processor. Nor does it delay message transmission for the purpose of performing handshaking operations between processors.

It should also be noted that if several processors transmitted the exact same bucket at the same time, and if the transmission was successful, all of the transmitting processors were successful. It is the same as This property is extremely useful for effective control of large multiprocessor complexes, as it saves time and overhead.

Node 54 also operates in a bi-directional manner, allowing undisturbed distribution of message packets downstream. Given node 54
, The port C provided on the up tree side
Is distributed to both the port A and the port B provided on the down tree side of this node. Forwarded to both. Under the control of the common clock circuit 56, the message packet is advanced synchronously down the tree and broadcast to all microprocessors simultaneously.
oadcast), thereby allowing one or more processors to perform a desired processing task or to accept a response.

The data transfer rate of the network 50 is higher than the data transfer rate of the microprocessor, and is typically more than twice as high. In this embodiment, network 50 has a byte clock interval of 120 nanoseconds, and its data rate is five times that of a microprocessor. Each node 54 has its three ports connected to a port of a node belonging to an adjacent hierarchy connected to the node or to a microprocessor, and the connection is made by a set of data lines (books). 10 lines in this embodiment) and control lines (2 lines in this embodiment)
The two control lines are respectively assigned to a clock signal and a collision signal (collision signal). The data lines and the clock lines are wired in pairs, and are separate lines in the up tree direction and the down tree direction. The collision line propagates only in the down tree direction. The above connection structure forms a full-duplex data path so that no delay is required to "reverse" the drive direction of any line.

Referring now to FIG. 13, ten data lines include 8-bit bytes, represented by bits 0-7, which comprise ten data lines.
Occupies eight of the lines. Another line, denoted C, is a control line, which carries a control sequence used to specify different parts of the message packet in a particular way. The tenth bit is used for odd parity in this embodiment. As will be appreciated by those skilled in the art, the system may increase or decrease the number of bits in the above data path, and may easily operate with such a change in the number of bits.

A byte sequence (a sequence of bytes) is arranged to form a series of fields, and is basically divided into a command field, a key field, a destination selection field, and a data field. Have been. As will be described in more detail below, the message may use only one field and terminate with a detectable "end of message" code. The "idle field" intervening between messages is represented by a continuous series of "1s" on the C line as well as on lines 0-7, and no message packet is available. Is always being transferred. Parity lines are also used to uniquely communicate changes in the status of individual processors.

An "idle state" is an intervening state between messages and is not part of a message packet.
A message packet usually begins with a two-byte command word containing a tag, which is in the form of a transaction number (TN) if the message is a data message, and the message If it is a message, the source processor ID (OP
ID). Transaction numbers have various levels of significance in the system and serve as the basis for many types of functional communication and control. After the command word, the packet consists of a variable-length key field and a fixed-length destination selection word.
word: DSW), which form the beginning of the variable length data field. The key field serves the purpose of providing a criterion for sorting between messages in cases where the messages are otherwise identical to each other in other parts of the key field. DSW provides the basis for a number of special features and is worthy of special attention with TN.

The system is adapted to operate using a word-synchronized interface so that all processors attempting to transmit a packet send the first byte of the command word to the network 50 simultaneously with each other. It is designed to be sent. The network uses the data content of the fields that follow to sort at each node on a binary basis, with the lowest numerical values being given priority. Of the consecutive data bits, if bit C is considered to be the largest quantity and bit 0 is considered to be the smallest quantity, the sorting priority is as follows:

1. 1. first sent to network 50; 2. a command code (command word) having a minimum value; 3. the key field is the minimum value; 4. the shortest key field; 5. The data field (including the destination selection word) is the minimum value; The shortest data field.

In view of the purpose of explaining the overview here, it should be noted that if the priority is determined at the node 54, the collision display (= collision display, hereinafter referred to as Acol or Bcol) ), But
In the determination of the priority, the transmission of the loser is returned to the route of the receiver. This collision indication indicates that the transmitting microprocessor has aborted its transmission because the network 50 is being used for a higher priority transmission, and will need to try again later. You can recognize that.

Simplified examples are shown in the various diagrams of FIGS. In this embodiment, the network 50 operates in cooperation with a high-speed random access memory arranged in a tree structure using four separate microprocessors. In more detail, IFP
14 and three AMPs 18, 19 and 20. FIGS. 3 to 12 showing a total of 10 planes show that t = 0 to t
= 9, corresponding to one of ten consecutive time samples, and at each of those times, a different simplified simplification sent from each of the microprocessors in this network ( 4 illustrates aspects of the distribution of serial messages (consisting of four characters) and the state of communication between the port and the microprocessor at those various times. FIG. 2 simply shows the state of the system before the start of signal transmission. In each of the above figures, it is assumed that transmission represented by “□” must be performed in order to be in a null state (a null state), that is, in an idle state. Since there is an agreement that the data content having the minimum value has priority, the message packet "EDDV" transmitted from the AMP 19 in FIG. 3 is the first message packet transmitted through this system. Each message in the figure is maintained within a high speed random access memory (sometimes referred to as HS RAM) in a microprocessor, as described in more detail below. H. S. The RAM 26 has an input area and an output area schematically shown in FIG. 3. At t = 0, a packet is stored in the output area in a FIFO (first in first out) system. Are arranged vertically, so that when data is transferred, H.D. S. It can be taken out as indicated by the cursor arrow written in the RAM 26. At this point, network 5
All transmissions in 0 indicate a null or idle state (□).

On the other hand, t = 1 shown in FIG.
At this point, the first byte of each message packet is sent out to the network 50 at the same time as each other, at which time all the nodes 54 are still returning an idle status indication and all the transmission statuses above the first level. Is also idle. During the first clock interval, the first byte of each message is set inside the lowermost nodes IN1 and IN2, and t =
At 2 (FIG. 5) the conflict is settled, and both the upstream transmission and the downstream transmission are performed in succession. Node IN1 has received "E" on both its input ports, and is forwarding it to the next layer upstream, and is pending in the downstream direction to both transmit processors. Is displayed. However, the node IN2 belonging to the same hierarchy determines the priority in the event of a collision between “E” from the processor 19 and “P” from the processor 20, and determines that the priority is toward “E”. If so, port A is coupled to port C on the up tree side while returning a Bcol signal to microprocessor 20. When the Bcol signal is returned to the microprocessor 20, the IN2 node has effectively locked its A input port to the C output port, thereby transmitting the serial signal sequence from the microprocessor 19 to the vertex node IN1. It will be transmitted.

In the IN1 node, the first two characters are both "ED", so that as shown in FIG. 5, it is impossible for this node to make a decision at time t = 2. I have. Furthermore, the common leading character "E" sent from the three microprocessors 14, 15 and 19 reaches the II1 vertex node at time t = 3 (FIG. 6), and this character "E" Similarly, when the second letter "D" common to all those messages is transferred to this vertex node IIN1, the direction of the transfer is reversed and directed downstream. At this point, node IN1 is still in a state where it cannot make a decision, however, at this time, a series of microprocessors 14, 18
And the respective third letters "F", "E" and "D" from 19 are being transmitted to this node IN1. The fact that the microprocessor 20 receives the Bcol signal means that the processor 20 has lost in the race to gain priority, and therefore, if the processor 20 has received the Bcol signal, an idle indication (□)
Is transmitted, and thereafter, only this idle display (□) is transmitted. Each cursor arrow written to each output buffer indicates that microprocessor 20 has been returned to its initial state, while the other microprocessors continue to send a continuous sequence of characters.
Therefore, the important event at time t = 4 (FIG. 7) is
A determination is made as to the port of node IN1 and that the leading character ("E") is inverted and transmitted through all lines to the first level node hierarchy. At time t = 5 (FIG. 8), a second collision is indicated, in which case the B port of node IIN1 wins the conflict and an Acol is generated.

During the subsequent several clock times, the downstream broadcast of the serial signal sequence is continuously performed, and at the time t = 6 (FIG. 9), the first character of the message is All H. S. It is set in the input area of the RAM 26. One thing to note here is that the priority decision made earlier at node IN1 is invalidated at this point, because the When the third character ("E") loses the competition with the third character ("D") sent from the microprocessor 19, the node AIN1 of the higher hierarchy leaves the node Aco.
This is because l is displayed. As indicated by the cursor arrow in FIG.
4, 18 and 20 have been returned to their initial state,
The winning microprocessor 19 has already completed all of its transmissions at the time t = 4. As can be seen from FIGS. 10 and 11, the priority message "EDDV" is sequentially loaded into all the input buffers. t
= 8 (FIG. 11), this message has already flowed out of the first layer and the vertex node IIN
1 has already been reset at t = 7 since only the idle signals are already competing with each other when the last downstream character is transferred to the microprocessor. At the time t = 9 (FIG. 12), the nodes IN1 and IN1 belonging to the first hierarchy
2 has been reset, and all of the lost microprocessors 14, 18 and 20 have taken priority over the network by sending out the first character of the message when the network is indicating idle again. Competition to get it again. In fact, as explained later, an acknowledgment signal is transmitted to the winning microprocessor,
It is not essential to the maximum generalization of the invention.

After the message has been broadcast to all microprocessors in this manner, the message is utilized by any of those microprocessors, or by all of them, as needed. How many microprocessors are used depends on the mode of operation and the function to be executed, and there are various variations in the operation mode and function.

Global Intercommunication and Control The embodiment described above as a way for the network to give priority to one of a group of conflicting messages is the transfer of primary data messages. It is an example about. However, complex multiprocessor systems need to utilize many other types of communications and commands to provide the good efficiency and versatility required today. Key functions that must be provided include, in addition to the transfer of primary data, what can be broadly referred to as multiprocessor modes, acknowledgments to messages, status indications, and control signals. I have. The following sections discuss, from a global perspective, how the various modes and messages cooperate with a sorting and communication network that performs sorting and communication for prioritization, i.e., multiprocessor systems. It presents an overview described from a system perspective. For a more detailed understanding, please refer to FIGS. 18, 23 and 24 and the following description of these figures.

In a broadcast or broadcast mode, a message is delivered to all processors simultaneously without specifying one or more specific receiving processors. This mode is used
Typical examples are responses, status queries,
Commands and control functions.

If the receiving processor needs to be specified, the destination selection information contained in the message packet itself should accept the packet locally (= in individual processors). A criterion for judging whether to reject is provided. By way of example, the interface logic inside the receiving processor module may, according to the map information stored in the high-speed RAM 26, cause the data of the packet to fall within the range of the particular processor in which the interface logic is incorporated. Identify if it is included. By differently setting the map bits in the high-speed RAM, the criteria for the different selection schemes can be easily set, including, for example, the selection of a particular receiving processor, ("hashing" Selection of a portion of the stored database, selection of a logical process type ("class"), and so on. The use of broadcast with local access control (= access control performed on individual processors) is particularly beneficial for database management systems, which are widely distributed and require little overhead software. Access to any part of the relational database or distributed local copy of any of a plurality of globally known logical processes. Accordingly, this system can specify and select one transfer destination processor as a transfer destination of a message, and can specify and select a plurality of resources belonging to one class.

Furthermore, high-level database queries often require a cross-reference between different parts of the database and a consistent reference for a given task. The transaction number (TN) embedded in the message can be of various attributes, among others, providing the identity and reference of such a global transaction. A large number of tasks can be processed concurrently by local processor modules (local processor modules) that operate asynchronously with each other, and each task or subtask has an appropriate TN
Have been to have. By using various combinations of TN, DSW (transfer destination selection word) and commands, virtually unlimited flexibility is achieved. A wide range of sort / merge operations can be applied to a very large number of tasks whose allocation and processing are performed asynchronously. The TN can be allocated and abandoned, and the merge operation can be started and stopped. Certain messages, such as continuation messages, may have priority over transmission of other messages. By utilizing a TN and a local processor that updates the status for that TN, a given TN can be obtained with only one query.
To determine the status of the global resource for. Distributed updates can also be achieved with a single communication. The system of the present invention
All of the above functions are performed without extending software or significantly increasing overhead burden.

The consequence of using the present invention is that a multiprocessor system with a much larger number of processors than the microprocessors typically found in the prior art can be very effectively used for the task at hand. It becomes possible to operate. Microprocessors are now inexpensive, enabling systems that perform well in problem areas, and that do more than just have "raw" power. can do.

A consistent priority protocol that encompasses all message types and various subtypes is:
It is defined to encompass all of the various messages provided to the network. Response messages, status messages, and control messages are different types of messages from primary data messages, but they are also similar to network contention /
Using a merge operation (contention / merge operation)
Thus, priority is given during the transfer. The response message in the present system may be an acknowledgment (ACK), a negative acknowledgment (NAK), or an indication that the processor has no resources to perform meaningful processing on the message ("non- Not applicable processor "
-NAP). NAK response is locked state,
It can be any of several different types that indicate an error condition or an overrun condition. Although there may be only one sender processor or multiple sender processors, since the sender processor needs such a response after finishing the transmission of the message, the primary message is included in the response message. Has a higher priority than the message.

The system further includes a SACK message (status acknowledgment message: status acknowledgment).
message), and the SACK message is
This indicates the readiness state of a certain local processor (readiness state) for a specific task or transaction. The content of this SACK response is updated locally (= at the individual processor, ie at the local processor) and kept accessible from the network. Such a SACK response is combined with the merge operation of the network to provide a global status report with a single query for a given task or transaction. Since the status response follows the priority protocol, the response with the smallest data content among the responses related to one transaction number automatically takes priority, whereby the lowest readiness state becomes the global system state. And this is done by a single uninterrupted operation. Further, such a SACK indication may be used with certain primary messages, thereby
For example, various protocols such as system initialization and lockout operation are set.

The priority protocol for the various message types is first defined for a command code which, as shown in FIG. The first six bits are used. This allows for sufficient discrimination with respect to message types and subtypes, but it is also possible to provide more multi-level discrimination.
As can be seen from FIG. 21, in this embodiment,
The SACK response is intended to distinguish between the seven different status levels (and also provide criteria for priority determination). In the case of a response message,
After the above 6 bits, a tag in the form of a 10-bit OPID follows (see FIG. 13). Both the TN and the OPID can serve as additional sorting criteria because of their TN and OPID
This is because they have different data contents inside the tag area.

After each primary message has been transmitted over the network, the interface portion of every processor will generate a response message anyway, even if it is a NAP. The response messages also compete with each other on the network, so that a single or common winning response message is broadcast to all processors. The lost message packet will be tried again at a later time, but again after a very short delay, thereby ensuring that the network is used substantially continuously. . Multiple processors ACK
If responses have been sent, their ACK responses
Sorting is performed based on D.

The consequence of using the present invention is that the starting, stopping, and controlling of tasks, and interrogation of tasks, can be performed by a very large number of physical processors with little overhead. This is due to the low power of many processors.
r) can be used effectively for handling problem situations, since the amount of this low power that is devoted to system coordination and control is very small. is there. Coordination and control overhead are fundamental constraints on the efficiency of any distributed processing system.

Global control (ie, network control)
For this purpose, various types of control communication are used. Accordingly, the "Merge Stop", "Status Request", and "Merge Start" messages, messages for allocating certain tasks, and messages for abandoning certain tasks have the same format as data messages. Therefore, those messages are also referred to herein as primary messages. These control messages also contain the TN, and are located in place in the priority protocol. This will be described later with reference to FIGS. The term "global semaphore buffer system" was first used in the fast random access memory 2 shown in FIG.
6 and the control logic 28 play an important role both in the selection of the mode of the multiprocessor and in the two-way communication of status indications and control instructions. The global semaphore buffer system provides access redundancy, which means that both the high-speed network structure 50 and the slower-operating microprocessor have memory 26 Messages, responses, controls within
Or the status display can be viewed without delay and without the need for direct communication between the network and the microprocessor. To accomplish this, the control logic 28 stores the memory 26 in the inserted word cycle (interl
time multiplexed in an eaved woed cycle and connected to the network 50 and the microprocessor, thereby resulting in the memory 26
It's the same as having separate ports that can be accessed in common. The global resource, the network 50 and the plurality of microprocessors, use the transaction number as an address locator that locates the portion of memory 26 that is allocated to store the status of the transaction. be able to. Local level (=
At the individual processor level), the status of the subtasks for a given transaction, including any kind of availability, is updated inside the memory 26 under the control of the microprocessor and by the control logic 28 the buffer system. Is locked. By using one of seven different ready states, the entry is stored in memory 26.
From different dedicated parts. If a query is received from the network, a communication of the status of the processor is made (i.e., a "semaphore" is read) and a priority determination is made in the network, with the degree of completion being determined. The lowest readiness status will get priority. With the above-described configuration, a quick hardware response from one processor to one query can be obtained. Therefore, it is possible to know without delay and without using software whether or not execution of all of a plurality of distributed subtasks relating to a given task has been completed. Further, in this system, any of the communicating processor modules can assign a transaction number, and the transaction number assignment uses the available transaction number for a message. Or an operation allocated for use within each global semaphore buffer system.

The preferred embodiment of using the transaction identity and status indication in an integrated manner is that each of the plurality of processors sorts all messages related to a given criterion in order. There is a compound merge operation that is required to be sent. If it is a system according to the prior art, each processor first receives its task and completes its processing, and then uses the result of that processing as a sort of "master" to perform the final merge operation. It would have to take the form of forwarding to the processor. Thus, the master processor is a significant bottleneck to the efficiency of the system.

If the global readiness state confirms that all of the affected processors are in a ready state, the memory 2 provided in each processor is provided.
The messages with the highest priority at 6 are sent to the network simultaneously with each other, and for those messages a priority determination is made during the merge, as described above. Successive retransmission attempts are made for a number of groups of messages, resulting in multiple messages ordered from highest to lowest priority for the transaction number, ending with the lowest priority. A serialized message sequence is generated, with things coming. According to a special command message, the system can stop and restart the merge operation in the middle, so that multiple merge operations in the middle of execution at the same time can be performed. There is a possibility that the network 50 is shared, which makes it possible to use the resources of the system very effectively.

Therefore, at any time, all the active processors connected to the network 50 can execute operations related to a plurality of messages related to various transaction numbers asynchronously with each other. Has become. The same transaction number or "current" by one status query
If a transaction number reference is made, all processors respond synchronously with one another with one of the available status levels. For example, the "START MERGE" message causes a test (= investigation) of the global semaphore specified by a particular transaction number, and the global state obtained as a result of this test. Is in the “ready” state (ie, “SEND READ”
Y) or "RECEIVE READY"), the TN transmitted with the current transaction number (present transaction number: PTN) value included in this "merge start" message Is set equal to the value of (If the global state resulting from the test was not the "ready" state, the PT
The value of N will be returned to the value "TN0 (this means that the transaction number (TN) is" 0 ")".

Further, the "STOP MERGE" message also resets the current transaction number to "0". In this way, “TN0” is used as a “default” value transaction number used for a message from one processor to another (point-to-point message). . In other words, this "TN0" means "non-merge"
The operation of the mode is specified.

In this global intercommunication system, the message structure shown in FIGS. 13 (a), (b), (c) and FIG.
18 and 2 for the configuration of the access memory 26.
0 is adopted. A more detailed description will be given later with reference to FIGS. 15, 17, 19, 23, and 24.
Will be performed in connection with

As can be seen from FIGS. 13 (a) to 13 (c) and FIG. 21, the command code used for the response is 0.
0 to 0F (hexadecimal), and the command code used for the primary message is 10 (1
Hexadecimal) to larger values. Therefore, the response has priority over the primary message, and the smallest value comes first in the arrangement order shown in FIG.

One high-speed RAM memory 26 "(FIG. 18) has a dedicated storage area (an area described as" transaction number "in FIG. 18) in the word format shown in FIG. Readyness status, TN
(Assigned state, as well as TN unassigned state). Among other dedicated parts of this memory 26 "are a circular buffer for input (received messages) and a storage space for output messages. Another separate part of this memory 26" is included. The separation area is used as a message completion vector area, and this area allows a pointer to be placed on an output message that has been transmitted, thereby effectively utilizing storage space for the output message. It has become.

As can be seen, for the memory 26 and the control logic 28, their queuing and data buffering functions are certainly important, but together with them, the global transaction Has a unique significance in that it operates in a distributed manner with respect to the individual processors.

(Active Logic Nodes) In each of the two networks arranged with redundancy, the plurality of active logic nodes 5 shown in FIG.
4 have the same configuration as each other, except that only the direction reversal node 54 at the top of each network does not have an upstream port, but instead has a direction reversal in the downstream direction. It has a simple signal direction inversion path. As shown in FIG.
Can be largely divided into two groups based on functions. One of these functional groups relates to the transmission of messages and collision signals (collision numbers), the other relates to the generation and retransmission of common clock signals. The clock signals are synchronized so that there is no skew between the respective clock signals at different nodes, ie, zero skew. These two functional groups are not independent of each other because
This is because the skew clock circuit forms an important part of the signal transmission system. Both word clock (consisting of two serial bytes) and byte clock are used. It should be noted that, particularly when setting or resetting the state of the active logic node 54 and setting different operation modes,
There is no need to control this active logic node 54 externally, and no such control is actually performed. Furthermore, because each node 54 has the same structure as each other, it is possible to mass produce those nodes using modern IC technology, thereby increasing reliability and increasing cost Can be reduced.

Each of the "ports" of A, B and C referred to above has 10 input data lines and 10
Book output data lines. For example, at the A port, the input line is represented by AI and the output line is represented by A
It is represented by 0. For each port, along with the upstream and downstream clock lines, one
The book's "collision" line (or "collision" line) is used (for example, Acol is used for the A port). Each data line of the A port and the B port is connected to a multiplexer 60, and the multiplexer 60 determines which of the two words conflicting with each other is the preferred word, or whose conflicting words are identical to each other. (If) the common word is converted to data signal C0.
To the up register 62 connected to the upstream port (C port). At the same time, downstream data sent from the higher hierarchical node and received at port C is shifted into the down register 64 and shifted out therefrom to form the A and B ports. Occurs as output to both.

One of the serial upstream signal streams of bytes can be blocked, however, without any additional upstream or downstream delay, and The words form a continuous column under the control of the word clock as well as the byte clock, and
And through the down register 64.

The mutually conflicting bytes supplied to the A port and the B port at the same time are sent to the first and second parity detectors 66 and 67 and also sent to the comparator 70. The priority is determined based on the eight data bits and one control bit in such a manner that the data content with the smallest value gets the priority. In the priority determination protocol, the "idle" signal, that is, the signal when no message is present, is a continuous "1" sequence. Parity errors can be caused by typical causes, such as the presence of excessive noise, or by any other factors that affect signal transmission or circuit operation. However, in the system of the present embodiment, the parity error indication is also used for another important application.
That is, each time a microprocessor transitions to an inoperative state, the transition is marked each time, and this marking is such that all output lines, including the parity line, are high (i.e., the value is "1"). ) So that the odd parity
An error condition is generated.

This parity error display indicates "marker" in the network if one error has occurred.
r) ", which allows the system to identify a change in the global resource and initiate a procedure to determine what the change is. ing.

The pair of parity detectors 66 and 67 and the comparator 70 supply signals to a control circuit 72. The control circuit 72 includes a priority message switching circuit 74.
And if the priority is determined, the comparator 7
The multiplexer 60 is configured to lock the multiplexer 60 to one of two states in response to the output of 0, and is further configured to generate and propagate a downstream collision signal. The name of the transition parity error propagation circuit 76 is because it forces a parity error condition in the network, as described above, in which all lines are simultaneously "1". The reset circuit 78 is for returning this node to an initial state, and includes an end of message (EOM) detector 80.

In order for the functions described above, as well as those described below, to be performed, each active logic node uses a microprocessor chip to perform these functions. However, they can be more easily implemented by performing their functions in accordance with the state diagram of FIG. 15 and the logical equations described below. In the state diagram of FIG. 15, the state S0 represents an idle state, and also represents a state in which it is not determined that one port has priority over the other port because messages competing with each other are the same. ing.
The S1 state and the S2 state are a state in which the A port has priority and a state in which the B port has priority, respectively. Therefore, when the data content of the BI is larger than the data content of the AI and there is no parity error in the AI, or when there is a parity error in the BI (there is a parity error in these AIs). The condition that the parity error does not exist and the condition that the parity error exists in the BI are denoted by AIPE and BIPE, respectively, and are represented by the states of the flip-flops. The opposite logical states (logical conditions) for AI and BI exist as states (conditions) at which the device should transition to the S2 state. If a higher level node issues an indication that a collision has occurred at that level, that indication is included in the downstream signal and sent back as COLIN. The device is capable of operating in the S0 state, the S1 state, and the S2 state.
S3 regardless of the state of the state
State and transfer this collision signal downstream as Acol and Bcol. When in the S1 state or the S2 state, since this node has already made a decision, the collision signal is transmitted in the same manner in the downstream direction to the (two) nodes in the lower hierarchy. When the priority message switching circuit 74
Is locked to the A port or the B port depending on the situation.

Reset circuit 78 includes an EOM detector 80, which is used to reset the node from S3 to S0 (FIG. 15). The first reset mode uses an end of message (EOM) field that terminates the data field in the primary message as shown in FIG. Using a group of flip-flops and gates, the following logic state is created.

URINC / URC / URCLY where URC represents the control bit in the up register, URINC represents the value of the control bit in the input signal input to the up register, and
CDLY represents the C value (= control bit value) in the up register delay flip-flop.

As shown in FIG. 16, a bit pair (bit pair) in which a set of two consecutive bits in a sequence of control bits specifies a certain field,
The transition from one field to the next is specified. For example, from a control bit state in which only “1” used at the time of idle continues, “0, 1”
The transition to the bit sequence (= bit pair) of this specifies the start of the field. This "0, 1"
Is used to identify the start of the data field. The subsequent string of "1,0" control bits indicates an internal field or subfield, and the end of message (EOM) is identified by the "0,0" control bit pair. Is done. The state where the bit pair of “0, 0” comes after the string of the bit pair of “1, 0” is a unique state, and can be easily identified. URINC signal,
The URC signal and the URCDLY signal are ANDed together, and each of these signals is delayed from each other by one byte clock. The waveform of the signal resulting from these ANDs is high until the beginning of the message packet, turns low at this start, and while this data (= message packet) continues, The waveform stays at a low level. This waveform returns to a high level two byte clocks after the EOM is generated. EOM is detected by the transition in which the waveforms URINC, URC, and URCDLY turn positive. As shown in FIG. 15, the return operation from S1 or S2 to S0 is triggered by this positive transition.

When a node of a higher hierarchy is reset, it is brought into the COLIN state, which indicates that the collision state has disappeared. This logic state starts the return operation from S3 to the base state S0. Note that this COLIN state is an end of
As messages "run through" the layers of the network 50 one after the other, they propagate down to those layers. As described above, each node can reset itself regardless of the length of the message. It should be further noted that regardless of the initial state of the network, all nodes are reset to the S0 state if an idle signal is provided.

The collision signal is returned to a plurality of processor modules. The modules store the collision state information and return to transmitting the idle sequence, the transmission of the idle sequence being performed while the processor winning the contention continues to transmit. I have. The processor is COLIN
A new transmission can be started as soon as the transition from to COLIN is detected. Still further, the processor may initiate a new transmission if it continues to receive idle signals for 2N byte clock times, where N is the number of layers in the network. It is made possible because such a situation, like the former situation, also indicates that no previously transmitted transmissions remain in this network. According to the latter of these schemes for enabling new transmissions, a processor joining the network for the first time can enter into a message synchronization state with the network if the traffic is small, so that this initial Participating processors do not have to wait for polls from other processors to initiate intercommunication with other processors on this network.

The parity error state is described in the state diagram of FIG. 15, and is set according to the following logical expression.

PESIG = AIPE AIPEDLY + BIPE BIPEDLY If the logic state of this PESIG is true,
The input signal URIN to the register is (URIN 0... URIN 7,
C, P = 1 ... 1, 1, 1). To satisfy the above equation, the transition parity error propagation circuit 76
Parity error flip-flop for PE, ie, A input, and delay flip-flop (AIPEDLY)
And The latter flip flop is AIP
According to the setting state of E, the state is set one byte clock later. Therefore, regarding the A input, when the flip-flop for AIPE is set due to a parity error, the PESIG value becomes high for one byte clock, so that this PESIG signal becomes a parity error. Is propagated only once when the first indication is made. This same condition occurs when all of the data bits, control bits, and parity bits are all “1” values, but the transition described above for the state of the global resource occurs. This is the state that occurs when you do. This forces all lines to go high, creating a state of all "1" s and establishing a total number even state (odd parity state), which results in the AIPE flip-flop to the state described above. The flop and the AIPEDLY flip-flop are set to indicate a parity error. The above arrangement operates in a similar manner when the message packet received at the B port contains a parity error or a forced parity indication to indicate a status change.

Parity errors caused by noise effects or other variables usually do not affect the operation of the processor because of the use of redundant networks with redundancy. Because it is. For monitoring or maintenance, the occurrence of a parity error is displayed using an indicator light (= indicator light: not shown). However, for a parity error that propagates only once indicating a status change, it initiates a routine to evaluate the significance of the change.

As shown in FIG. 14, the clocking system used for this node 54 does not depend on the number of layers used in the network. (Sk
ew) provides a unique means for ensuring that ew) is zero, ie, maintaining a zero skew condition. The clock circuit 86 includes a first and a second exclusive OR.
Gates 88 and 89, the outputs of their exclusive-OR gates designated A and B, respectively,
, Subtract between them (ie, "BA" operation)
Is performed so that the addition circuit 92
Controls the phase of the output from an oscillator (PLO) 96, which is a phase locked loop after being passed through a low pass filter 94. The inputs to the first exclusive OR gate 88 are the output of this PLO 96 and the downstream clock supplied via the isolated drive circuit 97 from the adjacent higher level node element. The line of this clock is labeled "word clock", which is obtained after a known delay τ from an adjacent higher hierarchy, and this same clock signal is no longer The signal is returned to an adjacent higher-level node via one insulating drive circuit 98. The input to the second exclusive OR gate 89 consists of the word clock and clock feedback from the adjacent lower hierarchy, which also receives the signal from the PLO 96. .

The above word clock line is connected to the third
Are connected to two inputs of an exclusive-OR gate 100, both of which are directly connected and those connected via a τc delay line 101. As a result, a byte clock signal having a frequency twice as high as that of the word clock and being in timing with the word clock is obtained.

The operation of the clock circuit 86 is described in FIG.
This can be better understood by referring to the timing diagram. Clock out signal (clock output signal)
Is the output of PLO 96. Of course, the primary purpose of this clocking system is to maintain zero time skew between the clock output signals for all nodes in the network, so of course The signals need not have the same nominal frequency as each other. The delay τ due to the transmission line between the nodes is set to a substantially constant value, but the value of the delay itself can be set to a long time. If the method disclosed herein is adopted, 28 feet (8.53) when the byte clock speed of the network and the node is set to the speed adopted in the actual system (120 ns nominal).
m). As will be readily appreciated by those skilled in the art, networks that are not heavily populated with the maximum possible number of processor modules can be implemented by adding additional layers to the network.
Lengths that are integral multiples of feet can be easily obtained. In that case, the waiting time, ie the transmission time of the transmission made through the network, is correspondingly increased.

As shown by the waveform immediately below the clock out signal in FIG. 17, the word clock obtained from the adjacent higher hierarchy has a similar waveform to the clock out signal, However, it is delayed by τ. This word clock forms a fundamental timing reference common to all nodes, but it is possible that the leading edge of each clock out signal is controlled within the circuit. Since their leading edge can be preceded by a word clock, so that all nodes can be kept in sync. As can be seen with reference to waveforms A and B, pulse A generated by first OR gate 88 terminates at the leading edge of the word clock, while second OR gate 89 generates. Pulse B
Has its leading edge coincident with the leading edge of the word clock. The trailing edge of this B pulse is located at the beginning of the feedback pulse from the adjacent lower layer module, and since this feedback pulse is delayed by τ, the B pulse has a constant duration. It has become. Clock circuit 86 acts to keep the duration of pulse A the same as the duration of pulse B, but it does so because it advances the phase of PLO 96 to establish synchronization. With the addition circuit 92
(The signal obtained by performing the subtraction “BA”) approaches zero. In practice, adjustments are made to this A signal by adjusting the leading edge of the A signal, which may be ahead or behind the preferred position, as shown by the dashed line.
The leading edge of the signal is positioned ahead of the leading edge of the word clock by a time τ. At all nodes,
Once the leading edge of the clock out signal is at this preferred nominal position, a zero skew condition exists between word clocks. Thus, each processor connected to the network is free of the constraints on the total length of the path from one processor to another, but without delay accumulation and the difference in propagation time. It does not occur.

In order to generate a double frequency byte clock, a word clock delayed by a delay time τc is duplicated by the delay line 101.
01 also supplies a signal to the gate 100. Thus, as can be seen from the waveform labeled byte clock in FIG. 17, byte clock pulses having a duration .tau.c are generated at both the leading and trailing edges of the word clock. . The occurrence of this pulse occurs twice during each word clock interval, and
All occur at the node in synchronization with the word clock. In the above description, the delays caused by the transmission lines between nodes are almost the same in either direction of transmission from layer to layer, so that virtually all of the It is a natural premise that the word clock and the byte clock are maintained in a stable phase relationship with each other. The byte clock generated locally (= inside the individual nodes) is therefore the two-byte word (= word of two bytes) of the message at each node.
It offers a clocking function for its individual bytes.

The active logic node described above has potential advantages whenever it is desired to resolve conflicts between simultaneously transmitted message packets based on their data content. . In contrast, for example, U.S. Pat. No. 4,251,879 issued Feb. 17, 1981, entitled "Speed Independent Arbiter Switch for Digital Communication Networks (Speed In).
dependent Arbiter Switch for Digital Communication
Nbiworks), most known systems aim to determine which signal is received first in time, and use externally provided processing. It uses a circuit or a control circuit.

(Processor Module) The individual processors shown in the schematic diagram of the entire system in FIG. 1 are interface processors (IFPs) 14 and 16 and an access module module, respectively.
Processors (AMPs) 18-23 are shown as specific examples, and these processors are broadly subdivided into a number of major components. A more detailed example of the construction of these processor modules (IFP and AMP) would have a correspondence with the functional broad subdivision of FIG. 1, but not only It also indicates a considerable number of further subdivisions. "Processor module" as used herein
The term refers to the entirety of the assembly illustrated in FIG. 18, which assembly includes IFP or A
It can function as any of the MPs. The term “microprocessor system” is used for a system 1 having a built-in microprocessor 105.
03, where the microprocessor 10
5 is, for example, an Intel 8086 type (Intel 8086) 16
A bit microprocessor. The address path and the data path of the microprocessor 105 are connected to a general peripheral system such as a main RAM 107 and a peripheral device controller 109 inside the microprocessor system 103. The peripheral device controller 109 includes a processor
The module is AMP and the peripheral device is a disk
This is shown as an example of what can be used when the drive 111 is used. On the other hand, if the processor module is to act as an IFP, the controller or interface may be replaced by a channel interface, for example, as shown in the dashed rectangle. IFP in such an embodiment
Communicates with the host system channel or bus. Since conventional general controllers and interfaces can be used for the microprocessor system 103, it is not necessary to describe those controllers and interfaces in further detail.

It should be noted that the use of one disk drive per microprocessor can indicate a cost and performance advantage. The advantage of such a scheme is that
As is generally the case with databases,
However, sometimes it is beneficial to configure a microprocessor so that one microprocessor can access multiple secondary storage devices. In the schematic diagram, other commonly used subsystems are not shown for simplicity. The omitted subsystem is, for example, an interrupt controller or the like, and the interrupt controller is supplied by a manufacturer of a semiconductor for use in combination with its own system. Also,
Those skilled in the art will also appreciate the importance of taking appropriate measures to supply power to the processor modules that will maximize the redundancy and reliability that the present invention can provide. Like.

The peripheral controller 109 and the channel interface, which are shown as optional elements in the microprocessor system 103, correspond to the IFP interface and the disk controller in FIG. In contrast, the high-speed RAM shown in FIG.
26 is actually the first HS RAM 26 'and the second HS RAM 26'.
RAMs 26 ", each of which has been functionally rendered a 3-port device by time multiplexing, and their ports Of the microprocessor (port indicated by "C" in the figure). HS RA
M26 ', 26 ", respectively, cooperate with the first and second network interfaces 120, 120', respectively, such that the first and second networks 50a and 50b, respectively (these networks are shown in FIG. 18), and communicate via an input (receive) port A and an output (transmit) port B. Thus, two systems having redundancy with each other are provided. Therefore, only the second network interface 120 'and the second HS RAM 26 "need be described in detail. Network interface 12
Although 0, 120 'are shown and described in more detail in connection with FIGS. 23 and 24, they can be divided into the following four main parts if they are largely subdivided.

The ten input lines from the second network 50b are connected to the HSR via the interface data bus and the interface address bus.
Input register connected to the A port of AM26 "
Array / control circuit 122;

The output line to the second network 50b is connected to the interface data bus and the interface address bus, and to the second HS RAM 2
An output register array / control circuit 124 connected to the 6 "B port.

Interface address bus, interface data bus, HS RAM2
A microprocessor bus interface / control circuit 126 connected to the 6 "A and B ports.

A clock generation circuit 128 which receives the word clock from the network and generates a plurality of clocks synchronized with each other and in an appropriate phase relationship for controlling the interface 120 '.

Second network interface 1
20 'and HS RAM 26 "cooperate with microprocessor system 103 to coordinate data transfer between a high speed network and a lower speed processor. And also serves to queue messages exchanged between the different systems (= network system and processor system) .The microprocessor bus interface / control circuit 126 It can be said to be for performing a (read / write function: R / W function) in cooperation with a microprocessor system, which microprocessor system (at least if it is of the Intel 8086 type) ) Ability to write data directly to HS RAM 26 " , And a capability to receive data from the H. S. RAM 26 ".

The structure of the IFP and the structure of the AMP are similar to each other with respect to their operation. However, the size of the input message storage area and the size of the output message storage area inside the HS RAM 26 "are different. There may be considerable differences between IFPs and AMPs in relational databases.In a relational database system, IFPs need to be able to constantly use the network to meet the needs of host computers. Inside the HS RAM 26 "is a large input message storage space for receiving new messages from the high speed network. The opposite is true for AMP because more storage space must be made available for processed message packets that are sent out to the high-speed network. HS RAM 26 "is a microprocessor
It also operates in cooperation with a main RAM 107 in the system 103, which has a message buffer section for each network.

The manner of allocating the system address space inside the main RAM 107 for the microprocessor system 103 is shown in FIG. 19, which will be briefly described. In accordance with a general scheme, an address assigned to the system random access function to leave space for expansion to be used when storage capacity for random access is increased, and an I / O address space And an address space allocated for ROM and PROM (including EPROM) functions. Further, some portions of the system address space may be divided into first and second high speed RAs, respectively.
M26 ', 26 "and the message packets sent to the high-speed RAM.
Assigned for packets. This provides great flexibility in the operation of the system, even though the microprocessor 105 can address the HS RAM 26 ",
This is because the function of 107 makes it possible to hardly be restricted by the interdependency between software and hardware.

Referring again to FIG. 18, as previously described, the HS RAM 26 ", which can be accessed from two directions, provides multiprocessor mode control, distributed updates, and message packets. In order to achieve these and other objectives, the HS RAM 26 "is divided into a number of different internal sectors to accomplish these and other objectives. I have. The aspect of the relative arrangement of the various sectors shown in FIG. 18 is that employed in all of the individual processor modules in the system, and specifies the boundaries of those sectors. The specific address indicates an address used in an actual system. It should be noted that the size of these memory sectors and their relative placement can vary greatly depending on the specific system situation. In the illustrated example, a 16-bit memory word is employed. The selection map and response directory are dedicated look-up tables of the kind that need to be written only once during initialization, while the transaction number section is dynamically revisable (= You can change the contents many times while you are
Offering a table.

The memory section of the selection map starts at location 0, but in this example there are basically four different maps used inside this memory section, Are used in an interrelated manner. The destination selection word (DSW) included in the message packet is H.264.
S. RAM 26 "in conjunction with a dedicated selection map. This destination selection word consists of a total of 16 bits, of which 12 bits.
It is intended to include the map address occupying the position and the map selection data occupying the other four bits. The first 1024 16-bit memory words of the HS RAM each contain four map address values. A single memory access to the HS RAM in accordance with the address value specified in the DSW provides map bits for all four maps, while containing the map bits for the DSW. The selected map selection bit determines which map to use.

FIG. 26 shows the conceptual structure of the map section described above. In FIG. 26, each map is physically separated from each other by 4096 × 1 bit R bits.
It is shown as if it consists of AM. For convenience in implementation, it is convenient to have all map data stored in a single portion of the HS RAM, as shown in FIG. DS
The W management section 190 (FIGS. 23 and 24)
S. controls the multiplexing operation on the four bits from each of the four maps of FIG. 26 obtained from one 16-bit word of the RAM. As will be appreciated by those skilled in the art, the advantage of this scheme is that the H.S.R.
The processor can initialize the map using the same means used to access the other parts of the AM.

Furthermore, three different classes (classifications) of destination selection words are used, and correspondingly, the storage location of the selection map is a hash selection part, a class selection part, and a destination processor identification information. (Destin
ation processor identification (DPID). This DPID is stored in the processor 1
05 specifies whether the message processor is a specific processor to which the message packet is to be transferred. In contrast, the class selection portion is whether the processor is one of a plurality of processors belonging to a particular processing class to receive the message packet, that is, is a member of the processor group. This is to specify whether or not. The hash value is stored according to the distribution method when the database is distributed inside the relational database system,
This distribution method follows the algorithm for a specific relation and the distributed storage method adopted in the system. When specifying a processor, the hash value in this specific example can be specified as having one of a primary responsibility and a backup responsibility for the data. ing. Therefore, the HS RAM 26 "is directly addressed by the plurality of selection maps to determine whether or not the processor is the transfer destination.
You can take the method. This feature is complementary to, and complementary to, the method of broadcasting prioritized messages to all network interfaces 120, and localizing the status of microprocessor 105 without interruption. It is also a function that allows for dynamic access.

One section of the HS RAM 26 ", independent of the other parts, serves as a central means for checking and controlling globally distributed activities. As already mentioned, FIG.
The transaction number (TN) for each of the various processes sent to and received from the network 50b, as shown in FIG.
Is assigned. The reason why the TN is included in the message is to provide a global transaction identity (transaction identification information) when each processor system 103 executes subtasks received by itself independently of each other. HS RAM2
6 ", a dedicated block for storing the addresses of a plurality of available transaction numbers is a status entry that is controlled and updated locally by the microprocessor system 103 in performing its subtasks. (= Entry for status), the TN uses the
It is used in a variety of different applications, both locally and globally. Transaction numbers are used to identify subtasks, invoke data, provide commands, control message flow, and identify the type of global processing dynamics. Transaction numbers can be assigned, abandoned, or changed during execution of global communications. These features are described in further detail below.

Among the TN features, the most complex, but probably the most effective, is the cooperation of a sort network (a network with a sorting function) to provide a local network for a given control operation. Its ability to enable distributed updates of the status of processors (= individual processor modules). Each control process (ie, task or multiprocessor activity) has its own TN.

The value of the readiness state (the state in which the processor is ready to operate) is H.
The readiness state value is stored locally (= in the individual processor module under the control of the microprocessor system 103) in the transaction number section of the S.RAM 26 ". Microprocessor system 10
3 is an appropriate entry (for example, SACK / Busy) in the response directory of FIG.
(Hex))), and by transferring the image as replicated, the status of this SACK / Busy
To the HS RAM 26 ". The entry entered at a certain TN address (= storage location corresponding to the transaction number) is A in the HS RAM 26".
It can be accessed from the network 50b via the port and the B port, and via the interface 120 '. The query is
"Status request" including command code (see FIG. 21) of request (status request) and TN
This is done using messages. Interface 12
0 'refers to a response directory storing a response message written in an appropriate format using the content stored at the TN address of the designated TN. Global status query for a given TN
Receive a direct response, which is only under hardware control. No pre-communications are required, and the microprocessor system 103 is not interrupted or affected.
However, if status is set by transmitting a "lock" indication to interface 120 ', microprocessor system 103 disables the interrupt and
0 'will continue to communicate the lock word from address "0501 (hex)" until its exclusion occurs later. The word format in the readiness state is shown in seven states from “busy (state during operation execution)” to “initial (initial state)” in FIG. 22, and FIG. 1 illustrates one useful embodiment employed in certain systems.
It is possible to change the readiness status into more or less types,
By using the seven types of states shown in the figure, a wide range of control suitable for many uses can be performed. H.S. RAM 26 "continuously updates the state level of each TN (= readiness state level represented by the entry stored at each TN address), thereby making subtasks available. It is the responsibility of the microprocessor system to reflect the nature and progress of the processing of the subtasks, and such updates are made using the format shown in FIG. This can be easily performed by writing to the TN address in the RAM 26 ".

In FIG. 20, each status response (status response) from "05" to "0D" (hexadecimal) has a status acknowledgment command code (status acknowledgmen) at the beginning.
t command code: SACK). Those SACK responses sent out to the network are actually
The command code of FIG. 20, the numeric portion of the word format of FIG. 22, and the source processor ID (OPI
D), which is as shown in FIG. Therefore, those SACK responses form a group of priority subgroups within the overall priority convention shown in FIG. O
PIDs have meaning with respect to priority conventions, for example, if multiple processors are working on a TN but none of them is in a "busy" state, then broadcasted This is because the determination of the highest priority message is made based on this OPID. The transfer and the coordination of the system can be performed based on this data (OPID).

[0120] The priority rules are defined for the SACK message (= SACK response), the responses are sent from a plurality of microprocessor systems 103 at the same time, and the network 50b dynamically By allowing the priority determination to be made (while making the transmission), the determination of the status of the global resource for a given task in a greatly improved manner compared to conventional systems. Is being done. The resulting response is unambiguous and never represents an unspecified state, nor does it require any software and does not waste time on the local processor (= individual processor module). . Thus, for example, deadlocks are never caused by frequent status requests that prevent execution of a task. At various status levels, many optional operations of the multiprocessor are available. It was never before possible that local processors could continue to operate independently of each other and that a single query would elicit a single, global, prioritized response. .

The series of states shown in FIG. 22 will be described in some detail here to help understanding. "Bizy" state and "waitin"
g: wait) state is a state in which the assigned, or delegated, subtask is going to progress to a stage closer to completion, and the "waiting" state is for further communication. Or a state requiring an event. These "visi" and "waiting" states are levels in which the status of a TN rises to a higher level, and eventually reaches a status level at which message packets for that TN can be transmitted or received. It shows an example of a rise.

On the other hand, when transmitting or receiving a message packet, another characteristic of the TN is as follows.
The TN's ability in message control will be demonstrated. When the microprocessor system 103 has a message to send, the status indication changes to "send ready". In addition to updating the status display, the microprocessor system 103 uses the word format of FIG. 22 to change the value of the "Next Message Vector" to the HS RA.
M26 ". The input entry specifies from which location in the HS RAM 26" the corresponding output message should be taken.
This vector is used to connect (= chain) a plurality of output messages related to a specific TN to a network interface 120 ′.
Is used internally.

The functions associated with the above functions are performed during the "receive ready" state. In the "ready for reception" state, the input message count value obtained from the microprocessor system 103 is held at the storage location (= TN address) of the TN. Is a value related to the number of messages that can be received for a given TN. This count value is decremented as input messages are successively transferred, and may eventually become zero.
If it reaches zero, no more messages can be received and an overrun condition will be indicated. As described above, using the TN, the network 50b and the microprocessor system 103
The speed of transmission between the two can be adjusted.

To explain the local (= individual processor) aspects, in each individual processor, during the execution of the processing, the TN is included in the transmitted and received messages in a system-wide constant. It is held as a constant standard. "TN0" state,
That is, the default state is that the message is not merged.
It also serves as a local command to indicate the fact that mode should be used.

From a global perspective, "TN
By distinguishing between “0” and various values of “TN> 0” as having different properties, one command function among a plurality of command functions using TN is defined. . That is, by distinguishing the TN in this manner, a characterization representing either “merge / non-merge” is attached to each message packet, whereby a plurality of messages are added. An effective system operation method of determining priority and performing sorting is obtained. Similarly, “Assigned (assigned state)”, “Unassigned (Unas
Global intercommunication and control functions are performed using the statuses "signed: unassigned", "Non-Participant", and "Initial". An "unassigned" state is a state where the processor has previously abandoned the TN, and thus needs to receive a new primary message to re-activate the TN. If the processor displays "Unassigned" when the status display should be "Assigned", then this indicates that the TN has not been properly entered and a corrective action is taken. There must be. If the TN is "assigned" when it should be "unassigned", this means that either an incomplete transfer has occurred or a new TN
May be an indication that there is a conflict between the two processors. Neither of these “assigned” and “unassigned” are treated as a readiness state, because at the time they are being displayed, the processor has not yet started working on the TN. It is.

Further, the "initial" state and the "non-participating processor" state are also important in relation to global resources. A processor that is about to go online, that is, has to undergo a subscription to this system, is in an "initial" state, which means that the processor must be administratively in order to be online. Indicates that you need to take steps. Processors that are in the "non-participating processor" state for a given task need not perform any processing locally, but
However, it is necessary to keep track of this TN so that it is not inadvertently used inappropriately.

Referring again to FIG. 20, H.S.
The dedicated directory or reference section of the RAM 26 ", in addition to the types described above, also includes a number of other types of prioritized messages used to generate responses in hardware. The entry NA (not assigned) is prepared for future use,
It is kept in a usable state. The three different types of NAK responses (overrun, TN error, and Locked NAK responses) have the lowest data content and therefore have the highest priority, but they have the highest priority. NAK response indicates an error condition. A plurality of SACK responses are followed by an ACK response and a NAP response (non-applicable processor response), which are arranged in order of decreasing priority. In the configuration of this specific example, two response commands
The codes have not been assigned a function (ie, NA) and they are ready for future use. Because the directories described above can be initialized by software and used by hardware, any of a wide variety of response message texts can be generated quickly and flexibly. Can be.

Using one independent part in the above directory that is independent of the other parts, the TO
The respective addresses of P, GET, PUT, and BOTTOM are stored, that is, a pointer regarding the function of the circular buffer for the input message and a pointer of the completion output message. These pointers function in cooperation with the respective dedicated sectors of the HS RAM 26 "which are respectively used for managing the input message and for managing the output message. To do this, a circular buffer method is used,
In this case, "TOP" stored in the directory section of the HS RAM 26 "is a variable address that specifies the upper limit address position for the input message. The PUT address stored in the same directory section specifies the address location where the circuit should store the next message to be received. The GET address is set and updated by the software so that the software can recognize the address position where the buffer is blanked by the hardware.

The input message buffer is managed by PU
Set T to the bottom address of the buffer,
Then, it is performed in such a manner that it starts from a state where the GET address is equal to TOP. The operational rules set by the software are as follows:
That is, it must not be set to a value equal to UT, and if it is set, an indeterminate condition will occur. When an incoming message is entered into the incoming message buffer in HS RAM 26 ", the message length value contained in the message itself determines the starting point of the next incoming message. Then, a change is made to the PUT address stored in the directory to indicate the storage location in the buffer to receive the next incoming message. The input unit 103 can take out an input message when its own work ability permits.

The data stored in the output message storage space in the HS RAM 26 "includes the output message completion vector held in a circular buffer independent of the other parts, and the HS RAM 26. Used with the next message vector in ". Editing (assembling) and storing of individual messages can be performed at any location, and a plurality of messages related to each other can be connected (chained) to send them over a network. I can do it. HS RAM
26 "directory section, TOP, BO
The respective addresses of the TTOM, PUT, and GET have been entered and updated as previously described, thereby maintaining a dynamic current indication of the location in the output message completion buffer. The message completion vector constitutes an index address for pointing to a message stored in the output message storage space and indicated by the received response that the transfer has been properly performed. ing. As will be explained, this system facilitates the input of output messages by the microprocessor system 103, while the microprocessor system 103 organizes complex concatenated vector sequences in an orderly manner. In order to make efficient use of the output message storage space and to enable the transfer of message chains.

The protocol of FIG. 21 described above with reference to the response also defines the primary message following the response. A plurality of types of response messages are arranged consecutively with each other, and hexadecimal command codes are shown in ascending order. Within the group of primary messages, the merge stop message (which is also the basic control message, the non-merge control message) has the lowest data content and therefore the highest priority. is there. This message constitutes a control communication that terminates the merge mode in the network as well as in the processor module.

A very large number of different types of primary data messages can be used with ascending priorities, and based on application requirements and system requirements. Classifications for priorities can be added. As mentioned earlier, a continuation message that follows another message may be given a higher priority to maintain continuity from the preceding message packet. it can.

The lowermost group in FIG. 21 consisting of four types of primary messages is the only type of status message that requires a status response from higher priority to lower priority. , A control message requesting "TN abandonment" and "TN allocation", and a lower priority "merge start" control message.

As described above, as will be apparent from the more detailed specific examples described later, the above configuration enables operations that can be used for many purposes. The processor module has a current transaction number (present transaction nu
mber: PTN)
In this case, the same is true whether the PTN is specified externally, by command from the network, or generated internally while performing a continuous operation. It is. When a merge operation is being performed, the processor module is performing the operation using a global reference, i.e., a transaction identity (= information to identify the transaction), and this transaction identity is It is determined by TN.
Starting, stopping, and resuming the merge operation is done using only simple message changes. The subtask is
If it is not necessary to merge the messages, or if a message packet having no particular relation to other messages is generated, those messages are output to "TN0". The transfer is performed while the base state, or default state (which is zero), currently determined by the transaction number, remains true, forming a queue. This "TN0" state
When the merge mode is not used, it allows messages to be queued for transfer.

(Network Interface System) Reference is now made to FIGS. 23 and 24, which show a more specific example of an interface circuit suitable for use in the system of the present invention. . Although the description in this "Network Interface System" section includes a number of detailed features that are not necessary for an understanding of the present invention, those features are:
It is built into the actual system and has therefore been included in the description to clarify the positioning of various embodiments with respect to the subject matter of the present invention. Descriptions of specific configurations and detailed structures for gating, which are not the subject of the present invention and relate to well-known means, may be omitted because various alternative configurations can be adopted. Or decided to simplify it. FIG.
3 and 24 illustrate the second network interface 120 'shown in FIG. S. RAM
26 ". The respective interfaces 120, 120 'for the two networks function in a similar manner to each other, and therefore only one need be described.

23 and 24, the input from the active logic network 50 connected to the interface shown in FIG. 23 is transmitted via a multiplexer 142 and a known parity check circuit 144 to a network message management. The signal is supplied to a circuit 140. Multiplexer 142 is further connected to the data bus of the microprocessor system, which allows access to message management circuit 140 via this data bus. With this feature,
The microprocessor system is capable of operating the interface in a step-by-step test mode, and the data is transmitted as if the interface were connected to the network online. Is transferred. The input from the network is supplied to the receiving network data register 146, where the byte data input directly to the first section of this register 146 and the receiving byte buffer 14
8, the byte data input to the register 146 is received, and the receiving byte buffer 148 stores the first byte data.
After inputting byte data to this section, its own byte data is input to another section of this register 146. This will cause both of the two bytes that make up each received word to be input to the receiving network data register 146 and kept there available.

The output message to be transmitted is input to the transmission network data register 150, and a parity bit is added inside the ordinary parity generation circuit 132. The message is sent from the network message management circuit 140 to the network connected to it, or (if the test mode is used) to the microprocessor system data bus. For the purpose of managing messages inside this interface,
The format of the transmission message stored in the random access memory 168 includes not only message data but also identification data. FIG.
As can be seen from (a), all of the commands, tags, keys, and DSWs are transmitted in the primary
Can be combined with data.

The configuration shown in FIG. 23 and FIG.
18 is essentially the same as that shown in FIG. 18, except that the interface data bus and the interface address bus S. RA
M26 "is separately connected to input port A and input port B, and the address bus and data bus of microprocessor system 103 are shown connected to independent C ports. However, in practice, as can be seen from FIGS. 23 and 24, such an access from two independent directions is performed by the HS RAM 2 which is performed inside this interface.
6 "is accomplished by time division multiplexing of the input and output address functions. The microprocessor's data bus and address bus are connected to the respective buses of the interface via gates 145 and 149, respectively. That allows the microprocessor to operate asynchronously based on its own internal clock.

The adopted timing system is based on a clock pulse, a phase control waveform, and a phase subdivided waveform, and the phase subdivided waveform is used in the interface clock circuit 156 (FIGS. 23 and 23). 24) and has the timing relationship shown in FIG. 25 (FIG. 25 will also be described later). Interface clock circuit 156 is receiving the network word clock from the nearest node and has a phase locked clock source 1
57 includes means for maintaining zero time skew as described above in connection with FIG. 24
Nominal network word in 0 ns network
The clock speed is set to the interface clock circuit 15
6, which is subdivided in time by a frequency multiplier (not shown in detail) held in phase locked state by a high-speed clock defining a reference period of 40 ns duration (Shown as PLCLK in FIG. 25). The basic word period is determined by a periodic signal denoted by CLKSRA in the figure, which has a full period of 240 ns and is inverted every half cycle. Two other signals having the same frequency and duration as CLKSRA are generated by the frequency divider 158 based on PLCLK, and these signals are respectively generated for one cycle and two cycles of PLCLK from CLKSRA. , And are given the names CLKSRB and CLKSRC, respectively.

On the basis of the various signals described above, the control logic 159 determines “IO GATE”, “RECV GAT”.
E "and" SEND GATE "(hereinafter also referred to as a gate signal), and these timing waveforms indicate each of three successive intervals of a word period that are successively divided into three. Things. These intervals include the “IO Phase”,
Applicable names such as “reception phase” and “transmission phase” are given. Each of these phases, defined by the gate signal, is further described as "IO CL
K ”signal,“ RECV CLK ”signal, and“ SEN
The D CLK "signal has subdivided it into two equally halved half-intervals, which define the second half of each phase. The byte clocking function uses the "BYTE CTRL" signal and the "BYTE CTRL" signal.
CLK ”signal.

In the IO phase, RECV phase (reception phase), and SEND phase (transmission phase), the random access memory 168 and the bus of the microprocessor system are time-division multiplexed (time multiplexing). It provides the basis for performing the required actions. The interface can only receive or transmit one word per word period to and from the high-speed network, and obviously, the reception and transmission never occur at the same time. The transfer rate for transfers to and from the microprocessor system is significantly lower than the transfer rate to and from this network, but even if both are of equal speed, it is excessive for the capabilities of the interface circuit. There is no burden. The configuration of this interface system is such that most operations are performed by direct access to the random access memory 168, so that little internal processing or software is required. It has become. Thus, as the system periodically progresses through successive phases in each word period, the words are determined one after the other and without colliding with each other. , Thereby performing various functions. By way of example, messages may be sent to the bus in the interval between receipt of messages from the microprocessor, and each of them may be alternated using a different portion of memory 168. Can be.

The data of the microprocessor system
The intercommunication between the bus and the network interface is based on the IO management circuit 160 (reading out of this IO /
Write (also referred to as Read / Write). A write gate 162 for gating words coming from the microprocessor system;
A system read register 164 for sending words to the microprocessor system provides a connection between the microprocessor bus and the bus interface to the network interface.

Further, a memory address register 165 and a parity generator / check circuit 166 are incorporated in the network interface subsystem. In this specific example, the high-speed memory (= HSRA
M) is 4K words x 17 bits random access
The memory 168 is internally re-partitioned, and the use of a plurality of dedicated memory areas provided inside the memory is as described above. The size (= capacity) of the random access memory can be easily reduced or expanded according to the needs of each specific application.

Received message buffer management circuit 170
Are connected to the data bus of the microprocessor and also to the address bus of the memory 168. The term "received messages" is sometimes used to refer to messages coming from the network and entering a storage location "PUT" in a circular buffer;
Also, after this entry, the message so entered into the circular buffer is transferred to the microprocessor, but may be used to indicate that transfer. When this transfer is made to the microprocessor, the value of "GET" specifies from which location the system should perform a continuous fetch operation in performing the fetch of a received message to be transferred to the microprocessor system. . Random access
A plurality of address values used for accessing the memory 168 are stored in a GET register 172, a TOP register 174,
It is input to the UT counter 175 and the BOTTM register 176, respectively. The PUT counter 175 is BOT
It is updated by being incremented by one from the initial position specified by the TOM register 176. The TOP register 174 gives an index of the boundary on the other side. Both the value of TOP and the value of BOTTM can be manipulated under software control, thereby increasing the size of the received message buffer and the H.264. S. It is possible to change both the absolute storage location in the RAM. When the contents of the PUT register equal the contents of the TOP register, the PUT register is reset to equal the contents of the BOTTOM register, thereby making this buffer available as a circular buffer. The GET register, TOP register, BOTTOM register, and PUT counter are used to manage both the input message circular buffer and the output message complete circular buffer.

The input to the GET register 172 is made under the control of software, which determines the next address (next address) in the buffer according to the length of the message currently being handled. Because. Comparison circuits 178 and 179 connected to the respective outputs of the GET register 172, PUT counter 175, and TOP register 174 are used to detect and display an overrun condition. The overrun state is a state that occurs when the value of GET and the value of PUT are set to the same value, or when an attempt is made to set the value of GET to a value larger than the value of TOP.
In either of these cases, an overrun status indication will be sent, and this status indication will continue to be sent until the overrun condition is corrected.

The above-described continuous scheme for configuring and operating the "received message" circular buffer is a scheme particularly suitable for this system. Collision
The PUT can be managed by hardware and the G
ET "can be dynamically managed. However, other types of buffer systems can be employed. However, in that case,
Probably there will be some extra burden on the circuit and software. Here, FIG.
Note that the format of the received message stored within memory 168 further includes identification data in the form of map results, data lengths, and key lengths, and how those data are Whether it can be obtained will be described later.

The DSW management section 190 inside this interface includes a transfer destination selection word register 1
92, and this destination selection word register 1
To 92, a transfer destination selection word (DSW) to be transferred to the address bus is input. When the dedicated DSW section of the memory 168 is addressed using the DSW, the output sent from the memory 168 onto the data bus returns the data, and based on the data, the DSW management section 190 sends the message packet to the relevant processor. It can be determined whether or not this is the transfer destination. As can be seen from FIGS. 23 and 24, the transfer destination selection word is composed of a 2-bit map nibble (nybl) address and a 10-bit map word
It consists of an address and 4 bits for map selection. The “nibble” address of these is
It is used to describe a subsection of the word from 68. The four bits for the map selection are provided to a map result comparator 194, which receives the associated map data from memory 168 via multiplexer 196. Multiplexer 196 is 1
6 bits of data are received, the 16 bits being the four different map data stored at the address specified by bit 10 of the map word address contained in the DSW. Represents a nibble. The memory 168 has its dedicated map section configured in a form particularly suitable for comparison so that the comparison performed here is easy. The remaining two in the DSW are provided to the multiplexer 196 for its control.
Depending on the bit, a corresponding one of the four map nibbles is selected. A comparison is made and the map code resulting from the comparison is input to map result register 197 and inserted into the input message being input to memory 168. If the comparison shows that there is no "1" bit in any of the selected maps, a "reject" signal is generated and the processor module causes It is indicated that the message packet is not intended to be received.

Referring to FIG. 26, there is shown in FIG. 26 a schematic diagram of a preferred method for subdividing the dedicated destination selection section of the memory 168 and for comparing the map results. Is shown in FIG. Each map is composed of 4096 words x 1 bit.
Further, it is subdivided into an individual processor ID sector, a class ID sector, and a hashing sector (FIG. 18).
reference). When a common map address is selected using twelve address bits (a 10-bit map address and a 2-bit nibble), one bit output is obtained from each map. (The multiplexers of FIGS. 23 and 24 and their nibbles are not shown in FIG. 26 for clarity). The four parallel bit outputs can be compared with four bits for map selection in an AND gate group 198 consisting of four AND gates, so that one or more matches are obtained. In this case, the output of the OR gate 199 becomes "true". This map result is shown in FIG. 23 and FIG.
4 can be input to the map result register 197,
This allows the message to be accepted into memory 168. If not, the message is rejected and a NAK is sent.

Command / word management section 200
Is the command register 20 that receives the command word.
Contains 2. The TN field of the command word can be used to access the address bus, and the access causes the received T.N.
N is examined to determine an appropriate response message (see FIG. 30). Further, when the “merge start” command is being executed, a data transfer path from the TN field to the PTNR (current transaction number register) 206 is secured, which corresponds to the “merge start”.
This is so that the value of the PTN (current transaction number) can be changed according to the command.

The input message input to the memory 168 will be described with reference to FIG. 34, in order to make available the address vector, the data field and the key field, if any, are used. It includes the length value. Their length values are determined by a receive data length counter 210 and a receive key length counter 211, each of which is used when the input source provides a field corresponding to the respective counter. Field counts the number of words in the sequence.

Further, the transmission message management section 2
20, the section includes an accept function for storing processed packets in the memory 168;
Sending the stored packets to the network later. This section 220
It includes a transmit transaction vector counter 222, a transmit data length counter 224, and a transmit key length counter 226, which are bidirectionally connected to the data bus. The transmit transaction vector counter 222 is connected to the address bus, while the transmit data length counter 224 is connected to an address generator 228, which is further connected to the address bus. I have. The message is transmitted using both the output buffer section and the circular buffer constituting the output message completion vector section of FIG. However, in this example, after a plurality of message packets are sequentially input, they are now fetched in the order defined by the vector.

Inside this interface,
The independent operation phases are executed at mutually exclusive times, and by adopting such a time division method, the memory 168 stores message packets from the network at the network clock speed. Receiving and supplying data, performing internal operations at an efficient high speed, and communicating with a microprocessor system operating asynchronously at its own slow clock speed. And is possible. In order to control the gating operation of messages to various counters and registers, a phase control circuit operates in response to control bits, which control commands, DSW, data, and individual It generates other signals indicating the field. Transmit state control circuit 250, receive state control circuit 260, and R / W (read / write) state control circuit 270 receive clock pulses, identify fields in the data, and transmit, receive, and It controls the sequencing of the data flow during the clock operation.

The control of this interface is performed by three finite state machines (FSMs).
Are for the transmit phase, the receive phase, and the processor (R / W) phase, respectively. These FSMs are programmable logic arrays (PLs).
A), using a status register, and an action ROM, in a general manner. Each FSM is
Each clock cycle of the network advances to the next state. Due to the large number of control signals to be generated, the output of the PLA is further encoded by the action ROM. As will be readily appreciated by those skilled in the art, the translation of a control sequence written for the FSM mode, and thus having general details and operation, which is necessary for the operation of the network, It is a simple task with a lot of work.

The state diagrams of FIGS. 28 and 29, 31 and 32, and the matrix diagram of FIG. 30 are included in the accompanying drawings because of the internal structural design that can be employed in fairly complex systems. The purpose is to present comprehensive details on the characteristics of

FIGS. 28 and 29 are diagrams related to the reception phase, and FIGS. 31 and 32 are diagrams related to the transmission phase. It corresponds to the notation used. For example, the following terms:

RKLC = Receive Key Length Counter RDLA = Receive Data Length Counter RNDR = Receive Network Data Word Register PUTC = Put Counter (PUT counter) GETR = Get Register (GET register) Accordingly, the state diagram can be understood substantially without explanation if it is referred to in comparison with FIGS. 23 and 24 and the specification. The state diagrams detail the various sequences and conditionals involved in complex message management as well as interprocessor communication. FIG.
In FIG. 29 and FIG. 29, the respective states in which the labels “Generate a response” and “Decode the response” are written, and the respective conditional statements indicated by broken-line rectangles are shown in FIG.
According to the specified response and operation described in the matrix diagram of FIG.

FIG. 30 shows DATA (data), STOP (stop), and S of a primary message (primary message) related to a predetermined transaction number (TN).
TATUS (status), RELQ (abandoned), ASG
N (allocation) and STRT (start) and the corresponding response messages LOCK (lock), TNER (TN error), OVER (overrun), nine different status responses corresponding to FIG. 22, and ACKR (confirmation) response)
And the combination relationship with the NAPR (no corresponding processor response). As for the dotted lines in the table, the upper part of the dotted line indicates a specific response, and the lower part of the dotted line indicates a specific process. The meaning of the symbols used in the table is listed below the table. The primary message always has a transaction number (TN) regardless of a data message or a control message.

When a primary message having a certain TN is transmitted via the network, the network interface section 120 of each station generates various response messages according to the processing status of the subtask related to the TN. The response message used in the system according to the present invention is a positive response (AC
K), negative acknowledgment (NAK), or the data
A non-compliant processor response (NAP), which is a response indicating that the device has no resources, is used. There are several different types of NAK responses, such as stop (LOCK), TN error (TNER), and buffer overrun (OVER).
It depends on such factors.

Here, the processor in its own station uses a status acknowledgment (SACK) indicating the ready state for transmission with respect to the processing of a specific task. The signal indicating the SACK is used together with a specific primary message to perform various protocols, for example, system initialization and lockout processing. As shown in FIG. 21, the SACK response has nine status levels indicating different meanings, and its word format is as shown in FIG. It is the responsibility of the processor in a station that is in charge of a plurality of sub-task processes related to a plurality of TNs to constantly update the status level of each sub-task process as the process progresses. is there. In FIG. 22, the states of “Bizy” and “Waiting” indicate that the state is moving to the next phase with respect to the specific subtask assigned together.

If the processor module 103 had a message to send, its status is "ready to send". "Ready to receive"
It indicates that the processor module can accept a message having a preset TN. The plurality of TN values to be used are preset in the HS RAM of each station in advance, but are discarded during operation or new TNs are allocated. “Assigned” and “unassigned” are responses indicating whether or not the TN is set in the station.

As described above, since the TN for making each station in the system synonymously recognize what task the transmission message relates to is included, even if a certain message is collectively transmitted in the network, In this station, it is possible to specify which task the transmitted message relates to, so that a plurality of tasks can be processed simultaneously in the system.

In FIG. 28 and FIG. 29, and FIG. 31 and FIG. 32, as for the condition judgment, many of them can execute a plurality of judgments at the same time. The state steps are changed one by one. In any case, the transmission operation and the reception operation are operations that proceed at a predetermined traveling speed without requiring external control,
This is because the structure of the message and the operation method of the network have already been described.

Many of the features employed in typical processor and multiprocessor systems are not closely related to the present invention and will not be described in particular. Among these features are parity error circuits, interrupt circuits, and various means for monitoring activities such as watchdog timers and a wide variety of test functions.

Here, a description will be given of a case where a plurality of tasks are handled simultaneously in the system according to the present invention.

All the messages transmitted and received between the processors constituting the computing system according to the present invention have a message format as shown in FIG. 13, and as shown in FIGS. The part has a command word consisting of a 6-bit command code and a 10-bit tag field.
Further, as shown in FIG. 21, the 10-bit tag
In the field, the transaction number (TN) if the message is a primary message, or the source I if the message is a response message to the primary message.
It always has a D number (OPID). A message sent to the communication network to cause a predetermined processor or processors to process a certain task is a primary message, and the task is identified by the identification number TN. The plurality of TN values to be used in each processor are stored in the high-speed RAM in each component processor.
(HSRAM), it is normally initialized to a predetermined address (0400 to 0500 in HSRAM in FIG. 18). The TN value can be assigned or abandoned on the way by a predetermined command code (command code) as a primary message (FIG. 21).

The primary message has, in addition to the TN, a destination selection word (DSW) for directly or indirectly indicating one or more destination processors from which the message is to be received (FIG. 13). A and B). Thus, by using various combinations of TN, DSW and command codes, a wide range of inter-system communication capabilities can be achieved. Primary messages are roughly classified into two types. One is for distributing a certain task or transmitting a processing result accompanying data of a certain task to another processor, and has a key field data message of variable length data and a data field. Data message ”(first
3 (FIG. A, FIG. 21). The other is to query the status of the processing result of the task message, allocate a new TN before sending the task message, or relinquish the used TN, or query the status. When a positive response is received from all the processors related to the task processing related to the specific TN, the “control / status” for instructing to start or stop the merge, which is a command to transmit the processing results all at once, is received. Message ”(FIG. 13B, FIG. 21). In this embodiment, as shown in FIG. 21, eleven command codes ("1") are used to transmit the data message (primary message) to which different specific TN values are assigned.
1 "to" 1B ") can be used simultaneously.

The TN described in the tag portion in the command code of the final primary message sent to itself regardless of the data message or the status message is handled as the current TN, and Is updated and stored by the interface itself in the current TN counter (206) in the network interface (FIGS. 18, 23 and 24) in each processor. As described above, each constituent processor in the system always includes the TN in the primary message, even if it is related to a plurality of task processes. Therefore, what kind of task control or status response is required by this? And transmits a response related to the requested TN in a response message format (command codes “00” to “0F” in FIGS. 13C and 21). Since the command code related to the response message has a smaller value than the command code related to the primary message, the command code is preferentially transmitted in the network, and its transmission source is O.
Specified by PID.

As shown in the block diagram of FIG. 18, in each station, the network interface 120 is provided separately from the processor module 103.
Working synchronously with the active logic network,
Messages sent from a communication network having a full-duplex communication configuration are H.264. S. The data is sequentially stored at a predetermined address in the RAM. In addition, the interface transmits a response related to a predetermined TN together with the reception at the timing of the network (17th
(Fig.). When a status request or the like is received, transmission of a response message related to the current TN is given top priority. Processor module 10 in each station
H.3 in the station. S. The messages stored in the RAM are sequentially taken into its own main RAM 107, necessary processing or search is performed, and the result is output as an output message. S. The data is sequentially stored at a predetermined address in the RAM. In this way, the processor module 103 receives the message from the network and sends the message to the H.264 module. S. It is not directly related to the storage in the RAM and the control of sending the processing result or response message to the network, and these are handled by the network interface.

The network interface 120,
H. S. RAM 26 and processor module 103
Since they are connected to each other by a time-division bus (FIG. 25), the interface 120 and the processor module 103, which operate in synchronization with the network, operate at their own timing. That is, each of them can access the HS / RAM without being involved in the other party's operation. H. S. The initialization, allocation, change, etc. of the DSW, TN, data message pointer and response directory stored in the RAM can be performed by another processor via a network. Access can also be made.

As described above, even if each station constituting the system is involved in a plurality of task processes at the same time, it can process and search for any task related to the primary message based on the TN in the received primary message. Or a status response is required,
The response related to the requested TN can be responded to by attaching a sender ID in a predetermined response message format. The source processor of the primary message recognizes from which processor these response messages are sent by the source ID.

As described above, a certain processor transmits a plurality of subtasks having the same TN to a given task as a primary message to a related processor specified by DSW, and transfers the processing of the subtask to each related processor. In the case of assignment, status inquiries (status requests) and processing result transmission requests (merge start) of the respective related processors are all performed with the TN attached to the subtask. Each station performs the processing of the subtask assigned to itself, and, together with the status, its own H.265. S. It is stored in a memory (circulating buffer) at a predetermined address in the RAM. When a status response or a processing result transmission request related to a specific TN is received, the network interface 120 in each station sets the TN as a current TN (PTN) and sends a response or processing result related to the TN to the network means 50. Send all at once. The response or the processing result sent to the network means is selected (sorted) in accordance with the priority protocol (FIGS. 2 to 12) each time it passes through a node in the network. The processing results of the subtasks related to the TN are transmitted successively (merged) in descending order of the priority of the message code. The processing result is transmitted to the network interface 120 of the station by the H.264. S. A series of processing results are stored in a predetermined range of addresses in the RAM.

(Specific Example of System Operation) The following describes FIGS. 1, 18, 23, and 2.
4 is a network and H.264 system. S. R
5 are some examples showing how to work internally in various modes of operation while working with AM. These examples illustrate how the inter-relationship between the precedence rules, the addressing scheme employed here, and the transaction identity can explain how both local control and global intercommunication functions. Indicates whether to provide.

Transmission / Reception of Primary Data Message FIG. 27 will be described below in addition to the other figures. FIG. It is a diagram. Even if a message is received in a buffer or memory, acceptance is not achieved unless the logical state shown is satisfied.
Although shown as a serial sequence of events in the figure, originally, a plurality of determinations are performed in parallel, that is, at the same time. Alternatively, an intermediate stage for reaching a certain operation stage may be performed by a circuit.

The messages on the network of FIG.
23 and 24 are passed through the receive network data register 146 until an EOM condition is identified, at which time the message is known to be complete. If the "LOCK" condition exists, the system proceeds to H. FIG. S. R
AM26 "and see NAK
Sends a / LOCK reject message.

Otherwise, that is, if the "lock" condition does not exist, the system moves to a map comparison check, which is performed inside the DSW management section 190 in the interface shown in FIGS. Executed in If there is a suitable comparison result, represented by "map output = 1", the system can continue to receive the message. If no such comparison exists, the message is rejected and a NAP is sent.

Once the appropriate map has been determined, the system is ready to check the TN status, which checks the TN directory shown in FIG. (Where TN status is strictly the status of the processor for a given TN,
Therefore, H. S. Readiness state represented by the entry stored at the TN address in the RAM). More specifically, this check of the TN status is based on the local status (= individual processor
This is performed to determine whether the status of the module is “ready for reception”. Here, it is assumed that the TN has already been assigned by a certain preceding primary message.

As a result of this inspection, TN indicates “execution end (don
e) If the status is found to be in one of the states "Non-participating processor" or "Initial", a "NAP" rejection message is sent out (where TN refers to TN). Strictly speaking, HS RA
This entry is stored at the TN address in M, but this entry will be simply referred to as TN unless there is a risk of confusion.) If the found status is any other out-of-spec condition, the reject message sent is a "NAK / TN error" and the two types of reject messages are also shown in FIG.
8 from the response directory. If the status was "ready to receive", yet another determination will be made.

This other determination relates to "input overrun", and as described above, this determination is performed within the input / output management buffer section 170 of FIGS. Address and PU
This is done by comparing with the T address. Furthermore, the transaction number is also checked for a non-zero received message count value, and if this count value is zero, it also indicates an input overrun. If an overrun condition exists, a "NAK / input overrun" is sent and the message is rejected.

If all of the above conditions are satisfied, H.P. S. An "ACK" message (acknowledgment message) is retrieved from the response directory in the RAM 26 "and sent out over the network, so that the priority is contested with other processor modules. Some of these other processor modules may have also sent acknowledgments to the received message. At this point, if the common response message received from the network (the "common" means merged) is an "ACK" message,
Accordingly, if it is specified that "all" processor modules selected as receiving processor modules are capable of accepting a previously received message, the received message is accepted. If the response is in any form other than "ACK", the previously received message is rejected by "all" processors.

In this example of receipt and response, after the primary message has been received,
All processors have an ACK response, a NAK response, and N
Note that it generates any one of the AP responses. As soon as the processor receives any one of these response messages, it can attempt to transmit the primary message. (The processor may also make this transmission attempt after a delay equal to or greater than the delay corresponding to the total latency to traverse the network, as already described in the "Active Logic Node" section. As you did). Another thing to note is that if several processors send "identical" messages to each other, all of those messages will have survived the contention on the network. Is also possible. In that case, "all" of those transmitting processors will receive the ACK response. This is important with respect to broadcast and global semaphore mode operation, which will be described in detail in a later example.

Examples of actual machines of the present invention actually used are as follows.
It includes many more types of responses in addition to those described above and performs various operations. FIG. 30 shows those responses and operations as LOCK, TN
Error and overrun interrupt states, nine different pre-identified status levels, and columns for acknowledgment (ACK) and non-applicable processor responses.

When a processor module is ready to send a message, it returns to P in FIGS.
The PTN value stored in the TN register 206 is ready for use, so all that is required is to confirm that the TN status is in the "ready to send" state. As can be seen from FIG. 22, the "ready to send" entry (entry) is the next entry for the output message.
Contains the message vector address. The output message that has been assembled is sent out on the network, and if contention is lost, this sending operation is repeated until a successful transmission, unless a PTN is changed, and a response is received if successful. become. If the transmission is successful and an acknowledgment is received, the address vector is changed. The next message vector is the second word in the current message (FIG. 34).
Retrieved from (a)), this word is transferred from the transmit transaction vector counter 222 to the random access memory 168. If the output message section is not overrun, PUT counter 1
75 is advanced by "1" and this overrun condition is
Indicated by UT being equal to GET.
The next message vector transferred from the transmission transaction vector counter 222 is H.264.
S. The transaction specified by the current transaction number register 206 in RAM
Input to the number address. If this new TN
If is in the "ready to send" state, the value of this input vector is again the value of the next message (the next message) associated with this transaction identity.
Message). H. S. R
See FIG. 34 for the format of the output message stored in the AM.

However, message management when sending a message can include many different forms of operation, including internal or external changes to the PTN. An error, overrun, or lock condition can cause the system to shift the transaction number to "TN0", which causes the system to return to non-merge mode, and then to "TN0" Will continue until the "ready to send" state is identified or a new TN is assigned. See the flowcharts of FIGS. 31 and 32 for conditions and conditions that can be employed in fairly complex embodiments.

Example of an Output Message Completion Buffer If the completion of the transmission of a message is indicated by any other response message except "LOCK", a pointer to the newly completed output message buffer is: H. S. It is stored in the output message completion circular buffer section of the RAM (see FIG. 18).
This pointer is simply a 16-bit word representing the address of the output message buffer. (The format of the output message buffer is shown in FIG. 34. Note that the output message buffer contains a place to record the response message received from the network.)

The output message completion circular buffer performs the function of communication between the network interface hardware 120 and the monitoring program located on the microprocessor 105. A program provided in the microprocessor transmits a message to be output from the microprocessor to H.264. S. Store in RAM. As will be described in more detail in the following example, a plurality of output messages are concatenated together (chained) together, with the TN acting as the leading pointer of this chain. Which can form complex sequences of operations. Another feature is that the network can be multiplexed or time-multiplexed between multiple TNs (also described in more detail below), so that the network can respond to various events that exist at various points in the network. The messages can be output in various orders.

Furthermore, the H.264 occupied by packets that have been successfully transmitted is used. S. It is important to quickly recover the storage space in RAM so that it can be reused for another output packet to be output. An output message completion circular buffer performs this function.

If the transmission of a data message ends successfully and a response other than a "lock" response is received,
The network interface is H.264. S. The PUT pointer (see FIG. 20) stored in “0510 (hexadecimal)” in the RAM is advanced by “1”, and the address of the first word of the output message whose transmission has just been completed is stored in the PUT register. To the address.
(If the value of the PUT pointer becomes larger than the value of the TOP pointer stored in “0512 (hexadecimal)”, P
The UT pointer is first reset to be the same as the BOT pointer (= BOTTOM pointer) stored in “0513 (hexadecimal)”. If the PUT pointer is larger than the GET pointer (storage location “0511 (hexadecimal)”), the circular buffer
It is overrun, so an "error interrupt" is issued to the microprocessor.

The output message buffer pointed to by the GET pointer is asynchronously examined by software running inside the microprocessor.
When the processor completes any processing requested to be executed, it advances the GET pointer by “1” (this G
When the value of ET becomes larger than the value of TOP, it is reset to the value of BOT.) If GET = PUT, there are no more output messages to process. Otherwise, further output messages have been successfully transmitted and must be processed. This process includes
H. S. This involves returning the storage space of the output buffer of the RAM to free space, so that this space can be reused for other packets.

It is important to note that the outgoing message completion circular buffer and the incoming message circular buffer are distinct from each other,
Two circular buffers, each with a separate PUT, GET, T
It is managed by each pointer of OP and BOT. Depending on the configuration, as shown in FIGS. 23 and 24, both circular buffers can share the circular buffer management hardware 170, but such a configuration is not essential. Absent.

Initial Setting Procedure Each processor module has a function of accessing the TN inside the high-speed random access memory 168 (FIGS. 23 and 24) of the processor module itself. Contains its directory of potentially available TNs. However, a TN that has not been assigned is assigned to a transaction stored in a storage location associated with the TN.
The number value clearly indicates that it has not been assigned. Therefore, the microprocessor system 1
03 identifies unassigned transaction numbers and selects one of them to use to initiate communication with other processor modules for a given transaction identity. can do.

The transaction number is the local
Locally assigned and updated under the control of a microprocessor (= microprocessor in a processor module), but global control throughout the network includes "TN abandonment instructions" and "TN allocation instructions" This is performed using the primary control message described above. There will never be a deadlock condition between competing processor modules that may require the same TN, because the network may be more susceptible to lower numbered processors. Is given priority. The remaining processors that tried to get the TN but did not get priority will receive a "NAK / TN error" response, which indicates that they have acquired another TN. Must be tried. Thus, complete flexibility has been obtained in securing and matching their transaction identities, both internally and locally. It should also be noted that repeated use of TN
This is done by shifting between the basic transmission mode which is "TN0" and the merge mode where TN is greater than zero. Thus, the system can change not only the focus of its operation, but also the nature of its operation, with only one broadcast transmission of the TN.

Yet another, and particularly useful, scheme for communicating global status changes is the forced parity error propagation described above with respect to FIG. This unique display scheme, when interleaved and transmitted between other transmissions, causes the aborted system resources to be examined and the appropriate action to be taken.

Processor-to-Processor Communication There are two types of special types of processor communication, one of which is communication directed to one specific destination processor, and the other is a plurality of communication belonging to one class. This communication is performed with the processor of the transfer destination. Both of these types of transmissions utilize DSW, and both of these transmissions are performed by non-merge mode broadcast.

In particular, when performing communication between one source processor and one destination processor, destination processor identification information (destination process information) is stored in the DSW.
r identification: DPID). FIG.
Referring to FIG. 8, the DP.ID of each receiving processor module is used by using the DPID value. S. RAM2
When the 6 "selection map portion is addressed, only the particular processor module intended for transfer will generate a positive response and accept the message. The positive response is sent and it is eventually Successfully received, both processors are ready to perform any of the required future operations.

When a certain message is to be received by a plurality of processors belonging to one class related to a certain control process, the H.264 / H.264 communication is performed by the map nibble and the map address in the DSW. S. The corresponding section in the selection map portion of the RAM is specified.
All the receiving processors then send out acknowledgments to each other, and the acknowledgments continue to reach the source processor module until the round trip for this communication is finally completed. become.

The global broadcast mode processor communication can be used for communication of primary data messages, status messages, control messages, and response messages. The inherent capabilities of both the priority protocol and the network with the ability to grant priority make it easy to insert such messages into sequences of other types of messages.

The processor selection in the hashing mode is as follows.
When executing a data processing task in a relational database system, a processor selection method is used which is by far the most frequently used. Primary data (=
A plurality of disjoint (= not sharing the same element) data subsets for the non-backup main data) and a disjoint data subset for the backup data are calculated according to an appropriate algorithm. Distributed among different secondary storage devices
You. A message about the primary data if two processors respond simultaneously because one processor is sharing a subset of the primary data and another is sharing a subset of the backup data. Is given priority. In order to compensate for this condition, a command code having a higher priority (see FIG. 22) may be selected. Maintaining the reliability and integrity of the database is also achieved by utilizing the various multi-processor modes described above, in which those modes are applied in the most advantageous way for the particular situation encountered. . For example, if the secondary storage device sharing a subset of the primary data fails, it can be updated using special processor-to-processor communication. Error correction and rollback of a part of the database can be performed in the same manner or by operating in the class mode.

Transaction Number Examples The concept of transaction numbers has provided a new and powerful hardware mechanism for controlling multiprocessor systems. In the present system, the transaction number constitutes a "global semaphore", and is used to transmit and receive messages to and from the network and to confirm the readiness of a given task distributed to a plurality of processors. Each plays an important role.

The transaction number (TN) is
H. S. It is physically implemented as a 16-bit word in RAM 26. This word has a format as shown in FIG. 22 so as to perform various functions. TN is H. S. Since it is stored in the RAM, it can be accessed from both the microprocessor 105 and the network interface 120.

Global Semaphore The term "semaphore" is a commonly used term in computer science literature to refer to variables used to control multiple operations that are performed asynchronously with respect to each other. It has become. A semaphore has the property that it can be "tested and set" in one uninterrupted operation.

As an example, “UNASSIGN
Let us consider semaphore variables that can take two states, "ED: state where assignment is not made" and "assigned (state where assignment is made)". In this case, the test-and-set operation is defined as follows: if the semaphore is "unassigned"
If so, the semaphore is assigned
Setting the state to indicate success; conversely, if the semaphore was already in the "assigned" state, leave the semaphore in the "assigned" state and indicate "failure". Thus, according to this semaphore, operations that successfully test and set the semaphore can continue their tasks, while operations that fail will reset the semaphore to an "unassigned" state. Or attempt to test and set another semaphore controlling another equivalent resource. As can be easily understood, if the test and set operation could be interrupted, there is a possibility that the two processes may access the same resource at the same time, thereby preventing the prediction. Erroneous results that cannot be obtained may occur.

[0202]

Any multiprocessor system actually implements, in hardware, a concept that can be equated with a semaphore to control access to system resources. However, the conventional system can maintain only one copy of a semaphore (= a semaphore having one copy, that is, a semaphore provided only at one location). Therefore, if semaphores of a plurality of copies (= semaphores having a plurality of copies, that is, semaphores provided at a plurality of locations) are provided and maintained one by one in each processor, the semaphores can be simply accessed for testing. It is desirable both for the purpose of reducing the number of occurrences of contention and for the purpose of utilizing multivalent semaphore variables for other uses described below. The problem is that many copies of the semaphore must be completely synchronized, and if this is not followed, semaphores are provided to enhance it. In this case, the integrity of access to resources is lost.

Multiple copy semaphores, or "global" semaphores, are provided by the present system. The following table describes the operations on the global semaphore as a single semaphore (1
Semaphore of a copy).

[0204]

[Table 1] In the system of the present embodiment, “TN assignment (ASSIGN T
N)) command and the "TN Abandon (RELIN-QUISH TN)" command respectively perform a test-and-set function and a reset function for a transaction number used as a global semaphore. Referring to FIG. 22, a "NAK / TN error" response indicates failure, while a "SACK / assigned" response indicates success.

The characteristics of this network include a synchronous clocking method used for synchronously clocking a plurality of nodes and a broadcast operation for transmitting the highest priority packet to all processors at the same time. It is the basis for the realization of the concept of global semaphores. Due to the implementation of this concept, the system gives control of the allocation, deallocation, and access of multiple copies of the desired system resource, simply granting the TN to that resource. This can be done by doing. It is important to note that control of distributed resources can be performed with a small amount of software overhead that is almost the same as that of a single semaphore. This is a significant advance over traditional systems because they cannot manage distributed resources or require complex software protocols and create hardware bottlenecks. Either it will be lost.

Readiness state "BUSY", "WAITING"
) "," READY "(ready for transmission and reception ready)," DONE ", and" NON-PARTICIPANT "(see FIG. 22). Provides the ability to quickly check the readiness of a task assigned a TN. In this system, the meaning of each state described above is as shown in the following table.

[0207]

[Table 2] The assignment of the TN to the task is dynamically performed by using the “TN assignment” command. Success indication ("T
"SACK / assigned" for "N Assignment" message
Response) indicates that all operational processors have successfully T
Indicates that the assignment of N to the task has been completed. It should be noted with respect to FIG. 21 that the "NAK / TN error" response has a higher priority (lower value), so that the network interface 12
If 0 detects a collision regarding the use of TN, all processors will receive a failure response. Further, the OPI of this failure response transmitted over the network
The D (originating processor ID) field indicates the first (smallest numbered) processor among the processors having a collision. This fact is used in the diagnostic routine. Each processor handles the tasks by software and sets the TN to “Biz”, “Waiting”, “Ready to send”,
Set to "Ready to receive", "End" or "Non-participating processor". The first "TN
Any processor, including the processor that issued the assignment ",
At any time, by issuing a "status request" command or a "merge start" command,
It is possible to easily check how much the task (TN) has been completed.

A "status request" is the same as a single test of a multivalent (= possible value) global semaphore. As can be seen from FIG. 21, the highest priority status response (SACK) message wins the competition on the network, resulting in the lowest readiness state being indicated. Furthermore, the OP
The ID field is the first (lowest numbered) processor among the processors in its lowest readiness state.
It will show the identity of the processor.

Using this latter property, a "wait" for the completion of a task distributed to multiple processors is provided.
The form of "non-bysy" is defined. The processor that first issues "TN assignment" is considered to be the original "wait master". The processor then designates any other processor as a new "wait master" based on any criteria. When the new "wait master" has reached the desired readiness state, it issues an inquiry to all processors by issuing either a "merge start" or a "status request". If all of the other processors were ready, the SACK would indicate so. If some processors were still not in the ready state, the OPID field of the SACK response would indicate the first of the processors with the lowest readiness state. The "wait master" instructs the processor to become the new "wait master". Eventually, all processors will be ready, but until then, the system will only attempt to query the status each time at least one processor is notified that it has reached the ready state. It is. Thus, the system is not burdened with periodic status queries that consume resources without producing results. Further, according to this method, the system can surely know that all the processors have completed their work just at the time when the processing to be completed last is completed. As will be appreciated by those skilled in the art, a wide variety of other "waiting" forms may be employed within the scope of the inventive concept.

[0210] The "merge start" command is one special type of test and set instruction. If the status of the global semaphore is “ready to send” or “ready to receive”, the current transaction number register (PTNR) 206 (see FIGS. 23 and 24) displays a “merge start” message (FIG. 13). ) Is set to the value of the transaction number in the above, thereby setting the PTNR register. If any of the active processors is in a lower readiness state, the value of PTNR is not changed.

The “merge stop” command is a reset operation corresponding to the above operation, and unconditionally resets the PTNRs of all active processors to “TN0”.

As described later, the current global task (current global task) specified by the PTNR
) Are output from the network interface 120.
Thus, the "Start Merge" and "Stop Merge" commands provide the ability to time multiplex, or time multiplex, the network between multiple tasks, and thus Can be arbitrarily stopped and / or resumed.

Significantly, in the details of the present invention, the network interface 120 ensures that access to the TN by a command from the network and access to the TN by the microprocessor 105 are never performed simultaneously. There is that. In the present embodiment, this is accomplished by a signal being sent from the receive state control circuit 260 to the read / write state control circuit 270, which signals a command from the network that may change TN. Is always "Yes" when the processing of (1) is performed. During the brief period in which this signal is in the "positive" state, the processor will S. Access to the RAM is prohibited by the control circuit 270. As will be appreciated by those skilled in the art,
A wide variety of alternatives to the above may be employed within the scope of the present invention.

Reception Control Another function of the TN is to control input messages.
By using the "assign TN" command, an input message stream in multiple processors can be associated with a given task. When the TN assigned to the task in a given processor is set to "ready to receive", the TN also includes a count value representing the number of packets the processor is ready to accept. Is displayed (Fig. 2
2). The network interface 120 decrements this count value after each successful receipt of an individual packet (this decrement is performed by arithmetically subtracting a "1" from the word in TN);
This decrement continues until the count reaches zero. When the count value reaches zero, “NA
A "CK / Overrun" response is generated, which causes this NACK to be sent to the processor sending the packet.
It is informed that the responding processor must wait until it is ready to accept more incoming packets. Further, as can be seen from FIG. 30, the PTNR is reset to "TN0" at this time.

With the above operation mechanism, it is possible to directly control the flow of packets flowing through the network. It also ensures that one processor is not packed with large amounts of unprocessed packets and that the processor does not become a bottleneck for the system.

Transmission Control Referring to FIG. 34 (a), as can be seen from FIG. S. Each message stored in RAM is
A field for containing the value of the new TN vector (= next message vector) is included. If the message has been sent and a response to it has been successfully received, the new TN vector contained in the message just sent will contain the H.264 vector. S. Stored (transferred from PTNR) to an address in RAM to store the current transaction number. Therefore, the TN is updated each time an individual message is sent, and it is possible to automatically set the TN to a desired state upon successful transmission of the message. .

Referring to FIG. 22, the format of the TN of “transmission ready” is a 14-bit H.264 format. S.
Contains the address in RAM, which is used to point to the next packet to output for a given task (TN). Therefore, H. S. RAM
The TN stored in also serves as a head pointer to the head of a first-in, first-out (FIFO) queue of messages for various tasks. Thus, as far as one given task (TN) is concerned, each processor will try to send out the packets in the order defined by the chain of new TN vectors.

High-speed multiplexing of a network among a plurality of TNs (tasks) as described above (multiplexing)
Obviously, in combination with the mechanisms for doing so, many complex sets of tasks distributed among many processors can be managed with very little software overhead. The configuration provided by the co-operation of the network, the interface, and the processors allows their copies to be distributed among hundreds of processors, and even even among thousands of processors. This is a preferred configuration for allocating and deallocating resources, suspending and resuming tasks, and performing other controls on resources and tasks that can be performed.

Example of DSW (Transfer Destination Selection Word) The transfer destination selection word (FIG. 13)
(FIGS. 23 and 24) and S. RAM 26 (FIG. 1)
By cooperating with the DSW section of 8), it provides a plurality of modes that enable: That is, the modes are determined by the network interface 120 of each receiving processor as to whether the message being received is intended to be processed by the microprocessor 105 associated with that network interface. Is a plurality of modes for making it possible to quickly turn off. As already explained, the DSW included in the received message is
H. S. The nibble stored in the DSW section of the RAM is selected and compared with the nibble.

Processor Address As shown in FIG. S. DSW for RAM
One part of the section is dedicated to storing processor address select nibbles. In this system,
For each of the 1024 processors that can be mounted,
H. S. One of the bit addresses contained in this portion of the RAM is associated. The bit of the bit address associated with the processor ID (identity) is set to “1”, while all other bits in this section are “0”.
Has been. Thus, each processor has only one bit in this section set to "1".

Hash Map H. S. Another part of the DSW section of the RAM is dedicated to storing hash maps. In the present system, two of the map select bits are assigned to their hash maps, resulting in two complete sets containing all 4096 possible values. In hashed mode, the keys for the records stored in secondary storage are set according to a hashing algorithm, thereby assigning a "bucket" between 0 and 4095. . The processor responsible for the record contained in a given "bucket" has a "1" bit set in the map bit whose address corresponds to the bucket number of that bucket. . Other bits are set to “0”. Simply setting multiple map bits allows a given processor to be responsible for multiple buckets.

In the structure of this embodiment, as will be easily understood, the setting of map bits can be performed in the following manner. That is, for a given map select bit, each bit address is set to "1" in only one processor, and any bit
The address is always set to “1” in any of the processors. The direct consequence of adopting this scheme is that each processor (AM
P) shares a distinct and disjoint subset of the records of the database, and the whole system is such that there is a complete set containing all of the records.

Although the above example has been described with reference to the problem of relational databases, as will be readily understood by those skilled in the art, disjoint subsets of the problem are stored in a multiprocessor union. The same method can be applied to any task area that can be assigned to each processor.

Yet another noteworthy point is that by providing two complete maps, one can map the scheme described above according to one map to the buckets assigned to a given processor. Can be configured so that it can be assigned to a different processor. Here, if one map is "primary" and the other is "backup", the direct consequence is that a record that is primary on a given processor is: It can be ensured that it is backed up on another processor. Further, there is no restriction on the number of processors that back up a given processor.

As will be appreciated by those skilled in the art, the number of distinct maps that can be implemented within the scope of the present invention can be three or more, and the number of buckets can be any number. .

Class In any of the processor addresses and hash maps described above, examining the given one bit address for all processors yields that bit address.
It can be seen that the address is set to "1" in only one processor and the corresponding bit address in all other processors is set to "0". However, a scheme in which the corresponding bit address is set to "1" in a plurality of processors is possible and useful. This method is called a "class address" mode.

The class address can be considered as the name of a processing procedure or function whose copy exists in a plurality of processors. Any processor having the corresponding processing procedure or function has the "1" bit set in the corresponding bit address.

To send a message to a class address, the corresponding class address in the DSW (FIG. 13) is set. H. S. All operable processors that are indicated as "belonging" to the class by setting the bit at the corresponding location in the RAM to "1" are sent out the message packet. "ACK". Processors that do not belong to the class respond with a NAP.

Thus, the DSW ensures that the routing calculations required to control the flow of messages in a multiprocessor system are performed by hardware. Also, the program can be independent of the knowledge of which processor has the various functions of the system. Further, the map is H.264. S. Because it is part of the RAM and thus accessible from the microprocessor 105, certain functions can be dynamically relocated from one processor to another.

Merging Example In a complex multiprocessor system, a task may require the execution of a series of interrelated operations. This is especially true for relational database systems that handle complex queries, in which data is assembled into files and then assembled in a particular manner. It may be necessary to refer to multiple secondary storage devices to create a file that can be redistributed to other processors. Examples shown below are shown in FIGS.
3 and briefly describe how the system of FIG. 24 can easily perform such functions by manipulating TNs, DSWs, and global semaphores. Things. First,
In the meantime, the merge coordinator (typically the merge coordinator is IFP 14-16,
Although not necessarily limited to this, a plurality of AMPs belonging to one class that will be formed by merging a certain file (that is, functioning as a data source) are selected (from among AMPs 18 to 23). Identify. One unassigned TN is selected and assigned to identify the data source function. The second major function of distributing or hashing this file to another set of AMPs (which may be the processor of the original data source) has not been assigned until then. Another TN is assigned.

The coordinator for the merge function identifies, using the DSW, a plurality of processors belonging to a class in which a merging operation is to be performed in a file related to the first TN. The participating processors involved in this merging task raise the level of the TN's status to "visit" or "wait"
Status, after which control of the merge operation is passed to one of the participating processors involved in the merge operation (ie, the coordinator's work is delegated). Each of the plurality of participating processors (all other processor modules are non-participating processors with respect to their transaction numbers) receives the message packet relating to the merge task defined in this way and After sending a positive response to
The execution of the processor's own subtask proceeds while updating its status level as appropriate. Then, if the processor delegated the job of the merge coordinator completes its own task, it will, for all other participating processors,
A status request may be sent to signal the status of the transaction number, thereby receiving a response indicating the processor with the lowest readiness among the participating processors. Control of the merge operation is passed to the processor with the lowest readiness state, after which the processor
You will be able to poll all other participating processors when you are done. The above process, if necessary, is repeated until a response is received indicating that all participating processors are ready.
Can be continued. The processor that was acting as the coordinator at the time such a response was received, then uses the DSW to identify participating processors belonging to the class, and S. The transfer of the message to the RAM 26 is started, and in accordance with the transfer of the message, the status level is updated to “transmission ready” by the corresponding output message vector information. If the subsequent polling indicates that all participating AMPs are ready for transmission, the coordinator issues a merge start command for that particular TN.

While the merge operation is being performed, the processed data packets are addressed to a plurality of processor modules belonging to a class for distributing the results to secondary storage according to a relational database.
Will be transferred. Regardless of whether or not the plurality of receiving processors are the same as the plurality of processors at this time, the participating processors belonging to the class involved in the distribution (that is, the receiving processors) are: The transaction is identified by the DSW, and the transaction is identified by the new TN. All new processors involved in this new transaction will be assigned this new TN, and
Their participating processors will raise their readiness level to "ready to receive." This DSW may be a hashing selection specification instead of a class specification, but in any case, while the merge is being performed, all participating processors can receive the broadcast message. You are in a state. If a "merge start" is issued, a plurality of message packets from each of the sending participating processors to be involved in the sending operation, and from each processor simultaneously with each other, are sent out onto the network, and the message packets are sent. Is dynamically determined (= during transmission). Once each sending participant has completed sending its own set of messages, each of their sending participant processors will have a defined "End of File". Attempt to send a message, and this "end of file" message has a lower priority than various data messages. Until all of the participating processors start sending out an "end of file" message, this "end of file" message will continue to lose contention with the data message,
Finally, once all participating processors have sent out, the transfer of the "end of file" message is achieved. Once this transfer is achieved,
The coordinator said, "End of Merge
ge) "message, followed by a" TN
Abandon "can be performed, which ends the transaction. Overrun condition,
An error condition or locked condition can be properly dealt with by restarting the merge or transmission.

Once the merging operation for one TN has been completed, the system can shift to the next TN in the sequence of TNs. Once each processor module has created a queue of message packets corresponding to this new TN, the processor modules will again begin working on the network to perform the merge operation. It becomes possible. Due to the efficient use of the in-network merge operations, in addition to the individually performed intra-processor merge operations, this system provides a significantly larger sort / Merge tasks can be performed. When the present invention is employed, the time required to sort a certain file in the system can be expressed by the following equation, where n is the number of records and m is the number of processors. .

[0234]

(Equation 1) In this equation, C2 is a constant, which for this embodiment is estimated to be about 10 microseconds when a 100 byte message is used, and C1 is the value used by a typical 16-bit microprocessor. , A constant estimated to be about 1 millisecond. Approximate sort / merge times for various combinations of n and m are given in the following table in units of seconds, and the values are for a 100 byte record being used. is there.

[0235]

[Table 3] It is not easy to evaluate the numbers of the specific examples shown in the above table in comparison with the conventional system. The reason is that two kinds of interrelated sort processing sequences (sort by processor and sort by network) are involved, and in the first place, there are almost no systems having such a capability. Because. In addition, the system sorts and merges long and variable messages, whereas
Many common sorting capabilities are rated for several bytes or words.

Another important factor is that the present system is a multiprocessor itself and is not a dedicated system for sort / merge processing. The system is able to shift between the merge operation and the non-merge operation with complete flexibility both locally and globally, and this shift can be performed without software disadvantage. Further, it can be performed without causing a loss in system efficiency.

Example Task Request / Task Response Cycle With reference to FIG. 1, any of the processors 14, 16, or 18-23 connected to the network 50
It has a function of forming a task request for causing one or more processors to execute a task in an appropriate format in the form of a message packet.
In relational database systems,
Most of these tasks are performed on the host computer 1
Sources 0 and 12 are sourced into the system via interface processors 14 and 16, but this is not a requirement. This message packet, formed in the proper format, is injected into the contention on the network for contention with packets from other processors, and the priority level of other tasks as well as the state of operation on this processor Depending on your level, you may sometimes get priority. A task may be specified by one message packet or its contents may be specified by a plurality of continuation packets, but the following continuation packets are grouped by data messages (FIG. 21). ) Are assigned a relatively high priority level, so that the delay in receiving the subsequent part is as short as possible.

The message packet contains the transaction identity (= transaction identification information) in the form of a transaction number. This transaction number includes a non-merge mode that is a mode relating to a method for extracting a processing result, that is, a default mode (“TN0”) and a merge mode (all TNs except “TN0”). It inherently has the property of distinguishing according to selection. Further, the message packet contains the DSW.
The DSW substantially specifies a transfer destination processor and a mode of multiprocessor operation, and this specification is performed by specifying a specific processor, a class including a plurality of processors, or specifying hashing. In this embodiment, hashing is hashing a part of the relational database.
The message packet broadcast to the target processor (designated destination processor) via the network 50 is locally accepted by the processor (= the determination that the acceptance by the processor itself is appropriate) is made. Made by the processor itself),
Then, authentication of reception is performed by an acknowledgment (ACK). All of the processors 14, 16, and 18 to 23 simultaneously send a response to the network 50 following the EOM (end of message), however, the ACK sent from the designated destination processor has priority. And will be received by the originating processor.

Subsequently, the designated transfer destination processor determines that the transmitted message is a local H.264 message. S. RAM (= HS RAM provided in each processor module)
And interface 120 (FIGS. 18, 23 and 2).
4) When the request packet (= message sent) is transferred to the local microprocessor via (4), the process requested by the request packet is asynchronously (= synchronized with an element other than the processor module). Do). When a task is performed on a relational database, the DSW typically specifies a portion of a disjoint data subset, which is stored on the disk drive for that subset. However, sometimes, tasks that do not need to refer to the stored database may be performed. Certain operations and algorithms may be executed by individual processors, and if multiple processors are specified as designated destination processors, each of those processors may be a disjoint subset of the entire task. About to be able to do the job. The variable-length message packet is configured so that an operation to be performed and a file to be referenced in the database system can be specified by a request message. Note that there may be a large number of message packets for a given task,
In that case, in order to provide appropriate features that serve as discrimination criteria for sorting performed inside the network,
The key field that can be arbitrarily adopted (FIG. 13) becomes important.

A task response packet generated by each processor attempting to respond is transmitted from the microprocessor via the control logic 28 of FIG.
S. It is transferred to the RAM 26 where the task response packet is stored in the outgoing message format of FIG. If the task response requires the use of a continuation packet, such a continuation packet is sent after the first packet, but with a higher priority for continuation. You. If the system is operating in merge mode and each processor is generating a large number of packets for one transaction number, those packets are first locally (= individual processor = Chaining (internally) in a sort order, and then merging over network 50 can be arranged in a global sort order.

The task result packet is transmitted to the processor 14,
16 and 18-23 to the network 50 to form a group of simultaneous transmission packets, and one top priority message packet is broadcast back to all processors after a predetermined network delay. Depending on the nature of the task, the transfer of these task result packets may be performed with the source processor that originally transmitted the request message as its transfer destination, and one or more other processors. May be performed as a transfer destination, and further, the transfer may be performed in any of the plurality of multiprocessor modes described above. The most common case in a relational database system is to perform merging and redistribution at the same time while selecting a destination using hashing. Therefore, as can be understood from that,
In the "task request / task response" cycle, each processor, even as the originating processor,
It can operate as a coordinator processor and also as a responding processor, and can even operate as all three. Because many "task request / task response" cycles are involved, processors 14, 16 and
18-23, as well as the network 50, are multiplexed between those tasks, provided that this multiplexing is based on time and also on a priority basis.

Complex Query Example In a relational database system,
Utilizing the host computers 10, 12, and furthermore, the relational database can be stored in a plurality of disk drives 38-34 according to an algorithm that defines tuples and disjoint data subsets of primary and backup data. A complex query is input from the host computer 10 or 12 to the system via the IFP 14 or 16 using a distribution method that is arranged to distribute among 43. The input query message packet is first sent to IFP 14 or 1
6, which is performed to convert a message from the host computer into a plurality of task requests for requesting the AMPs 18 to 23 to execute a task. IFP
14 to 16 send out a request packet for extracting information from one or more specific AMPs at the start of the operation, so that a detailed analysis of the message from the host computer is required. It may be necessary to obtain in-system data. When the data necessary for processing the request from the host computer is obtained, the IFPs 14 to 16
-23 can be executed, and the data can be actually processed to satisfy the request from the host computer. In the above-described processing sequence, the cycle including the task request and the task response described above is used, and the cycle can be continued for an arbitrary length. Then I
The FPs 14 to 16 communicate with the host computer via the IFP interface. This response to the host computer is simply
Or 12 may be to provide the data needed to generate the next complex query.

(Standalone Multiprocessor System) The basic embodiment of the system according to the invention described above in connection with FIG. 9 shows an example of a post-processor (back-end processor) that can be used in combination. However, as already mentioned, the present invention can be used in a wide variety of processing applications, and especially in those types of processing applications in which processing tasks can be easily subdivided and distributed without the need for large amounts of central processing power. , With particular advantages. FIG. 33 shows an embodiment of a simple configuration of a stand-alone (stand-alone) multiprocessor system according to the present invention. In FIG. 33, a plurality of processors 300 are all connected to an active logic network 304 via an interface 302.
This network is similar to that already described. To enhance data integrity, a redundant active logic network 304 may be employed. Also in this embodiment, a 16-bit microprocessor chip can be used for the processor 300, and a sufficient capacity of the main RAM memory can be incorporated. In this figure, only nine processors 300 are shown, and each of these processors is connected to a different type of peripheral device,
This is to show the versatility of this system. actually,
The system becomes much more efficient by having more processors in the network, however, even with a relatively small number of processors, the system's reliability and data integrity This offers particular advantages.

In this embodiment, the plurality of processors 300 can be physically separated from each other at a sufficient distance without inconvenience, the data transfer rate being the rate described for the previous embodiment. In some cases, the maximum separation between nodes can be as much as 28 feet (5.5 m), so multiple processors in a large array can be combined on one floor of a building,
Or, it can be installed and used on several adjacent floors so as not to be crowded unnecessarily.

In a stand-alone system, much more types are used for the peripheral controller and for the peripheral itself, as compared to the postprocessor embodiment described above. Here, for convenience, it is assumed that each input / output device is connected to a separate processor. For example, the keyboard 312 and the display 3
14 is connected via a terminal controller 320 to a processor 300 for the terminal device 310. However, in the case of relatively slow operating terminals, it is not impossible to control a large terminal network with a single 16-bit processor. The input / output terminal device shown in FIG.
It merely shows an example of how a manual operation input processing device such as a manual operation keyboard is connected to the system. Utilizing the processing power of the processor 300, the terminal device 310 can be configured as a word processor, and the word processor can communicate with a database, another word processor, or various output devices via the network 304. Can also. For example, a mass secondary storage device such as a rigid disk drive 322 may be connected via a disk controller 324 to a processor for the storage device. Also, as will be readily appreciated, larger systems may use more disk drives or use different forms of mass storage. Output devices such as the printer 326 and the plotter 330 are connected via a printer controller 328 and a plotter controller 332, respectively.
It interfaces to a processor 300 for those output devices. Interaction with other systems (not shown) is performed via a communication controller 338 and via a communication system 336, such as a teletype network (TTY),
One of the larger networks (for example, Ethernet) is used. Processor 300
May simply be connected to the network 304 without connecting peripheral devices (not shown).
The two-way data transfer can take place at the tape drive (tape drive) 340 and at the tape drive.
If a drive controller 342 is used,
In addition, there is a case where the floppy disk drive 344 to which the controller 346 is connected is used. In general, tape drives not only provide large storage capacity when used online,
It can also be used to back up disk drives. For the purpose of this backup, tapes are used to store data stored up to a certain point in a sealed rigid disk drive. Such backup operations are typically performed during periods of low load (eg, at night or on weekends) so that long “streaming” transfers can be performed using network 304. In addition, the floppy disk drive 344 may be used for program input during system initialization, so some of the network usage time may be reduced in this "streaming" mode. Can transfer a significant amount of data. Optical character reader 350 serves as a further source of input data, which is input to the system via its controller 352. In addition, the peripheral device simply described as “other device 354” is connected to the system via the controller 356,
Other functions can be performed as needed.

Each message packet is sent simultaneously from different processor modules to each other, and the priority of the message packets is determined so that one or a common highest priority message packet is determined. Any processor that is online can be used to broadcast to all processor modules simultaneously within a certain amount of time.・ Equal access to the module. This global semaphore system, utilizing a prioritized transaction number and readiness status indication, and a destination selection entry included in the message, allows any processor to act as a controller. Therefore, this system can operate in a hierarchical system or a non-hierarchical system. It is also very important that the system can be scaled up or down without requiring software review and modification.

Even if access is required to a message that is considerably longer than the message length already described, but is still relatively limited in length, such access can still be performed. For example, for a complex computer graphics device (not shown), it is necessary to access only certain parts of a huge database to create sophisticated two-dimensional and tertiary figures. There is. Also, for word processing systems, only a small sequence of data at a time may be required from the database due to the slow operation speed of the operator. In these and similar situations, the system's ability to handle variable length messages,
In addition, the ability to give priority to continuation messages would be beneficial. Circumstances that require centralized processing or transfer of extremely long messages limit the use of this system, but in other situations the system can perform very well. I do. Any of the dynamic situations involving the manipulation of various different data formats and the associated sorting or merging functions are situations in which the present invention operates advantageously. Business decision making, which involves collecting, collating and analyzing complex data, is one example of such a situation, and the creation and editing of video and graphical inputs for periodicals is also an example. This is an example.

[0248]

Conclusion As will be apparent to those skilled in the art, the system of FIG. 1 allows the number of processors included therein to be any number (but not the data transfer capacity) without requiring software changes. (Up to the number of practical limits determined by). It is also evident that the system shown in the figure is used for checking the status of each processing unit, setting tasks and priorities of processors, and ensuring efficient use of the processing power of the processors. It significantly reduces the need for management and overhead software.

The obvious benefit is that the subdivision of a database system or other subtasks, like a database system, into one complete task can be performed independently of each other. This is the case with an appropriate system. For example, in relation to a relational database, if the capacity of the secondary storage device is significantly increased, it is only necessary to appropriately integrate a further database into a data structure composed of primary data and backup data. is there. In other words, the network can be extended indefinitely, which is possible because the standardized intersection devices or nodes are connected in a binary-evolving connection scheme, This is because the functions executed in those individual nodes are not changed by the extension. Furthermore, a setting processing sequence and an external control for the operation of the node are not required. Thus, when a system according to the present invention is connected to function as a back-end processor for one or more host computers, as shown in FIG. The database can be arbitrarily expanded (or reduced) without changing the system software or application software. From the perspective of the host processor system (= host computer), this back-end processor is "transparent" regardless of its configuration, even if its configuration changes. This is because the manner of interaction between the backend processor and the host processor system does not change. To switch this back-end processor to do the work of another host processor system, simply ensure that the IFP properly talks to the channel or bus of the new host processor system. Just good. According to the configuration of the network in an embodiment of a real machine, a single array can be used without causing a significant delay in message transfer in the network and without an unreasonable delay due to contention between processors. Up to 1024 microprocessors can be included and used. It will be apparent to those skilled in the art how to extend the embodiments described herein to include more than 1024 processors. When 1024 processors are used in one system, it has been found that the maximum line length between the active nodes is 28 feet in a practical example, and this line length is necessary for forming an array. There is no problem. The delay due to the network is a fixed time 2τN for any message, where τ is the interval between byte clocks and N is the number of layers in the hierarchy. Obviously, doubling the number of processors by adding one more tier will only increase the delay slightly.
Since data messages are almost inevitably long messages (about 200 bytes long), the priority determination for all competing messages requires that data be transferred along the network. As such, the network is capable of transferring data messages with much higher efficiency than conventional systems.

Among the important economic and operational features of the system are the fact that standardized active logic circuits are used in place of software and even firmware in network systems. There are features obtained by:
That is, by this fact, modern LSI and VLSI
By using the technology described above, a highly reliable circuit can be incorporated at a relatively low cost relative to the total cost including the cost of the processor and the cost of the peripheral device.

The time and expense that must be spent on software is limited to only those important parts that are related to tasks in problem areas such as database management. For example, the configuration of the system allows all of the functions required to maintain the integrity of the database to be performed within a range based on the configuration of the message packets and the configuration of the network. ing.
Functions such as polling, status change, and data recovery are performed inside the system.

Yet another important consideration is that the network of the present invention has high-speed data transfer performance that is sufficiently comparable to conventional ohmic wiring buses. Since a plurality of message packets are transmitted simultaneously with each other and the priority is determined while they are being transmitted, the status request and the response to the status request and the priority determination are performed in a conventional manner. This is because the delay that has been occurring has been avoided. Furthermore, even if the number of processors is enormous, the length of the connection structure between nodes can be suppressed to a predetermined length or less, so that the propagation time in the bus is a constraint on the data transfer rate. Nothing.

The system has been found to be near optimal in terms of microprocessor and network utilization. What is important in these respects is that all microprocessors remain busy and that the network is fully utilized. The configuration of the "IFP-Network-AMP" effectively makes them possible because of the messages it sends out.
The microprocessor that lost the packet in the race to gain priority only has to try again as soon as possible at the appropriate time, thereby maintaining the bus duty cycle at a high level. Fast random access memory also contributes to this effect because it stores both input message packets to be processed and output message packets to be sent out inside. Because each processor can always obtain the backlog of the work, the network can also obtain the backlog of message packets. When all the input buffers are full, the processor sends an indication on the network to indicate this fact. Also, when the input buffer used for receiving a message from the host computer used for the IFP is full, an indication to that effect is sent out on the channel. Thus, the system is self-starting, both internally and externally.

The system is configured to execute many other functions required for a general-purpose multiprocessor system by utilizing the architecture and message structure as described above. . For example, in the prior art, great care has been given to schemes for evaluating and monitoring changes in the status of global resources. In contrast, according to the present invention, only the parity channel is provided and used as a means for communicating both the occurrence of parity errors and the fact that processor availability has changed. If one or more processors shut down, the shutdown is communicated to the system substantially simultaneously with its occurrence, so that execution of the interrupt sequence can begin. I have. Because multiple responses are sorted according to priority, if a global capability change occurs, the nature of the change will be much greater than in the past. It can be specified by small-scale circuits and system overhead.

The global response achieved through a single query and priority determination, achieved by employing a global semaphore and an active logic network, has very deep system implications. I have. Broadcasting queries in this manner provides unambiguous and unambiguous global results, eliminating the need for complex software and overhead. Status setting operations such as distributed update can be performed even when a large number of simultaneous operations are being executed by a plurality of different processors.

Further, the present system exerts excellent ability for distribution of work and collection of processing results in a multiprocessor system by using the above network, transaction number, and transfer destination selection word. . Various multiprocessor modes and control messages are available, and various levels of priority can be easily set and changed simply by manipulating the priority protocol. . By combining the ability to broadcast to all processors simultaneously, and the ability to sort messages across the network,
Any processor group or any individual processor can be a transfer destination, and processing results can be extracted in an appropriate order. Thus, when a complex query to a relational database system is entered, it initiates any processing sequence required for database operation.

[0257] Yet another advantage of the present system is that multi-processor systems such as relational database systems can be used.
It is that redundancy can be easily introduced into a system. The dual network and dual interface provide redundancy so that the system can continue to operate even if one of the networks fails for some reason. Since the database is distributed in a disjoint temporary subset and a backup subset, the probability of data loss is reduced to a minimum level. In the event of a failure or modification, the integrity of the database can be maintained due to the availability of a variety of versatile control functions.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system according to the present invention, including a novel interactive network.

FIG. 2 is a diagram showing a state before the start of transmission of a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 3 is a diagram showing a state at time t = 0 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 4 is a diagram illustrating a state at a time t = 1 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure illustrated in FIG. 1;

FIG. 5 is a diagram showing a state at time t = 2 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 6 is a diagram showing a state at time t = 3 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 7 is a diagram showing a state at time t = 4 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 8 is a diagram showing a state at time t = 5 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 9 is a diagram showing a state at time t = 6 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 10 is a diagram showing a state at time t = 7 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 11 is a diagram showing a state at time t = 8 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 12 is a diagram showing a state at time t = 9 when transmitting a data signal and a control signal in the network of the embodiment having the simple structure shown in FIG. 1;

FIG. 13 is an explanatory diagram illustrating a configuration of a message packet employed in the system shown in FIG. 1;

FIG. 14 is a block diagram showing a further detailed structure of the active logic node and clock circuit used in the novel bidirectional network shown in FIG. 1;

FIG. 15 is a state diagram showing various operating states inside the active logic node.

FIG. 16 is a timing diagram illustrating an end-of-message detection operation performed inside the active logic node.

FIG. 17 is a timing waveform diagram for explaining the operation of the clock circuit shown in FIG. 14;

FIG. 18 is a block diagram of a processor module including high speed random access memory that can be used in the system shown in FIG.

FIG. 19 is a diagram showing an assignment state of addresses inside a main RAM of the microprocessor system shown in FIG. 18;

FIG. 20 shows a high-speed random access mode shown in FIG.
FIG. 3 is a block diagram of an arrangement of data in one reference portion of the memory.

FIG. 21 is a chart showing a message priority protocol used in the system.

FIG. 22 is an explanatory diagram illustrating a word format of a transaction number.

FIG. 23 is a diagram showing the left half of a block diagram of an interface circuit used for each processor module provided inside the system shown in FIGS. 1 and 18;

24 is a diagram showing the right half of a block diagram of an interface circuit used for each processor module provided inside the system shown in FIGS. 1 and 18. FIG.

FIG. 25 is a timing diagram illustrating various clock waveforms and phase waveforms used in the interface circuit shown in FIGS. 23 and 24.

FIG. 26 is a block diagram illustrating further details of a memory configuration and one type of mapping for performing mapping based on a destination selection word.

FIG. 27 is a simplified flowchart showing a status change upon receipt of an input data message.

FIG. 28 is a diagram showing the first half of a flowchart showing a status change when a message is being received;

FIG. 29 is a diagram illustrating a latter half of a flowchart showing a status change when a message is being received.

FIG. 30 illustrates the relationship between various primary messages and various responses generated thereto, as well as the relationship between various primary messages and actions performed in response thereto. It is a table.

FIG. 31 is a diagram showing the first half of a flowchart showing a status change when a message is being transmitted.

FIG. 32 is a diagram illustrating a latter half of a flowchart showing a status change when a message is being transmitted.

FIG. 33 is a block diagram of a stand-alone system according to the present invention.

FIG. 34 is a diagram showing a transmission message and a reception message stored in the high-speed random access memory.

FIG. 35 is a simplified schematic diagram illustrating one possible distribution scheme for distributing respective portions of a database among a plurality of different processors in a database system.

[Explanation of symbols]

10, 12 host computer, 14, 16 interface processor, 18-23 access module processor, 24 microprocessor, 2
6 High Speed Random Access Memory, 28 Control Logic, 32 Disk Controller, 38-43 Disk Drive, 50 Active Logic Network Structure, 54 Nodes, 56 Clock Sources, 12
0, 120 'network interface, 10
3 Microprocessor system

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Richard Clarence Stockton Northridge Merrion Drive, California, USA 19005 (72) Inventor Martin Cameron Watson, Northridge Cabrioall Avenue, California, USA 11112 ( 72) Inventor David Clonshaw, 5635 Trans Towers Street, California, U.S.A. 5635 (72) Inventor Jack Ebert Siemer, Los Angeles Oshano Drive, California, USA 270

Claims (9)

(57) [Claims] 1. A method for operating a plurality of processors that asynchronously execute a plurality of associated tasks to obtain global coordination with respect to processing of a given task, comprising: a. Sending a message having a transaction number set to identify the task in a message relating to a task to be processed globally; b. A plurality of messages competing with each other sent from a plurality of different processors are collectively sorted in descending order of priority while judging the priority between the messages based on the data content of the messages including the transaction number. Transmitting; c. Receiving each task identified by the transaction number at an individual processor involved in the processing of the task and processing locally and asynchronously with each other; d. Sequentially storing processed messages for a plurality of tasks in individual processors; e. One processor sending a message to the other processors inquiring about the existence of a processed message related to a specific transaction number; f. Transmitting a message related to the processed message transmission request; g. Obtaining a series of processing results for the task by sequentially sending mutually conflicting processed messages from the processors for a given transaction number according to the priority determination; A method for controlling task processing and message transmission and reception in a multiprocessor system, comprising: 2. The multiprocessor system according to claim 1, further comprising a step of sending a message including a command word for setting and assigning the specific transaction number before or after the execution of each of the steps. For controlling task processing and message transmission / reception in a computer 3. In the message relating to the inquiry in step e, when the transaction number is "0", the message is defined as a message not related to a specific task. When the transaction number is other than "0", 2. The method for controlling task processing and message transmission / reception in a multiprocessor system according to claim 1, wherein the message is defined as a message related to a specific task. 4. In a multiprocessor system in which a plurality of processors are interconnected via a network having a sorting function, a given task to be processed globally is asynchronously distributed as a plurality of subtasks. A method of coordinating processing, comprising: a. Global task processing to be performed by the corresponding processor as the subtask by sending a message including transaction identity reference information indicating that the message is related to a specific task to the plurality of processors via the network. And b. Accepting the message including the transaction identity reference information at an individual processor to perform a subtask for the particular task; c. Processing a subtask associated with each of the tasks and displaying completion of the processing in each processor; d. Of the messages sent from each processor to the network in a predetermined time frame,
The network transmitting the processing results of the plurality of subtasks relating to a specific task while sorting the subtasks; e. A step of sequentially receiving the sorted processing results of the plurality of subtasks and obtaining an integrated processing result of the task; and a task processing and message transmission / reception control method in a multiprocessor system. 5. If the processing of the subtask related to the task is not completed in step c, step a) is performed for a task related to another transaction number.
5. The method for controlling task processing and message transmission / reception in a multiprocessor system according to claim 4, wherein steps e through e are performed. 6. A communication control method between processors in a multiprocessor system in which a plurality of processors are interconnected via a network, comprising: a. A predetermined predetermined priority that includes a transaction number for identifying a task by one processor to another processor and a command code for requesting a given operation to another processor. Sending a primary message provided with a protocol; b. Batch transmitting simultaneously the highest priority message determined according to the priority protocol to all of the plurality of processors via the network; c. A plurality of processed data relating to the task specified by the transaction number included in the highest priority message from the other plurality of processors;
Sending messages to the network simultaneously with each other; d. For the plurality of processed data messages transmitted simultaneously, a priority determination is performed in the network according to the predetermined priority protocol, whereby the highest priority processed data message is assigned to the one processed data message. Means obtained by the processor of e. Step d is repeated between messages other than the highest priority processed data message;
Thereby sequentially accepting said plurality of processed data messages for said task specified by the transaction number in said highest priority message to said one processor, the task in a multiprocessor system comprising: Processing and message transmission / reception control method. 7. When a plurality of processed data messages relating to a plurality of transaction numbers relating to a plurality of tasks are present in each of said processors, said individual steps a and b are repeatedly executed. 7. The task processing in the multiprocessor system according to claim 6, wherein the processor stores the processed data messages related to the plurality of tasks side by side in its buffer means, and then executes the steps c to e. And a method for controlling transmission and reception of messages. 8. In the step (a), when there are a plurality of tasks to be processed and a plurality of primary messages are sequentially transmitted, the primary messages having a higher priority according to the priority protocol are sequentially transmitted. Item 7. A task processing and message transmission / reception control method in the multiprocessor system according to Item 7. 9. The method according to claim 8, wherein between the step b and the step c,
Sending a message for a status inquiry indicating the processing status of each processor with respect to a given transaction number; simultaneously sending response messages to the inquiry message in the individual processors; A step of preferentially transmitting a status with the lowest processing status based on the priority protocol with respect to the response message, and thereby determining an overall processing status of the task process related to the transaction number; 9. The method for controlling task processing and message transmission / reception in a multiprocessor system according to claim 8, comprising: