JPH02114933U - - Google Patents

Info

Publication number
JPH02114933U
JPH02114933U JP1989022309U JP2230989U JPH02114933U JP H02114933 U JPH02114933 U JP H02114933U JP 1989022309 U JP1989022309 U JP 1989022309U JP 2230989 U JP2230989 U JP 2230989U JP H02114933 U JPH02114933 U JP H02114933U
Authority
JP
Japan
Prior art keywords
wiring board
board
wiring
bonded
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989022309U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989022309U priority Critical patent/JPH02114933U/ja
Publication of JPH02114933U publication Critical patent/JPH02114933U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案による配線基板を用いた情報カ
ードの一実施例を示す側面図、第２図は従来の情
報カード読取システムの構成を示す略線図、第３
図はその情報カードの電気的構成を示す略線的ブ
ロツク図、第４図は従来の配線基板を示す側面図
である。 ４，３０……情報カード、４Ａ，３２……基板
、４Ｅ……配線パターン、１５……チツプ部品、
１６……電極、１７……バンプ、２１，３１……
配線基板。 FIG. 1 is a side view showing an embodiment of an information card using a wiring board according to the present invention, FIG. 2 is a schematic diagram showing the configuration of a conventional information card reading system, and FIG.
The figure is a schematic block diagram showing the electrical configuration of the information card, and FIG. 4 is a side view showing a conventional wiring board. 4, 30... Information card, 4A, 32... Board, 4E... Wiring pattern, 15... Chip parts,
16... Electrode, 17... Bump, 21, 31...
wiring board.

Claims (1)

【実用新案登録請求の範囲】 チツプ部品の表面に形成した複数の電極をそれ
ぞれ対応する接合部材によつて基板上に設けられ
た対応する配線パターンに接合するようになされ
た配線基板において、 上記基板を柔軟性のある材料によつて形成した ことを特徴とする配線基板。[Claims for Utility Model Registration] A wiring board in which a plurality of electrodes formed on the surface of a chip component are bonded to corresponding wiring patterns provided on the board by respective bonding members, A wiring board characterized in that it is formed of a flexible material.
JP1989022309U 1989-02-28 1989-02-28 Pending JPH02114933U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989022309U JPH02114933U (en) 1989-02-28 1989-02-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989022309U JPH02114933U (en) 1989-02-28 1989-02-28

Publications (1)

Publication Number Publication Date
JPH02114933U true JPH02114933U (en) 1990-09-14

Family

ID=31240305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989022309U Pending JPH02114933U (en) 1989-02-28 1989-02-28

Country Status (1)

Country Link
JP (1) JPH02114933U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873126A (en) * 1981-10-27 1983-05-02 Seiko Keiyo Kogyo Kk Mounting method of semiconductor device
JPS60262430A (en) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873126A (en) * 1981-10-27 1983-05-02 Seiko Keiyo Kogyo Kk Mounting method of semiconductor device
JPS60262430A (en) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

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