JPH02114344A - Garbage collection processor - Google Patents

Abstract

PURPOSE:To speed up garbage collection processing using a cache memory device capable of simultaneously reading/writing plural words to decide whether the data of plural simultaneously read words are pointers or not. CONSTITUTION:A reading address register 01, an address decoder 07, a tag memory 08, a data memory 09, data register 05, 06, a comparator 10, a selector 23, and a part (for controlling a cache device) of a control device 30 constitute the cache memory device capable of simultaneously reading out/writing two words. The data of plural simultaneously read words are pointers or not are simultaneously judged by using the cache memory device capable of simultaneously reading our/writing plural words. Consequently, rapid garbage collection processing can be executed by adding a simple change to the cache memory device without changing a memory device or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a garbage collection processing device.

[Conventional technology]

Conventionally, in languages that require garbage collection, such as Lisp, garbage collection has been performed by software or firmware.

That is, garbage collection has been performed by software or firmware by comparing and determining values read out from the storage device word by word.

[Problem to be solved by the invention]

Garbage collection processing is a process of copying a data structure in one data area to another data area.

Traditionally, data structures are read word by word from a storage device or cache memory device, and software or firmware performs processing while checking whether the read value is a pointer to other data. .

An object of the present invention is to make changes to the memory device, etc. by using a cache memory device that can read and write multiple words at the same time, and by simultaneously determining whether the data of the multiple words read at the same time is a pointer. Instead, the object is to provide a high-speed garbage collection processing function by making simple changes to the cache memory device.

[Means to solve the problem]

A garbage collection processing device of the present invention includes a cache memory device having a configuration that allows simultaneous reading and writing of data of multiple words, an address register that specifies data reading and storage addresses of the cache memory device, and the cache memory device a plurality of data registers that store multiple words of data read simultaneously from the
a garbage register, a stack pointer that points to an area that stores a pointer to data that has not been garbage collected, a destination pointer that holds a copy destination address of data that is being garbage collected, and the destination register and the stack pointer. and a control device that controls the overall operation based on the value of the data register.

[Effect]

In languages that require garbage collection, such as Lisp, garbage collection is basically a process of copying data structures scattered in one area to another area. Consider garbage collection of the data structure shown in FIG. In this example, two data words constitute one unit (called a cell), and by connecting them, a larger structure is constituted. Assume that this data structure is stored in a certain area as shown in FIG. 2(a), for example. In this case, garbage collection will transfer this structure to other areas (see Figure 2).
The apparatus of the present invention, which performs packing and copying processing as in b), reads this unit structure (cell in FIG. 1) in - times, uses a writable cache memory device, and By simultaneously determining whether the data read at the same time is a pointer, the memory device
This method performs high-speed garbage collection processing by making simple changes to the cache memory device without making any changes to the language processing device or the like.

〔Example〕

Hereinafter, the apparatus of the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 01 is a read address register, 02 is a stack pointer, 03 is a destination register, 04 is an adder/subtractor, 05 and 06 are data registers, and 07
is an address decoder, 08 is a tag memory, 09 is a data memory, 10 is a comparator, 2"0.21, 22, 23.2
4 is a selector, and 30 is a control device that performs overall control. each register.

It is assumed that control of writing to and reading from each memory and control of each selector are all performed by the control device 30. The read address register 01, address decoder 07, tag memory 08, data memory 09, data registers 05 and 06, comparator 10, selector 23, and part of the control device 30 (the part that controls the cache device) are as follows:
It constitutes a cache memory device that can read two words at the same time and write two words at the same time.

First, the operation of this cache memory device will be explained. When reading data from the cache memory device, a value is given to the read address register 01, and when read is instructed by the control device 30,
A part of the value of the read address register 01 is decoded using the address decoder 07, and the tag memory 08 and data memory 09 are read.

The tag memory 08 stores the actual address of the data stored in the data memory 09. In this case, since the configuration is such that two words can be read and written, the tag memory 08 stores an address corresponding to two words of data, that is, an address of a part common to the two words. Therefore, the value of the read tag memory 08 and the value of the read address register 01 are compared using the comparator 10,
If the two values match, the value read from the data memory is the correct value; if they do not match, the value is incorrect. Therefore, the data is read from an external storage device, and its address is the tag. In memory 08, data is stored in data memory 09.

When reading a portion of the cache device, the selector 23 is given the portion of the addresses of the two read words that do not match, and one of the two words is selected.

When writing data from the cache device,
When a value is given to the read address register 01 and writing is instructed by the control device 30, a part of the value of the read address register 01 is decoded using the address decoder 07, and the tag memory 08 is read. . This value is compared with the value of the read address register 01 using the comparator 10, and if they match, the data stored in the data memory 09 is correct data, and two words of data are given to the data memory 09. , two words are written at the same time. When writing only one word, the control device 30 gives an instruction to the data memory 09, and although two words of data are given, only one word is written.

If the comparison results do not match, the data is read from the external storage device in the same way as when reading.
Writing is performed after the values in the tag memory 08 and data memory 09 are updated. However, when writing two words simultaneously, there is no need to read values from an external storage device, and the tag memory 08 and data memory 09 are updated.

In the above processing, tag memory 08, data memory 0
When the value of data memory 09 is erased by updating 9, the data is transferred from the external storage device to data memory 0.
9, those values are written back to the external storage device. If it has not been changed, it will be deleted as is.

Taking the data structures shown in FIGS. 2 and 3 as an example, the process of performing garbage collection processing will be described in detail. At this time, it is assumed that the value of the destination register 03 is n and the value of the stack pointer 02 is X. below,
To simplify the explanation, we will not discuss the process when the value read from the tag memory 08 and the value in the read address register 01 do not match.

First, address p of cell 1 is given to read address register 01, and reading from tag memory 08 and data memory 09 is performed. At this time, two words are read at the same time, so in the end, address p and address p+1
The value of will be read. Below, 2 as above
(n+2.s) The operation of reading two values at the same time as described above will be written as read (p) → (q, s).

Since the value of cell 1 is read to data registers 05 and 06, the value of data register 05 becomes q, and the value of data register 06 becomes S. This value is sent to the control device 30, and it is determined that both values are pointers (this can be determined based on the data value).

As a result, (value of destination register 03 + 2
) and the value of data register 06, that is, the two values n+2 and S are stored at address n indicated by destination register 03.

That is, the value n+2 is stored at address n, and the value S is stored at address (n+1). n+2 is a copy destination where data to be processed next is copied. In this case, there is no need to store S, but it is written to ensure consistency with the processing to be performed below.

After writing, destination register 03
2 is added to the value of (the value of the destination register 03 becomes n+2), and this addition is performed using the adder/subtractor 04.

Below, the operation of writing two values at the same time is as follows: (n+2.s) → write(n) I will write it as

Next, since the cell to be copied is cell 2, the value of data register 05 is read and transferred to address register 01, and since copying from cell 4 onwards has not yet been completed, the address of cell 4 must be memorized. This is because the storage location of the pointer that must point to the transfer destination must be remembered (until the copy is made,
I don't know where it will be copied), (n,
s) →write(x) ・Writes 2 to the value of stack pointer 02.
(The value of stack pointer 02 becomes X+2)
.

Next, cell 2 is read.

read (q) = (r, n1l) Since the value r of data register 05 is a pointer, as in the case above, the value of destination register 03 + 2 and the value of data register 06 are the address indicated by destination register 03. will be written to. That is, since the value of the destination register is n+2, ((n+2)+2.n1l) -ewrite((n+
2)) is written, and 2 is further added to the value of destination register 03. At the same time,
The value of data register 05 is read address register 0
Transferred to 1. Since the value nil in data register 06 is not a pointer, no further processing is performed.

Next, cell 3 is read.

read(r) -) ('a', n1l) In this case, since neither the values of data registers 05 and 06 are pointers, the values of data registers 05 and 06 are written as they are to the address indicated in destination register 03. , ('a', n1l)-ewrite((n+4
)) 2 is further added to the value of destination register 03. Since neither of the values in data registers 05 and 06 are pointers, next we reduce the value of stack pointer 02 by 2 using adder/subtractor 04, and use the previously stored data that has not yet been copied. Reads the storage address. That is, reading is performed as read (x)-e(n, s). Here, data register 06
The value S read out is the address of the data to be further copied, and the value n read out to the data register 05 is the address of the pointer that must point to the copy destination of the data indicated by the data register o6. It is a certain address. Therefore, the value of the data register 05 is transferred to the read address register 01, and a write (--, (n+6))-write(n) is performed. Here, -' indicates that no data is written.

(n+6) is the value of destination register 03. That is, when cell 1 was copied, since the copy destination address of cell 4 was not known, writing was performed as is, and the correct value was written in the location where the pointer to cell 4 should originally be written. Next, the value of data register 06 is transferred to read address register 01, and reading of cell 4 is performed.

read(a) −+ (' b ', t) In this case, the value "b' of data register 05 is not a pointer, but the value t of data register 06 is a pointer, so (' b ', (n+6 )+2)→((n+6))
A write is performed and the destination register 0 is
2 is further added to the value of 3. At the same time, the value of data register 06, which was a pointer, is sent to address register 01, and reading of cell 5 is performed.

read(t) -) ('C', n1l) In this case, the values of data registers 05 and 06 are both not pointers, and the value of stack pointer 02 is also the same value as when processing started, It can be seen that the garbage collection process has ended because there is no data that needs to be further copied.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment only, and when a cache memory is configured with a plurality of data memories, and when the number of words that can be read and written at the same time is changed. However, the basic implementation method remains the same.

〔Effect of the invention〕

According to the present invention, by using a cache memory device that can read and write multiple words simultaneously, it is possible to make changes to the memory device, etc. by simultaneously determining whether data of multiple words read simultaneously is a pointer. Without,
High-speed garbage collection processing can be achieved by making simple changes to the cache memory device.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, FIG. 2 shows an example of a data structure, and FIG. 3 shows an example of garbage collection. 01 is a read address register, 02 is a stack pointer, 03 is a destination register, 04 is an adder/subtractor, 05, 06... data register, 07 is an address decoder, 08 is a tag memory, 09 is a data memory,
10 is a comparator, 20°21.22, 23.24 are selectors, 30...control device.

Claims (1)

[Claims] A garbage collection processing device includes a cache memory device having a configuration capable of simultaneously reading and writing multiple words of data, an address register that specifies data read and storage addresses of the cache memory device, and a cache memory device configured to simultaneously read and write data from the cache memory device. Multiple data registers that store the data of multiple words issued, a garbage register, a stack pointer that points to an area that stores pointers to data that has not yet been garbage collected, and a copy destination address for the data that is being garbage collected. A garbage collection processing device comprising: a destination pointer that holds a destination register; an adder that updates the destination register and the stack pointer; and a control device that controls overall operation based on the value of the data register.