JPH02113627A - Phase synchronizing oscillator - Google Patents

Phase synchronizing oscillator

Info

Publication number
JPH02113627A
JPH02113627A JP63266553A JP26655388A JPH02113627A JP H02113627 A JPH02113627 A JP H02113627A JP 63266553 A JP63266553 A JP 63266553A JP 26655388 A JP26655388 A JP 26655388A JP H02113627 A JPH02113627 A JP H02113627A
Authority
JP
Japan
Prior art keywords
voltage
phase comparator
phase
output
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63266553A
Other languages
Japanese (ja)
Inventor
Takanobu Gidou
孝信 儀同
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63266553A priority Critical patent/JPH02113627A/en
Publication of JPH02113627A publication Critical patent/JPH02113627A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To decrease an offsetting voltage fluctuation and to attain the stable oscillation by providing an automatic level control circuit between the output of a voltage control oscillator and the input of a phase comparator. CONSTITUTION:The title oscillator has a voltage control oscillator 1 to respond to a control signal, a reference signal source 3, a phase comparator 2 to compare the voltage control oscillator with the output phase of the reference signal source 3 and a loop filter 4 to filter the output of the phase comparator 2 and generate the control voltage. An automatic level control circuit 5 is provided between the output of the voltage control oscillator 1 and the input of the phase comparator 2. Consequently, the input level from the voltage control oscillator 1 to the phase comparator 2 is automatically controlled, held to a constant value, and the output level fluctuation of the voltage control oscillator 1, namely, the input level fluctuation to the phase comparator 2 can be eliminated. Thus, the offsetting voltage fluctuation is decreased, the phase synchronization is more stably maintained and the stable oscillation can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はアナログ形位相同期発振器に関し、特に高安定
の位相同期発振器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog type phase-locked oscillator, and particularly to a highly stable phase-locked oscillator.

〔従来の技術〕[Conventional technology]

従来、この種のアナログ形位相同期発振器は、第3図の
ように電圧制御発振器(VCO)1からの一出力を直接
位相比較器(サンプリング・)エイズ・ディテクタ:5
PD)2に入力して基準信号源3からの出力と位相比較
し、これらの位相誤差に対応する位相比較器2からの出
力(誤差出力)をループフィルタ4でろ波して電圧制御
発振器1の周波数制御電圧入力端子に印加するように構
成している。
Conventionally, this type of analog phase synchronized oscillator has been used to directly connect one output from a voltage controlled oscillator (VCO) 1 to a phase comparator (sampling) and an aids detector 5 as shown in FIG.
PD) 2 and compares the phase with the output from the reference signal source 3, and the output (error output) from the phase comparator 2 corresponding to these phase errors is filtered by the loop filter 4 and output from the voltage controlled oscillator 1. It is configured to be applied to a frequency control voltage input terminal.

[発明が解決しようとする課題] 上述した従来のアナログ形位相同期発振器では、位相誤
差が零の場合でも位相比較器2内のアンバランスにより
、また誤差出力が零の場合でもループフィルタ内のオペ
アンプ等の不完全性により、電圧制御発振器1の周波数
制御電圧入力端子には零でない電圧が入力される。その
結果、系はこの電圧(オフセット電圧)を基準中心電圧
として、系に固有でその範囲で位相同期の維持が可能な
制御電圧範囲(ホールド・イン・レンジ)内で位相比較
特性を示す。
[Problems to be Solved by the Invention] In the conventional analog type phase-locked oscillator described above, even when the phase error is zero, the unbalance in the phase comparator 2 causes an imbalance in the operational amplifier in the loop filter even when the error output is zero. Due to such imperfections, a non-zero voltage is input to the frequency control voltage input terminal of the voltage control oscillator 1. As a result, the system exhibits phase comparison characteristics within a control voltage range (hold-in range) that is unique to the system and within which phase synchronization can be maintained, using this voltage (offset voltage) as the reference center voltage.

このオフセット電圧は、特に温度変動を誘因として構成
部品の初期特性の変動が発生し、位相比較器へ入力する
電圧制御発振器の出力レベルが−定しないために変動す
る。この様子の典型的な一例をグラフ化したものが第4
図である。図では、位相比較器の入力レベル変動(ΔP
vco)に対するオフセット電圧変動(ΔVoFF )
を示している。
This offset voltage fluctuates because the initial characteristics of the components change, particularly due to temperature fluctuations, and the output level of the voltage controlled oscillator input to the phase comparator is not constant. The fourth graph shows a typical example of this situation.
It is a diagram. In the figure, the input level fluctuation of the phase comparator (ΔP
Offset voltage variation (ΔVoFF) with respect to vco)
It shows.

このオフセント電圧の変動分がホールド・イン・レンジ
を越えると、位相同期外れを生ずる。従って系の位相同
期を維持するためには、オフセット電圧の変動をホール
ド・イン・レンジ等で規定される値以下Gこ抑えなけれ
ばならないが、そのオフセット電圧変動の最大要因のひ
とつである、位相比較器の入力レベル、即ち電圧制御発
振器の出力レベルの変動は温度変化や予測困難な内外部
要因のため回避できないという問題がある。
If this offset voltage variation exceeds the hold-in range, phase synchronization will occur. Therefore, in order to maintain the phase synchronization of the system, it is necessary to suppress the offset voltage fluctuation by G below the value specified by the hold-in range, etc., but one of the biggest causes of offset voltage fluctuation is the phase There is a problem in that fluctuations in the input level of the comparator, that is, the output level of the voltage controlled oscillator, cannot be avoided due to temperature changes and other internal and external factors that are difficult to predict.

本発明はオフセット電圧変動を軽減して安定な発振を可
能とする位相同期発振器を捉供することを目的とする。
An object of the present invention is to provide a phase-locked oscillator that reduces offset voltage fluctuations and enables stable oscillation.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の位相同期発振器は制御信月に応答する電圧制御
発振器と、基準信号源と、電圧制御発振器および基準信
号源の出力位相を比較する位相比較器と、前記位相比較
器の出力をろ波して前記制御電圧を発生ずるループフィ
ルタを有し、更に、前記電圧制御発振器の出力と前記位
相比較器の入力の間に設けられた自動し・\ル制?i1
1回路を有する。
The phase-locked oscillator of the present invention includes a voltage-controlled oscillator that responds to a control signal, a reference signal source, a phase comparator that compares the output phases of the voltage-controlled oscillator and the reference signal source, and a filter that filters the output of the phase comparator. and a loop filter for generating the control voltage, and further includes an automatic loop filter provided between the output of the voltage controlled oscillator and the input of the phase comparator. i1
It has one circuit.

〔作用〕[Effect]

子連した構成では、電圧制御発振器から位相比較器への
入力レベルを自動制御して−・定植に保持し、電圧制御
発振器の出力レベル変動、即ら位相比較器への入力レベ
ル変動をなくしてオフセノ]・電圧変動を軽減する。
In a serial configuration, the input level from the voltage controlled oscillator to the phase comparator is automatically controlled and maintained at a fixed level, eliminating fluctuations in the output level of the voltage controlled oscillator, that is, fluctuations in the input level to the phase comparator. Offseno] - Reduces voltage fluctuations.

〔実施例] 次に、本発明を図面を参照L2で説明する。〔Example] Next, the present invention will be explained with reference to the drawings L2.

第1図は本発明のブロック構成図を示す。図において、
1は電圧制御発振器、2は位相比較器、3は基準信号源
、4はループフィルタであり、これらで位相同期発振器
を構成している。そして、前記電圧制御発振器1と位相
比較器2との間に自動レベル制御回路(AI、C)5を
接続し、電圧制御発振器1から生じる位相比較器2の入
力信号レベルを一定に保っている。位相比較器2へは基
準信号源3から位相比較の基準となる信号が入力され、
かつ位相比較器2の出力はループフィルタ4によりろ波
して電圧制御発振器1に帰還している。
FIG. 1 shows a block diagram of the present invention. In the figure,
1 is a voltage controlled oscillator, 2 is a phase comparator, 3 is a reference signal source, and 4 is a loop filter, which together constitute a phase synchronized oscillator. An automatic level control circuit (AI, C) 5 is connected between the voltage controlled oscillator 1 and the phase comparator 2 to keep the input signal level of the phase comparator 2 generated from the voltage controlled oscillator 1 constant. . A signal serving as a reference for phase comparison is inputted to the phase comparator 2 from a reference signal source 3.
The output of the phase comparator 2 is filtered by a loop filter 4 and fed back to the voltage controlled oscillator 1.

第2図は第1図の構成をより具体的に示すブロック図で
あり、第1図に示した自動レベル制御回路5を、レベル
検出器(DET)6と、増幅器7と、PINダイオード
減衰器(PIN  ATT)8とで構成している。即ち
、電圧制御発振器1から位相比較器2へ向かう信号は、
レベル検出器6での入力レベルが一定となるようPTN
ダイオード減衰器8により制御される。
FIG. 2 is a block diagram showing the configuration of FIG. 1 in more detail, in which the automatic level control circuit 5 shown in FIG. (PIN ATT)8. That is, the signal going from the voltage controlled oscillator 1 to the phase comparator 2 is
PTN so that the input level at level detector 6 is constant.
Controlled by a diode attenuator 8.

この構成によれば、電圧制御発振器1から位相比較器2
に入力される信号のレベルは自動レベル制御回路5によ
って自動制御されて一定値に保持される。このため、構
成部品の経年変化や温度変化等によって生ずる電圧制御
発振器1の出力レベル変動、即ち位相比較器2への入力
レベル変動をなくし、オフセット電圧変動を軽減し、位
相同期を安定に維持した発振を得ることができる〔発明
の効果〕 以上説明したよう乙こ本発明は電圧制御発振器から位相
比較器への入力レベルを自動制御して一定値に保持して
いるので、電圧制御発振器の出力レベル変動、即ち位相
比較器への入力レベル変動をなくすことができ、これに
よりオフセット電圧変動を著しく軽減し、位相同期をよ
り安定に維持して安定な発振を得ることができる効果が
ある。
According to this configuration, from the voltage controlled oscillator 1 to the phase comparator 2
The level of the signal input to is automatically controlled by the automatic level control circuit 5 and held at a constant value. For this reason, fluctuations in the output level of the voltage controlled oscillator 1 that occur due to aging or temperature changes in the components, that is, fluctuations in the input level to the phase comparator 2, are eliminated, offset voltage fluctuations are reduced, and phase synchronization is maintained stably. Oscillation can be obtained [Effects of the Invention] As explained above, the present invention automatically controls the input level from the voltage controlled oscillator to the phase comparator and maintains it at a constant value. Level fluctuations, that is, input level fluctuations to the phase comparator can be eliminated, which has the effect of significantly reducing offset voltage fluctuations, maintaining phase synchronization more stably, and obtaining stable oscillation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明によるアナログ形位相同期発振器の実施
例を示すブロック図、第2図は第1図の構成を具体的に
示すブロック図、第3図は従来のアナログ形位相同期発
振器のブロック図、第4Mは位相比較器の入力レベル変
動に対するオフセット電圧変動を示すグラフである。 1・・・電圧制御発振器(VCO) 、2・・・位相比
較器(SPD)、3・・・基準信3源、4・・・ループ
・フィルタ、5・・・自動レベル制御回路(DET)、
6・・・レベル検出器(DET)、7・・・増幅器、8
・・・PIχ −一 八  〇
FIG. 1 is a block diagram showing an embodiment of an analog phase-locked oscillator according to the present invention, FIG. 2 is a block diagram specifically showing the configuration of FIG. 1, and FIG. 3 is a block diagram of a conventional analog phase-locked oscillator. Figure 4M is a graph showing offset voltage fluctuations with respect to input level fluctuations of the phase comparator. 1...Voltage controlled oscillator (VCO), 2...Phase comparator (SPD), 3...3 reference signal sources, 4...Loop filter, 5...Automatic level control circuit (DET) ,
6...Level detector (DET), 7...Amplifier, 8
...PIχ -180

Claims (1)

【特許請求の範囲】[Claims] 1、制御信号に応答する電圧制御発振器と、基準信号源
と、前記電圧制御発振器および基準信号源の出力位相を
比較する位相比較器と、前記位相比較器の出力をろ波し
て前記制御信号を発生するループフィルターとを有する
位相同期発振器において、前記電圧制御発振器の出力と
前記位相比較器の入力間に自動レベル制御回路を設けた
ことを特徴とする位相同期発振器。
1. A voltage controlled oscillator that responds to a control signal, a reference signal source, a phase comparator that compares the output phases of the voltage controlled oscillator and the reference signal source, and filters the output of the phase comparator to detect the control signal. A phase-locked oscillator having a loop filter that generates a voltage-controlled oscillator, characterized in that an automatic level control circuit is provided between the output of the voltage-controlled oscillator and the input of the phase comparator.
JP63266553A 1988-10-22 1988-10-22 Phase synchronizing oscillator Pending JPH02113627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63266553A JPH02113627A (en) 1988-10-22 1988-10-22 Phase synchronizing oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63266553A JPH02113627A (en) 1988-10-22 1988-10-22 Phase synchronizing oscillator

Publications (1)

Publication Number Publication Date
JPH02113627A true JPH02113627A (en) 1990-04-25

Family

ID=17432445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63266553A Pending JPH02113627A (en) 1988-10-22 1988-10-22 Phase synchronizing oscillator

Country Status (1)

Country Link
JP (1) JPH02113627A (en)

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