JPH02113468U - - Google Patents
Info
- Publication number
- JPH02113468U JPH02113468U JP2136589U JP2136589U JPH02113468U JP H02113468 U JPH02113468 U JP H02113468U JP 2136589 U JP2136589 U JP 2136589U JP 2136589 U JP2136589 U JP 2136589U JP H02113468 U JPH02113468 U JP H02113468U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- video signal
- delay circuit
- adds
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Picture Signal Circuits (AREA)
Description
第1図は本考案の一実施例の画質補正回路を示
すブロツク図、第2図は第1図の回路各部の周波
数特性を説明する説明図、第3図は従来の画質補
正回路を示すブロツク図、第4図は第3図の回路
各部の信号波形図、第5図は第3図のデイレイラ
インのゲイン及びデイレイタイムの周波数特性を
説明する説明図、第6図は第3図の画質補正回路
の周波数特性を説明する説明図である。
1……入力端子、2,3……デイレイライン、
4,6,7……重み付け回路、5,9……加算回
路、8…減算回路、10……出力端子。
Fig. 1 is a block diagram showing an image quality correction circuit according to an embodiment of the present invention, Fig. 2 is an explanatory diagram explaining the frequency characteristics of each part of the circuit in Fig. 1, and Fig. 3 is a block diagram showing a conventional image quality correction circuit. Figure 4 is a signal waveform diagram of each part of the circuit in Figure 3, Figure 5 is an explanatory diagram explaining the delay line gain and delay time frequency characteristics in Figure 3, and Figure 6 is the image quality of Figure 3. FIG. 3 is an explanatory diagram illustrating frequency characteristics of a correction circuit. 1...Input terminal, 2, 3...Delay line,
4, 6, 7... Weighting circuit, 5, 9... Addition circuit, 8... Subtraction circuit, 10... Output terminal.
Claims (1)
する第1の遅延回路と、 この第1の遅延回路からビデオ信号を所定量遅
延する第2の遅延回路と、 前記第1、第2の遅延回路の持つ帯域特性と同
等な帯域特性を有し、前記の入力として供給され
るビデオ信号を通過させる低域通過フイルタと、 この低域通過フイルタを通したビデオ信号と前
記第2の遅延回路からのビデオ信号とを加算する
第1の加算回路と、 この第1の加算回路からの加算信号の振幅を1
/2にする重み付け手段と、 前記第1の遅延回路からのビデオ信号より前記
重み付け手段からの信号を減算し、二次微分信号
を得る減算回路と、 この減算回路からの二次微分信号と前記第1の
遅延回路からのビデオ信号を加算し、輪郭補正さ
れたビデオ信号を得る第2の加算回路と を具備したことを特徴とする画質補正回路。[Claims for Utility Model Registration] A first delay circuit that delays a video signal supplied as an input by a predetermined amount; a second delay circuit that delays a video signal from the first delay circuit by a predetermined amount; 1. A low-pass filter that has a band characteristic equivalent to that of the second delay circuit and that passes the video signal supplied as the input, and a video signal that has passed through this low-pass filter and the a first addition circuit that adds the video signal from the second delay circuit; and a first addition circuit that adds the video signal from the second delay circuit;
/2; a subtraction circuit for subtracting the signal from the weighting means from the video signal from the first delay circuit to obtain a second-order differential signal; a second-order differential signal from the subtraction circuit; An image quality correction circuit comprising: a second addition circuit that adds video signals from the first delay circuit to obtain a contour-corrected video signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2136589U JPH02113468U (en) | 1989-02-28 | 1989-02-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2136589U JPH02113468U (en) | 1989-02-28 | 1989-02-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02113468U true JPH02113468U (en) | 1990-09-11 |
Family
ID=31238544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2136589U Pending JPH02113468U (en) | 1989-02-28 | 1989-02-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02113468U (en) |
-
1989
- 1989-02-28 JP JP2136589U patent/JPH02113468U/ja active Pending
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