JPH02101698U - - Google Patents
Info
- Publication number
- JPH02101698U JPH02101698U JP943889U JP943889U JPH02101698U JP H02101698 U JPH02101698 U JP H02101698U JP 943889 U JP943889 U JP 943889U JP 943889 U JP943889 U JP 943889U JP H02101698 U JPH02101698 U JP H02101698U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- difference
- phase shift
- delay means
- signal output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010363 phase shift Effects 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案になる疑似サラウンド回路の一
実施例のブロツク図、第２図は従来の疑似サラウ
ンド回路のブロツク図である。
１……位相シフト回路、２……減算器、３……
ローパスフイルタ、４……遅延回路。
FIG. 1 is a block diagram of an embodiment of a pseudo surround circuit according to the present invention, and FIG. 2 is a block diagram of a conventional pseudo surround circuit. 1... Phase shift circuit, 2... Subtractor, 3...
Low-pass filter, 4...Delay circuit.
Claims (1)
ヤンネル信号を位相シフトする位相シフト手段と
、該位相シフト信号と他方のチヤンネル信号との
差信号を得る減算手段と、該差信号を所定時間遅
延する遅延手段とを備え、 前記減算手段の出力する差信号と遅延手段の出
力する遅延信号とを左右のサラウンド信号として
出力することを特徴とする疑似サラウンド回路。[Claims for Utility Model Registration] A phase shift means for phase shifting one channel signal of an input signal consisting of two left and right channels, a subtraction means for obtaining a difference signal between the phase shift signal and the other channel signal, and the difference. 1. A pseudo surround circuit, comprising: delay means for delaying a signal for a predetermined time; and outputting a difference signal output from the subtraction means and a delayed signal output from the delay means as left and right surround signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP943889U JPH02101698U (en) | 1989-01-31 | 1989-01-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP943889U JPH02101698U (en) | 1989-01-31 | 1989-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02101698U true JPH02101698U (en) | 1990-08-13 |
Family
ID=31216178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP943889U Pending JPH02101698U (en) | 1989-01-31 | 1989-01-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02101698U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02139796A (en) * | 1988-11-18 | 1990-05-29 | Toshiba Corp | Semiconductor integrated circuit |
-
1989
- 1989-01-31 JP JP943889U patent/JPH02101698U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02139796A (en) * | 1988-11-18 | 1990-05-29 | Toshiba Corp | Semiconductor integrated circuit |
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