JPH02112023U

JPH02112023U -

Info

Publication number: JPH02112023U
Application number: JP2009289U
Authority: JP
Priority date: 1989-02-21
Filing date: 1989-02-21
Publication date: 1990-09-07

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例である受信装置１の
簡略化した電気的構成を示すブロツク図、第２図
はＲＡＭ１３のメモリ領域を示す図、第３図は制
御回路１０の制御動作を示すメインプログラムの
フローチヤート、第４図はオートプリセツト機能
の制御動作を示すフローチヤートである。１……受信装置、２……アンテナ、３……高周
波同調増幅回路、４……混合回路、５……局部発
振回路、６……中間周波増幅回路、１０……制御
回路、１１……ローパスフイルタ回路、１２……
フエーズロツクトループ周波数シンセサイザ、１
３……ＲＡＭ、１４……帯域変換スイツチ、１６
……オートプリセツト専用操作スイツチ、Ｍ１〜
Ｍ８……サブメモリ、Ｆ１，Ｆ２……フラグ、Ｍ
ｉ１〜Ｍｉ１０，ｉ：１〜６……ストア領域、Ｎ
……分周比。 FIG. 1 is a block diagram showing a simplified electrical configuration of a receiving device 1 which is an embodiment of the present invention, FIG. 2 is a diagram showing the memory area of the RAM 13, and FIG. 3 is a diagram showing the control operation of the control circuit 10. FIG. 4 is a flowchart showing the control operation of the auto preset function. DESCRIPTION OF SYMBOLS 1...Receiving device, 2...Antenna, 3...High frequency tuned amplifier circuit, 4...Mixing circuit, 5...Local oscillation circuit, 6...Intermediate frequency amplifier circuit, 10...Control circuit, 11...Low pass Filter circuit, 12...
Phaselock loop frequency synthesizer, 1
3...RAM, 14...Band conversion switch, 16
...Auto preset dedicated operation switch, M1~
M8...Sub memory, F1, F2...Flag, M
i1 to Mi10, i:1 to 6...store area, N
...Dividing ratio.

Claims

[Claims for Utility Model Registration] (1) A receiving circuit capable of changing a receiving frequency, an operating switch, and a switch that sequentially changes the receiving frequency of the receiving circuit in response to an output of the operating switch. 1 control means; a detection means for detecting received field strength in response to the output of the receiving circuit; a first memory for storing a signal; a second memory for storing a signal in response to the output of the operation switch and representing the reception frequency immediately before the operation switch was operated; and a reception circuit for controlling the reception frequency stored in the first memory. a second control means for causing a reception operation; and in response to the output of the detection means, after the reception frequency of the reception circuit is changed over a predetermined reception frequency band by the first control means, the reception frequency of the reception circuit is changed over a predetermined reception frequency band; and third control means for bringing the receiving circuit into a receiving state at the receiving frequency stored in the second memory when reception with a receiving field strength equal to or greater than a value is not performed. . (2) In response to the output of the detection means, the first memory sequentially stores reception frequencies in which the reception field strength is greater than or equal to the predetermined value from the highest to the lowest. When, after the reception frequency of the receiving circuit is changed over a predetermined reception frequency band by the first control means, reception is performed with a reception field strength equal to or greater than the predetermined value; 2. The receiving device according to claim 1, further comprising fourth control means for tuning the receiving circuit to the receiving frequency at which the receiving field strength is the highest.